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1147

Converter Using Phase-Shifted PWM

Kui Wang, Member, IEEE, Lie Xu, Member, IEEE, Zedong Zheng, Member, IEEE, and Yongdong Li, Member, IEEE

converter is an attractive topology for high-power medium-voltage

motor drives. This paper presents a capacitor voltage-balancing

method for the 5L-ANPC converter, including the voltage balancing of dc-link capacitors and flying capacitors. In order to ensure

that the series-connected or high-voltage switches of the 5L-ANPC

converter are operated at fundamental frequency and the other

switches are operated at a constant switching frequency, phaseshifted pulse width modulation is used to control this converter. The

relationship between the average neutral-point current and zerosequence voltage is investigated, and an optimum zero-sequence

voltage is calculated to regulate the neutral-point potential. The

voltage across the flying capacitor is also regulated by adjusting

the switching duty cycles of two PWM signals, which varies the

operation time of redundant switching states in each switching period. Simulation and experimental results are presented to verify

the validity of this method.

Index TermsActive neutral-point clamped (ANPC), capacitor

voltage balancing, multilevel converter, phase-shifted pulse width

modulation (PWM), zero-sequence voltage.

I. INTRODUCTION

ULTILEVEL converters have been widely used in

high-voltage high-power applications since 1981 [1].

Among the existing multilevel converters, neutral-pointclamped (NPC), flying-capacitor (FC), and cascaded H-bridge

(CHB) multilevel converters are three classical multilevel

topologies that are the most widely used in the industry [2][7].

However, when the number of voltage levels increases, not only

the complexity to control the voltage across the dc-link capacitors in the NPC converter and the FCs in the FC converter, but

also the number of clamping diodes in the NPC converter, FCs

in the FC converter, and isolated transformer windings in the

CHB converter is greatly increased [8][10].

Modular multilevel converter (MMC) is an emerging multilevel converter topology which gains increasing attentions in

April 17, 2014. Date of publication April 29, 2014; date of current version

October 15, 2014. This paper was presented in part at the IEEE Energy Conversion Congress and Exposition, Denver, CO, USA, September 1519, 2013.

Recommended for publication by Associate Editor F. H. Khan.

K. Wang, L. Xu, and Z. Zheng are with the State Key Laboratory of

Power System, Department of Electrical Engineering, Tsinghua University,

Beijing 100084, China (e-mail: wangkui@tsinghua.edu.cn; xulie@tsinghua.

edu.cn; zzd@tsinghua.edu.cn).

Y. Li is with the Department of Electrical Engineering, Tsinghua University,

Beijing, China, and also with the School of Electrical Engineering, Xinjiang

University, Urumqi 830046, China (e-mail: liyd@tsinghua.edu.cn).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2014.2320985

half-bridges without transformer and the output voltage can

reach to hundreds of kilovolts. The most successful commercial

application of MMC is in high-voltage direct-current (HVDC)

transmissions [15][17]. When used in medium-voltage motor

drives, it suffers from low-frequency fluctuation in the floating

capacitors [12]. Therefore, the MMC would not be suitable for

constant-torque loads that require the rated torque in a low-speed

region.

Five-level active neutral-point clamped (ANPC) converter is

an attractive multilevel topology, which is more suitable for

high-performance medium-voltage motor drives [18][25]. Its

dc-link is subdivided into two parts and only four switches and

one FC are needed for clamping per phase; hence, the costs, volume, and control complexity can be reduced. The main problem

of this topology is the unequal voltage stresses of switches and

voltage balancing of the dc-link and FCs [19][23].

A new four-quadrant medium-voltage drive using this fivelevel ANPC topology is described in [19]. The direct torque

control method based on space-vector PWM (SVPWM) is used

to control this converter. A proper combination of three-phase

switching states is selected to produce the voltage vectors to

regulate the desired output voltage and balance the neutralpoint (NP) potential and FC voltages while maintaining the

same line voltage. However, the large number of redundant

voltage vectors and redundant switching states makes the control

method fairly complex. A five-level virtual-flux direct power

control for the five-level ANPC converter was implemented

in [20]. The switching frequency of the series-connected or

high-voltage switches is higher than the fundamental frequency,

which will increase the switching losses.

A phase-disposition PWM (PD-PWM) with zero-sequence

voltage injection method was proposed in [21] to control the NP

potential of the 5L-ANPC converter. The redundant switching

states are utilized to control the voltages across the FCs. However, the calculation and selection of zero-sequence voltage is

very complex and the switching frequency is not constant for

the outside switches with PD-PWM. In [22], a control strategy

based on selective harmonic elimination PWM was proposed

and the voltage across the FCs was balanced by swapping the

switching patterns. The NP voltage was regulated by adding

or subtracting a relatively small pulse to the switching pulse

signals [22], [23]. This method is very suitable for the highpower and low switching-frequency applications. However, the

voltage regulation ability is not strong due to the low switching

frequency and the capacitor voltage ripple will be high.

This paper focuses on the voltage-balancing issue of the 5LANPC converter, including the voltage balancing of dc-link

0885-8993 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

1148

TABLE I

SWITCHING STATES OF THE 5L-ANPC CONVERTER

Fig. 1.

switches are operated at fundamental frequency and the other

switches are controlled with PS-PWM, which can minimize the

higher silicon demand of the converter and lower the switching

losses. In order to balance the NP potential, the relationship between the average NP current and zero-sequence voltage under

PS-PWM is discussed and an optimal zero-sequence voltage

can be obtained easily. The voltage balancing of the FCs is also

achieved by adjusting the switching duty cycles of two PWM

signals slightly, which essentially varies the operation time of

the redundant switching states in each switching period. With

this method, the voltage-balancing control of the NP and FCs are

decoupled. The NP potential and FC voltages can be controlled

to a given value precisely and rapidly.

This paper is organized in the following way. In Section II,

the operating principles of the 5L-ANPC converter and the modulation method are introduced first. The NP potential-balancing

method based on zero-sequence voltage injection is discussed

in Section III, and the voltage balancing of FCs is discussed

in Section IV. In Section V, simulation and experimental results are presented to validate the proposed method, and finally,

conclusions are summarized in Section VI.

II. OPERATING PRINCIPLES AND MODULATION METHOD

A single phase of the 5L-ANPC converter is shown in Fig. 1.

Each phase of this converter consists of eight switches and an

FC. If the voltage across the FC is assumed constant and is

equal to Uc , then the voltages across the upper and lower dclink capacitors are 2Uc . So Sx3 , Sx3 , Sx4 , and Sx4 require two

switches connected in series or high-voltage switches to bear a

higher voltage 2Uc . All the switching states V0V7 are listed

in Table I, where x represents phase (a, b, or c), if x and iNPx

are the corresponding FC current and NP current and iox is the

phase current. Since (Sx1 , Sx1 ), (Sx2 , Sx2 ), (Sx3 , Sx3 ), and (Sx4 ,

Sx4 ) are complementary switch pairs and Sx3 and Sx4 require

the same switching signal, only Sx1 Sx4 are given in Table I.

The NP of the dc-link is referred as the zero potential.

From Table I, it can be seen that Sx3 and Sx4 are turned

OFF when the output voltage is negative and turned ON when

the output voltage is positive. So the series-connected or highvoltage switch pairs (Sx3 , Sx3 ) and (Sx4 , Sx4 ) can be operated

at fundamental frequency based on the polarity of the phase

voltage. The other switch pairs (Sx1 , Sx1 ), (Sx2 , Sx2 ) together

phase, so classic PS-PWM can be used to control the switch

pairs (Sx1 , Sx1 ) and (Sx2 , Sx2 ).

Defining the switching functions of switches Sx1 Sx3 be

Sf x1 Sf x3 , respectively, the instantaneous output voltage Vox

can be written as

Vox = [2 (Sf x3 1) + Sf x2 + Sf x1 ] Uc .

(1)

the output phase voltage is [2, 2]. In order to operate Sx3 at

fundamental frequency, Sf x3 can be decided as follows:

1, 0 uox 2

Sf x3 =

(2)

0, 2 uox 0

where uox is the reference output phase voltage. Then the reference modulation voltage urefx of (Sx1 , Sx1 ) and (Sx2 , Sx2 ) can

be written as follows:

uox /2,

Sf x3 = 1

urefx =

(3)

(uox + 2)/2, Sf x3 = 0.

The diagram of PS-PWM used for the 5L-ANPC converter

is shown in Fig. 2. The carrier signals for switches Sx1 and Sx2

are two triangular waves phase shifted by 180o . The resulting

PWM signals are switching functions Sf x1 and Sf x2 to control

the corresponding switches.

III. VOLTAGE BALANCING OF THE DC-LINK CAPACITORS

A. Modeling of the Average NP Current

From Fig. 1 and Table I, it can be seen that the load current

flows out of the NP when Sx3 and Sx2 are switched ON or Sx3

and Sx2 are switched ON. So the instantaneous NP current iNPx

can be written as

(1 Sf x2 ) iox , Sf x3 = 1

iNPx =

(4)

Sf x3 = 0

Sf x2 iox ,

If the carrier frequency is higher enough than the fundamental frequency, then the reference modulation voltage and phase

current can be assumed constant in a carrier period. So the duty

ratio of Sf x1 and Sf x2 in a carrier period is equal to the reference modulation voltage urefx . Based on (2)(4), the average

WANG et al.: CAPACITOR VOLTAGE BALANCING OF A FIVE-LEVEL ANPC CONVERTER USING PHASE-SHIFTED PWM

1149

iNP = (um ax im ax + um id im id um in im in )/2

(9)

to um in , um id , and um ax .

After zero-sequence voltage injection, the average NP current

can be written as

= iNP (im ax + im id im in ) uz /2.

(10)

iNP = (um ax im ax um id im id um in im in )/2. (11)

After zero-sequence voltage injection, the average NP current

can be written as

= iNP (im ax im id im in ) uz /2.

Fig. 2.

as

(1 uox /2) iox , 0 uox 2

(5)

iNPx =

(1 + uox /2) iox , 2 uox 0.

Then, the total average NP current is

iNP = iNPa + iNPb + iNPc

= (ioa + iob + ioc ) (|uoa | ioa + |uob | iob + |uoc | ioc )/2.

(6)

For a three-phase three-wire system, there exists ioa + iob +

io c = 0. So (6) can be written as

iNP = (|uoa | ioa + |uob | iob + |uoc | ioc )/2.

(7)

B. NP Potential-Balancing Method

As a most important freedom degree in the carrier-based

PWM, zero-sequence voltage does not influence the output line

voltage and current. It leads to different pulse patterns and so

results to different NP currents [26]. If a zero-sequence voltage

uz is injected into the three-phase reference voltages, the actual

phase voltage and reference modulation voltage can be written

as

uox = uox + uz

(8)

urefx = urefx + uz /2.

In order to operate the series-connected or high-voltage

switches at fundamental frequency, the polarity of the initial

three-phase voltages cannot be changed after zero-sequence

voltage injection. Defining the minimal, medium, and maximal values of uoa , uob , and uoc be um in , um id , and um ax ,

respectively, since um ax + um id + um in = 0, there must exist

um ax > 0 and um in < 0, only the polarity of um id is uncertain.

(12)

According to (10) and (12), the average NP current is linearly proportion to the zero-sequence voltage. In order to ensure the polarity of the three-phase voltages unchanged after

zero-sequence voltage injection, according to (8), the region of

zero-sequence voltages is limited to

uref ,m in uz /2 1 uref ,m ax

(13)

where uref ,m in and uref ,m ax are the minimal and maximal values

of uref a , uref b , and urefc , respectively. Then, the maximal and

minimal values of uz are

uz m ax = 2(1 uref ,m ax )

(14)

uz m in = 2uref ,m in .

The two boundary values of average NP current after zerosequence voltage injection can be calculated by plugging uz m ax

and uz m in into (10) or (12). According to the actual upper and

lower dc-link capacitor voltages, the demanded NP current that

is used to balance the NP potential can also be calculated easily

[21]

INP,ref = Cd

udc2 udc1

Ts

(15)

where Cd is the upper/lower dc-link capacitor and Ts is the carrier period. Suppose that the two boundary values corresponding

to uz m ax and uz m in are INP,m ax and INP,m in . Then, an optimum

zero-sequence voltage uz ref can be calculated by adopting the

linear interpolation algorithm

uz ref =

uz m ax uz m in

INP,ref

INP,m ax INP,m in

+

uz m in INP,m ax uz m ax INP,m in

.

INP,m ax INP,m in

(16)

With this optimum zero-sequence voltage uz ref , the NP potential can be balanced effectively with the most appropriate

NP current. The control block diagram of the NP potentialbalancing method is shown in Fig. 3.

1150

Fig. 3.

In order to balance the FC voltages, another freedom degree

of the 5L-ANPC converter is used: redundant switching states.

From Table I, it can be seen that the redundant switching states

for voltage levels Uc and Uc have different effects on the FCs.

The load current flows out of the FC when Sx2 and Sx1 are

switched ON and into it when Sx2 and Sx1 are switched ON. So

the instantaneous FC currents if x can be written as

if x = (Sf x1 Sf x2 ) iox .

(17)

if x = (dx1 dx2 ) iox

(18)

where dx1 and dx2 are the duty cycles of Sf x1 and Sf x2 in a carrier period, respectively. When using classic PS-PWM, dx1 and

dx2 are equal. So, under ideal and steady-state conditions, the

average FC current is zero and the FC voltage can be naturally

balanced. This characteristic can also be easily obtained in the

FC multilevel converter when PS-PWM is used [27][30]. However, it also may diverge under nonideal and dynamic conditions

if not controlled.

According to (18), a way to regulate the average FC current

is to adjust the duty cycles of Sf x1 and Sf x2 , which varies the

operation time of redundant switching states (V1, V2) or (V5,

V6) essentially. So the PS-PWM method should be modified

slightly to achieve this goal.

Taking Uf x > Uc and iox > 0 as an example, the FC needs to

be discharged. As shown in Fig. 4, there are two cases that should

be considered respectively: 0 urefx 1/2 and 1/2 urefx

1, but the consequences are the same. If the duty cycle of Sf x1

is decreased by t symmetrically, and the duty cycle of Sf x2

is increased by t symmetrically, the output voltage remains

unchanged, but the average FC current becomes negative and

Fig. 4.

can be written as

if x =

2t

iox .

Ts

(19)

WANG et al.: CAPACITOR VOLTAGE BALANCING OF A FIVE-LEVEL ANPC CONVERTER USING PHASE-SHIFTED PWM

1151

TABLE II

CIRCUIT PARAMETERS USED FOR SIMULATION

(b) FC voltages.

Fig. 5.

Sf x1 is increased by t symmetrically, and the duty cycle of

Sf x2 is decreased by t symmetrically, the average FC current

is positive

if cx =

2t

iox .

Ts

(20)

PI regulator or a hysteresis comparator. With this method, the

FC voltage can be balanced easily.

(b) FC voltages.

1152

Fig. 8. Simulation waveforms of zero-sequence voltage and reference modulation voltages: (a) m = 0.2; (b) m = 1.15.

Fig. 9. Dynamic simulation results with m = 0.2: (a) dc-link capacitor voltages and (b) three-phase FC voltages.

A. Simulation Results

Simulation results using MATLAB/Simulink are presented

to verify the proposed voltage-balancing method. The circuit

parameters used for simulation are summarized in Table II.

Figs. 58 show the performance of the proposed capacitor

voltage-balancing method under steady states with different

modulation indices. Fig. 5 shows the phase voltage and line

voltage with the modulation index m = 0.8. The phase voltage

has five levels and the line voltage has nine levels. Fig. 6 shows

the voltages across the dc-link capacitors and FCs with m = 0.2,

and Fig. 7 shows the voltages across the dc-link capacitors and

FCs with m = 0.8. The capacitor voltages under different conditions are all balanced with the proposed voltage-balancing

method.

Fig. 8 shows the waveforms of zero-sequence voltage and

reference modulation voltages before and after zero-sequence

voltage injection. When the modulation index is very small,

according to (13), the span of the zero-sequence voltage is very

wide. When the modulation index reaches to the maximal value

of 1.15, the span of the available uz is very small and the primary

which will make the voltage-balancing effect not so well.

In order to demonstrate the dynamic performance of the

voltage-balancing method, Figs. 9 and 10 give the simulation results under dynamic states with m = 0.2 and m = 0.8,

respectively.

As can be seen from Figs. 9(a) and 10(a), the upper and

lower dc-link capacitor voltages are controlled balanced first

and, suddenly at t = 2 s, are set to 5% higher and lower than

the nominal value. The two voltages diverge and stabilize at the

given values rapidly. At t = 6 s, the dc-link capacitor voltages

are controlled back to the nominal value and balanced again.

The situation is similar for the FCs. The three-phase FC voltages are controlled to 1/4 of the dc-link voltage at first and,

suddenly at t = 2 s, are set to 20% higher than, equal to, and

20% lower than the nominal value, respectively. As shown in

Figs. 9(b) and 10(b), the three voltages diverge and gradually

stabilize at the new given values. At t = 6 s, the three voltages

are controlled and balanced again.

WANG et al.: CAPACITOR VOLTAGE BALANCING OF A FIVE-LEVEL ANPC CONVERTER USING PHASE-SHIFTED PWM

Fig. 11.

1153

Experimental prototype.

Fig. 10. Dynamic simulation results with m = 0.8: (a) dc-link capacitor voltages and (b) three-phase FC voltages.

B. Experimental Results

A low-power three-phase 5L-ANPC converter prototype has

been built up to verify the proposed control method, as shown

in Fig. 11. The circuit parameters are the same as the simulation

parameters in Table II. In the experiments, the capacitor voltage

control method is investigated with various modulation indices.

For the voltage-balancing control of FCs, the time width t is

set to 20% of the initial time width in the experiments.

Fig. 12 shows the experimental results of the phase voltage,

line voltage, and phase current with modulation index m = 0.8.

Figs. 13 and 14 present the steady-state voltage waveforms of

dc-link capacitors and FCs with modulation indices m = 0.2

and m = 0.8, respectively. It can be seen that the voltages of

dc-link capacitors and FCs are all well balanced. The voltage

ripples increase with the load current.

Fig. 15 shows the dynamic-state waveforms of load changes

from full load to half load and then to full load again with

m = 0.2 and m = 0.8. It can be seen that the dc-link and FC

voltages remain stable during the whole process.

Fig. 16 shows the dynamic-state waveforms when the capacitor voltages are controlled to different values. The voltages

of dc-link capacitors and FCs are controlled balanced at the

Fig. 12. Experimental results of (a) phase voltage (100 V/div), (b) phase to

phase voltage (200 V/div), and (c) phase current (5 A/div).

1154

Fig. 15. Experimental results of load step changes with (a) m = 0.2 and

(b) m = 1.0. From top to bottom: phase current (10 A/div), dc-link capacitor

voltages (25 V/div), and FC voltages (25 V/div).

Fig. 13. Experimental results of (a) dc-link capacitor voltages (2.5 V/div) and

(b) three-phase FC voltages (1 V/div) with m = 0.2.

Fig. 14. Experimental results of (a) dc-link capacitor voltages (2.5 V/div) and

(b) three-phase FC voltages (1 V/div) with m = 0.8.

and three-phase FC voltages (10 V/div) with (a) m = 0.2 and (b) m = 0.8.

WANG et al.: CAPACITOR VOLTAGE BALANCING OF A FIVE-LEVEL ANPC CONVERTER USING PHASE-SHIFTED PWM

voltages are set to 5% higher and 5% lower than the nominal

value. The FC voltages are set to 20% higher than, equal to, and

20% lower than the nominal value. All the capacitor voltages

gradually stabilize at the new given values. At about t = 6.5 s,

all the capacitor voltages are set back to the nominal values and

balanced again with the proposed voltage-balancing method.

The above simulation and experimental results demonstrate

that the proposed voltage-balancing method has an effective and

powerful control to the NP potential and FC voltages.

VI. CONCLUSION

A capacitor voltage-balancing method for the 5L-ANPC converter using PS-PWM is proposed in this paper. The seriesconnected or high-voltage switches can be operated at fundamental frequency and the other switches are operated at the

same constant switching frequency. The voltage balancing of

dc-link capacitors is achieved by zero-sequence voltage injection. The relationship between the average NP current and the

zero-sequence voltage is discussed, and it can be concluded that

the average NP current is linearly proportional to the zerosequence voltage under PS-PWM. So, an optimum zerosequence voltage can be calculated to regulate the dc-link capacitor voltages. The voltages across the FCs are regulated by

adjusting the duty cycles of the PWM signals, which essentially

varies the operation time of redundant switching states in each

switching period. Simulation and experimental results verify the

validity of this method.

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1156

He received the B.S. and Ph.D. degrees in electrical

engineering from the Department of Electrical Engineering, Tsinghua University, Beijing, China, in 2006

and 2011, respectively.

He is currently a Faculty Member with the

Department of Electrical Engineering, Tsinghua

University. His research interests include multilevel converters, control of power converters, and

adjustable-speed drives.

in 1980. He received the B.S. and Ph.D. degrees

in electrical engineering from the Department of

Electrical Engineering, Tsinghua University, Beijing,

China, in 2003 and 2008, respectively.

He is currently a Faculty Member with the Department of Electrical Engineering, Tsinghua University.

His research interests include power electronics converters and high-performance motor control systems.

He received the B.S. degree in electrical and electronic engineering from the Beijing University of

Aeronautics and Astronautics, Beijing, in 2003, and

the M.S. and Ph.D. degrees from The University of

Nottingham, Nottingham, U.K., in 2004 and 2008,

respectively.

From 2008 to 2010, he was a Research Fellow with

the Department of Electrical and Electronic Engineering, The University of Nottingham. He is currently

a Faculty Member with the Department of Electrical

Engineering, Tsinghua University, Beijing. His research interests include multilevel techniques, multilevel converters, direct acac power conversion, and

multilevel matrix converter.

1962. He received the B.S. degree from the Harbin Institute of Technology, Harbin, China, in 1982, and the

M.S. and Ph.D. degrees from the Department of Electrical Engineering, Institut National Polytechnique

de Toulouse, Toulouse, France, in 1984 and 1987,

respectively.

Since 1996, he has been a Professor with the Department of Electrical Engineering, Tsinghua University, Beijing, China. He was also an Invited Professor

with the Institut National Polytechnique de Toulouse

and the Dean of the School of Electrical Engineering, Xinjiang University,

Urumqi, China. His research interests include power electronics, machine control, and wind power generation.

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