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Buradasnz: Ana Sayfa WEBS Courses Undergraduate ELE413 VLSI 1

Groups 20092010 Students Burak Budanur Latchup Latch-up in CMO

Latch-up in CMOS Integrated Circuits

Latch-up in CMOS Integrated Circuits
Outline:
1.

Introduction

2.

Explanation of the phenomena

3.

Preventing latch-up

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Report A Problem

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4.

Conclusion

5.

References

Gir
Kullanc smi

Parola

1. Introduction

In CMOS fabrication, latch-up is a malfunction which can occur as a result

Latch-up in a CMOS integrated circuit, causes unintended currents will possibly res
destruction of the entire circuit, thus, it must be prevented.
Gir

Parolanz

2. Explanation of the phenomena

unuttunuz mu?
Yeni kullanc

Figure 1 shows the cross section of a two-transistor CMOS integrated circu

on the left hand side and the pMOS on the right hand side. As it can be seen from

msnz?

about a parasitic pnp transistor from source of the pMOS to the p-substrate. Furthe

transistor is formed from source of the nMOS, p-substrate and the n-well. These pa

finite resistances of n-well and p-substrate can be shown like Figure 2 [1]. Equivale
parasitic bipolar transistors is given in Figure 3 [1].

Figure 1 Cross section of a CMOS IC

Figure 2 Parasitic bipolar transistors in a CMOS process

Figure 3 Equivalent circuits formed by the parasitic transistors

As it can be clearly seen from the equivalent circuit, there is a positive fee

and Q2. If a parasitic current flows through the node X and raise V x, Q2 turns on a

resulting VY decrease. This increases IC1 and consequently Vx increases much more

equal to or greater than unity, this situation continues until an enormous current fl
in other words, until the circuit is latched up. [1]

3. Preventing Latch-up

As explained above, the loop gain of the equivalent circuit shown in Figure

unity in order to prevent latch-ups. Consequently, both of process and design engin

for latch-up prevention. Doping levels, and the other design aspects should be arr
to have low parasitic resistances and current gain of bipolar transistors. There are
prevent latch-ups in different technologies [1].

4. Conclusion

As its results may be fatal for the circuit, preventing latch-up in CMOS inte
essential for a proper operation.

5. References
[1] Razavi, B., 2000, Design of Analog CMOS Integrated Circuits, p. 628

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Site Haritas Eriilebilirlik Bize Yazn

Sitede Arama
Ara
Ayrntl Arama
Blmler
Ana Sayfa
ITU VLSI LABS
Ana Sayfa
Direktrn Kesi
Genel Bilgiler
Duyurular ve Etkinlikler
Kiiler ve Kariyer
Projeler
Dersler ve altaylar
Dokumanlar ve Aralar
Electronic Library
letiim
Mail Formu
Balantlar
Report A Problem
WEBS
Gir
Kullanc smi

Parola

Parolanz unuttunuz mu?

Yeni kullanc msnz?

Buradasnz: Ana Sayfa WEBS Courses Undergraduate ELE413 VLSI 1

Student Groups 20092010 Students Burak Budanur Latchup Latch-up in
CMOS Integrated Circuits
Latch-up in CMOS Integrated Circuits

Latch-up in CMOS Integrated Circuits

Outline:

1.

Introduction

2.

Explanation of the phenomena

3.

Preventing latch-up

4.

Conclusion

5.

References

1. Introduction

In CMOS fabrication, latch-up is a malfunction which can occur as a result of

improper design. Latch-up in a CMOS integrated circuit, causes unintended currents
will possibly resulting with the destruction of the entire circuit, thus, it must be
prevented.

2. Explanation of the phenomena

Figure 1 shows the cross section of a two-transistor CMOS integrated circuit

where the nMOS is on the left hand side and the pMOS on the right hand side. As it
can be seen from the figure, we can talk about a parasitic pnp transistor from
source of the pMOS to the p-substrate. Furthermore a parasitic npn transistor is
formed from source of the nMOS, p-substrate and the n-well. These parasitic
transistors and finite resistances of n-well and p-substrate can be shown like Figure
2 [1]. Equivalent circuit of these parasitic bipolar transistors is given in Figure 3 [1].

Figure 1 Cross section of a CMOS IC

figure 1

Figure 2 Parasitic bipolar transistors in a CMOS process

figure 2

Figure 3 Equivalent circuits formed by the parasitic transistors

Figure 3

As it can be clearly seen from the equivalent circuit, there is a positive

feedback loop around Q1 and Q2. If a parasitic current flows through the node X and
raise Vx, Q2 turns on and IC2 increases resulting VY decrease. This increases IC1
and consequently Vx increases much more. If the loop gain is equal to or greater
than unity, this situation continues until an enormous current flow through the
circuit in other words, until the circuit is latched up. [1]

3. Preventing Latch-up

As explained above, the loop gain of the equivalent circuit shown in Figure 3
should be lesser then unity in order to prevent latch-ups. Consequently, both of
process and design engineers should take steps for latch-up prevention. Doping
levels, and the other design aspects should be arranged properly in order to have
low parasitic resistances and current gain of bipolar transistors. There are specific
design rules to prevent latch-ups in different technologies [1].

4. Conclusion

As its results may be fatal for the circuit, preventing latch-up in CMOS
integrated circuit design is essential for a proper operation.

5. References

[1] Razavi, B., 2000, Design of Analog CMOS Integrated Circuits, p. 628

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