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CPU
Execution
Time
Instruction
Clock Cycle
CPI X
X
Count
Time
Input
Control
Memory
Datapath
Simplification:
ONLY implement a subset of MIPS ISA
Output
Datapath Design
Generic Implementation:
use the program counter (PC) to supply instruction address
get the instruction from memory
read registers
use the instruction to decide exactly what to do
High-Level Overview
D a ta
Reg ist er #
PC
A d d re s s
In stru ction
me m ory
In s tr u c ti o n
R e giste rs
AL U
A d dr e s s
Reg ist er #
D a ta
m e mory
Reg ist er #
D ata
Combinational Logic
f(a,b)
Sequential Logic
Contains state (flop, latch, etc)
clocked or unclocked
falling edge
cycle time
rising edge
Clocking Methodology
D
Q
Flip-flop
C
tprop
D
Q
Flip-flop
C
Combinational
logic block
tcombinational
tsetup
Register
Write Enable
Data In
N
N
Write Enable:
Clk
Data
Out
Register selection:
RA selects the register to put on busA
RB selects the register to put on busB
RW selects the register to be written via busW when Write
Enable is 1
RW RA RB
Write Enable 5 5
5
busW
32
Clk
32 32-bit
Registers
busA
32
busB
32
Memory
Write Enable
Data In
32
Clk
Address
DataOut
32
If Write Enable
is 0, the memory location is put on Data Out bus
is 1, the memory location is overwritten by Data In
CPI of 1
Overview
Instruction Fetch
Register File and register-register ops
Memory ops
Control ops
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
11
rd
5 bits
6
shamt
5 bits
0
funct
6 bits
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
26
op
6 bits
21
rs
5 bits
Example: sw
16
rt
5 bits
immediate
16 bits
beq
26
op
6 bits
16
rt
5 bits
0
immediate
16 bits
Questions??
Break!!
R-Type Datapath
Load Datapath
Store Datapath
Branch Datapath
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
Jump?
Instruction [25-0]
<<2
PC+4 [31-28]
6 bits
j format
OP
26 bits
target
5 function ALU:
ALU Control
Function
000
AND
001
OR
010
add
110
subtract
111
load (lw) - 00
branch (beq) - 01
ALU Control
6-bit opcode
6-bit function
main
control
2-bit ALUOp
ALU
control
3-bit ALUCtrl
To ALU
opcode
ALUOp
instruction
function
ALU Action
ALUCtrl
lw
00
load word
XXXXXX
add
010
sw
00
store word
XXXXXX
add
010
beq
01
branch equal
XXXXXX
subtract
110
R-type
10
add
100000
add
010
R-type
10
subtract
100010
subtract
110
R-type
10
AND
100100
AND
000
R-type
10
OR
100101
OR
001
R-type
10
SLT
101010
SLT
111
C D
0C
D
C6
6
DC
A 4
A CA
1 B
2C
10C
2C
DC
6
6 C DD
DC
DC
4
DC
A
AC
A 4
A 4
6
D C
6
D C
A
I 5
2C
C D C
DC
A 4
6
66
D CD
3 CA
1
6
66
C D
2C
66
2C
66
DC
A 4
0
1
A CA
DC
A 4
6
66
C DD
66
AC
R-format
0
M
u
x
ALU
Add result
Add
Shift
left 2
RegDst
B ranch
1
PCSrc
M emRead
Instruction [31 26]
Control
M emtoReg
A LUOp
M emWrite
A LUSrc
RegWrite
PC
Read
address
Read
register 1
Instruction
memory
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Zero
A LU ALU
result
0
M
u
x
1
Write
data
Data
memory
Write
data
16
Instruction [15 0]
Sign
extend
Read
data
Address
1
M
u
x
0
32
ALU
contr ol
Instruction [5 0]
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp
10
Loads
0
M
u
x
ALU
Add result
Add
Shift
left 2
RegDst
B ranch
1
PCSrc
M emRead
Instruction [31 26]
Control
M emtoReg
A LUOp
M emWrite
A LUSrc
RegWrite
PC
Read
address
Read
register 1
Instruction
memory
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Zero
A LU ALU
result
0
M
u
x
1
Write
data
Data
memory
Write
data
16
Instruction [15 0]
Sign
extend
Read
data
Address
1
M
u
x
0
32
ALU
contr ol
Instruction [5 0]
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp
00
Store
0
M
u
x
ALU
Add result
Add
Shift
left 2
RegDst
B ranch
1
PCSrc
M emRead
Instruction [31 26]
Control
M emtoReg
A LUOp
M emWrite
A LUSrc
RegWrite
PC
Read
address
Read
register 1
Instruction
memory
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Zero
A LU ALU
result
0
M
u
x
1
Write
data
Data
memory
Write
data
16
Instruction [15 0]
Sign
extend
Read
data
Address
1
M
u
x
0
32
ALU
contr ol
Instruction [5 0]
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp
00
BEQ
0
M
u
x
ALU
Add result
Add
Shift
left 2
RegDst
B ranch
1
PCSrc
M emRead
Instruction [31 26]
Control
M emtoReg
A LUOp
M emWrite
A LUSrc
RegWrite
PC
Read
address
Read
register 1
Instruction
memory
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Zero
A LU ALU
result
0
M
u
x
1
Write
data
Data
memory
Write
data
16
Instruction [15 0]
Sign
extend
Read
data
Address
1
M
u
x
0
32
ALU
contr ol
Instruction [5 0]
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp
01
Controller
Inputs
Op5
Op4
Op3
Op2
Op1
Op0
Outputs
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
R-format
lw
sw
beq
Opcode
000000
100011
101011
000100
O RegDst
u ALUSrc
t
p MemtoReg
u RegWrite
t MemRead
s
MemWrite
Branch
ALUOp1
ALUOp2
Up Next
Multicycle Implementation
Why isn t single cycle enough?
control is relatively simple
CPI is 1, but cycle time must be long enough for
every instruction to complete!
branch instruction versus load instruction
loads require instruction fetch, register access, ALU,
memory access, register access
branches require instruction fetch, register access, ALU
Key Points