Beruflich Dokumente
Kultur Dokumente
Aims
Familiarize students with combinational and sequential digital logic circuits, the analogue-digital
interface, and the hardware and basic operation
of microprocessors, memory and the associated
electronic circuits which are required to build microprocessor based systems.
Information Processing
Handout 1
Combinational Logic
Richard Prager
Tim Flack
January 2009
1
Contents of Handout 1
Section A
Section B
Section C
Section D
Logic Variables
Logic variables
Handout 1 Section A
Binary variables
Boolean variables
Washing Machine
Heating Boiler
If drum not turning and no water in drum and program finished then permit door to be
opened.
T
W
P
L
B = chimney blocked
=
=
=
=
drum turning
water in drum
program active
door unlocked
C = house is cold
P = pilot alight
V
Logic Gates
Electronic circuits that have logic signals as their inputs and outputs are known as LOGIC CIRCUITS or
DIGITAL CIRCUITS.
NOT Gate
Graphical
Symbol
Input-output
Map
0
1
1
0
Boolean
representation
Y =A
Input-output maps.
Boolean algebra.
9
10
OR Gate
AND Gate
Graphical
Symbol
Input-output
Map
A
B
Graphical
Symbol
Boolean
representation
Input-output
Map
B 0
0 0
1
0
1 0
Y = A.B
11
A
B
0
0 0
1
1
1 1
Boolean
representation
Y =A+B
12
EXCLUSIVE OR Gate
Graphical
Symbol
Input-output
Map
A
B
B 0
0 0
1
1
1 1
NAND Gate
Boolean
representation
Graphical
Symbol
Input-output
Map
Y =AB
A
B
0
0 1
1
1
1 1
Boolean
representation
Y = A.B
13
14
Boiler Example
NOR Gate
Graphical
Symbol
Input-output
Map
A
B
B 0
0 1
1
0
1 0
Boolean
representation
C = house is cold
P = pilot alight
V
V = B.C.P
Y =A+B
B
C
P
15
16
T = drum turning
W = water in drum
P = program active
L = door unlocked
L = T .W .P
T
W
L
A discussion of the power consumption of NMOS gates
leads to the introduction of the CMOS inverter circuit.
P
17
18
10v
1
x
2
0v
in
Inverter
circuit
Vout
Current
through
1 ohm
Current
through
2 ohm
V+
ic
rist istor
e
t
c res
ara
Ch ohm
of 2
0v
V+
V
in
19
tic
ris
te
ac
ar hm
Ch 1 o
of
10v
1
x
Thing
x
1
0v
Current
through
Thing
Current
through
1 ohm
C
of hara
1 ct
oh er
m ist
tic
ris
te
ac
ar hm
Ch 1 o
of
0v Voltage across
Thing
Thing
0v
Current
through
1 ohm
Characteristic
of Thing
The characteristic of
I
the upper component is
drawn backwards along
the V axis, starting at
the supply voltage.
10v
Current
through
Thing
Thing
characteristic
ic
Thing
Suppose we now recharacteristic
place the lower resistor
I
with a non-linear component (that we will call
a Thing).
0v
21
Voltage across
1 ohm
Characteristic
of Thing
x
Voltage across
Thing
10v
22
N-channel MOSFET
OFF
Drain +VD
Gate
111
000
n+
000
111
0v
Source 0v
111
000
n+
000
111
Reverse biased
p-n junction
p-type
substrate
ON
Drain +VD
Gate
+VG
Source 0v
111
000
000
111
n+
00
11
000
111
00
11
00
11
00
11
000
111
00
11
000
111
n+
000
111
N-type layer:
inversion
p-type
substrate
23
24
NMOS Inverter
NMOSFET Characteristics
IDS 12
mA 10
8
6
4
2
0
VGS = 10v
VGS = 8v
VGS = 6v
10
8
VDS Volts
VDD = 10v
1k
VGS = 4v
VGS = 2v
VGS = 0v
Vout
Vin
VGS
IDS as a function of
VGS at constant VDS
VDS
0v
IDS
mA
IDS 12
mA 10
8
6
4
2
0
3
VT
VGS
6
Volts
VGS = 10v
VGS = 8v
VGS = 6v
8
10
VDS Volts
NMOS FET
Characteristic
25
VGS = 4v
VGS = 2v
VGS = 0v
I 12
mA 10
8
6
4
2
0
6
V
8
10
Volts
Resistor
Characteristic
26
IDS 12
mA 10
8
6
4
2
0
VGS = 10v
Voltage Levels
VGS = 8v
VGS = 6v
8
10
VDS Volts
VGS = 4v
VGS = 2v
VGS = 0v
10
Vout
8
6
4
2
0
However if we say:
10
Vin
Vout
8
voltage > 9v
voltage < 2v
6
4
is logic 1
is logic 0
2
0
Vin
Vin > 9v
Vin < 2v
10
27
Vout < 2v
Vout > 9v
28
10
VDD
VDD
R
R
VY
VA
VY
VB
VA
0v
B
low
Y
high
high
low
low
high
low
low
high
high
VB
0v
A
low
high
low
B
Y
low high
low high
high high
high
high
low
low
30
VDD = 10v
IR
R = 1k
Vout
ID
IC
Vin
0v
32
IR = IC
VDD Vout
dVout
= C
R
dt
So
IDS 12
mA 10
8
6
4
2
0
Vout
V
dVout
+
= DD
dt
RC
RC
t
Vout = VDD + (1 VDD ) exp
RC
VGS = 10v
VGS = 8v
VGS = 6v
8
10
VDS Volts
VGS = 4v
VGS = 2v
VGS = 0v
Power Consumption
Smaller NMOS Inverter
10
VDD = 10v
VDD = 10v
6
Vout
4
2
0v
Vin
10
Vout
switch
Vin
1k
Vin
pseudo-resistor (load)
Vout
0v
35
36
Complementary MOS
CMOS Inverter
The problem with NMOS logic is power dissipation in
the resistors. To solve this, CMOS logic was invented.
This uses both NMOSFETS and PMOSFETS.
VSS = 10v
VGS = -10v
S
G
PMOS
D
D
Vin
VGS = -8v
NMOS
G
VGS = -6v
-2
-4
-6
-8 -10
VDS Volts
VGS = -4v
VGS = -2v
VGS = 0v
0v
Vin
low
high
G
S
Vout
NMOS PMOS
off
on
on
off
Vout
high
low
D
37
38
PMOS
NMOS Characteristic
IDS 12
mA 10
8
6
4
2
0
VGS = 10v
VGS = 8v
VGS = 6v
10
8
VDS Volts
VGS = 4v
VGS = 2v
VGS = 0v
PMOS Characteristic
IDS -12
mA -10
-8
-6
-4
-2
0
VGS = -10v
VGS = -8v
VGS = -6v
-2
-4
-6
-8 -10
VDS Volts
VGS = -4v
VGS = -2v
VGS = 0v
PMOS
VGS = -10v
12
I 10
mA 8
6
4
2
0
VGS = -6v
12
I 10
mA 8
6
4
2
0
Intersection of curves
NMOS
VGS = 4v
0
10
Intersection of curves
VGS = 0v
10
12
10
Intersection of curves
I
8
mA
6
4
2
0
0
2
4
6
8
NMOS
VGS = 6v
PMOS
VGS = -4v
10
(a)
Vin = 0v Vout = 10v. No current flows.
40
12
I 10
mA 8
6
4
2
PMOS
VGS = 0v
Intersection of curves
VGS = 10v
10
I /mA
Power /mW
0
2
4
5
6
8
10
0.0
1.0
2.7
3.6
2.7
1.0
0.0
0
10
27
36
27
10
0
Vin
Vin
41
10
Vin
42
10
Logic Families
VSS = 10v
NMOS Compact, slowish, cheap.
T2
T1
VB
VA
VY
T3
TTL Constructed from bipolar transistors. Propagation delay 1.510 nS, max clock frequency 35
200 MHz. Power consumption is about 102 W/gate.
T4
0v
VA
low
low
high
high
VB
low
high
low
high
T1
on
on
off
off
T2
on
off
on
off
T3
off
on
off
on
T4
off
off
on
on
VY
high
high
high
low
44
Handout 1 Section C
Combinational Logic Design
Boolean Algebra for Logic Design
In this section we introduce the laws of Boolean algebra and show how it can be used to design combinational logic circuits. We then introduce the hardware description language VHDL. This language can
be used to enable computer-aided design of logic circuits.
T
W
P
L
46
We need:
In an extreme example, it would be very useful to be
able to work out that
A
1. Techniques for simplifying logic expressions. Simpler expressions mean fewer gates which lead to
lower cost.
Y
C
D
can be replaced by
We are going to study two ways of solving these problems: Boolean algebra and Karnaugh maps.
B
C
Y
Boolean algebra rigorous, computable.
This sort of problem can be solved using Boolean algebra and Karnaugh maps.
47
Boolean Algebra
ORs
A+0=A
A+A=A
A+1=1
A+A=1
Commutation
A+B =B+A
A.B = B.A
normal
normal
Association
(A + B) + C = A + (B + C)
(A.B).C = A.(B.C)
normal
normal
ANDs
A.0 = 0
A.A = A
A.1 = A
A.A = 0
Distribution
A.(B + C + . . .) = (A.B) + (A.C) + . . .
A + (B.C. . . .) = (A + B).(A + C). . . .
normal
NEW
Absorption
A + (A.C) = A
A.(A + C) = A
NEW
NEW
49
.
+
0
1
replaced by
replaced by
replaced by
replaced by
+
.
1
0
50
A + (A.B) = (A + A).(A + B)
A + A.B
= 1.(A + B)
= A+B
52
De Morgans Theorem
Simplify X.Y + Y .Z + X.Z + X.Y.Z
A + B + C + . . . = A.B.C. . . .
A.B.C. . . . = A + B + C + . . .
A + B + C + . . . = A.B.C. . . .
A.B.C. . . . = A + B + C + . . .
= X.Y + Y.Z
53
54
B
0
1
0
1
A+B
1
0
0
0
A.B
1
1
1
0
A
1
1
0
0
B
1
0
1
0
A.B
1
0
0
0
A+B
1
1
1
0
In our washing machine example we needed to implement the logic function L = T .W .P . This can be
simplified with a single application of De Morgans theorem:
L = T .W .P
= T +W +P
55
56
(B.B = B)
(De Morgan)
(repeated A.B)
= A.B + A.B.C
(B.B = 0)
= A.B + A.C + B
(B + B.C = B)
= A.B
(absorption))
= A.C + B
(A.B + B = B)
57
58
Simplify:
A
B
Y
= (A.B.(C + B + D) + A + B).C.D
(De Morgan)
= (A.B.C + A.B.B + A.B.D + A + B).C.D
(distribute)
= (A.B.C + A.B.D + A + B).C.D
(cancel A.B.B)
= A.B.C.D + A.B.D.C.D + A.C.D + B.C.D
(distribute)
= A.B.C.D + A.C.D + B.C.D
(cancel A.B.D.C.D)
= (A.B + A + B).C.D
(distribute)
= (A.B + A.B).C.D
(De Morgan)
= C.D
(A.B + A.B = 1)
59
= A.B.B.C.B.C.C.D
= (A.B + B.C).(B.C + C.D)
(De Morgan)
= A.B.B.C + A.B.C.D + B.C.B.C + B.C.C.D
(distribute)
= A.B.C + A.B.C.D + B.C + B.C.D
(remove repeated variables)
= B.C
(absorption)
60
A power plant is cooled by 3 ventilation fans, numbered 1 to 3, with flow rates F , 2F and 3F respectively. An alarm is to be sounded if the plant is running
and the air flow rate is less than 3.5F . Design a logic
circuit to do this.
A1
A2
A3
Y
= (A3 + A1.A2).B
= A3.B + A1.A2.B
= (A3.B).(A1.A2.B)
A2
B
Y
A3
61
62
= A1.A3 + A2.A3 + B
= A1.A3 + A2.A3 + B
= (A1 + A3) + (A2 + A3) + B
A1
A3
A2
B
63
64
VHDL
Structure of VHDL
Computer-aided design tools are required for the development of complex digital systems. These tools
enable the simulation, modelling and testing of designs before they are built.
A hardware description language is required to describe the systems. It must be clear and readable for
the designer, yet sufficiently precise to enable rigorous testing of the design.
66
entity INV is
port(A : in BIT;
Y : out BIT);
end INV;
entity NOR2 is
port(A, B : in BIT;
Y
: out BIT);
end NOR2;
entity NAND2 is
port(A, B : in BIT;
Y
: out BIT);
end NAND2;
entity NOR3 is
port(A, B, C :
Y
:
end NOR3;
in BIT;
out BIT);
68
in BIT;
out BIT);
Handout 1 Section D
in BIT;
out BIT);
72
Karnaugh Map
Karnaugh maps are a powerful visual tool for carrying out simplification and manipulation of logic expressions with up to 5 input variables.
AB
00 01
CD
00 1
01 1
11
10
A1 A 2
00
A3 B
A1
11 10
1
01
11
10
AB
00 01
CD
00 1
11 10
00
01
11
B
1
A3
01
11
C
1
10 1
10
A2
73
74
AB
00 01
CD
00
1
1
11 10
1
01
11
10
D
C
AB
CD
00 01
11 10
00 1
11
C
1
1
D
01
11 10
1
11
C
1
01
AB
00 01
CD
00 1
10 1
10 1
B
75
76
1
0
AB
CD
00
00
A.B
1
Two variable expression
eg. A.B
1
or
01
C.D
11
1.B
0
A
01 11 10
1
1
C
1
One variable expression
eg. A
C.D
10
A.B + C.D
78
A1
1
B
= (A3.B).(A1.A2.B)
A3
A2
A1
A1
A3
A3
A2
A1
B
A3
A2
A2
= A1.A3 + A2.A3 + B
= (A1 + A3) + (A2 + A3) + B
A1
A2
B
Sometimes you can produce a simpler circuit by mapping the opposite way (i.e. 0s for NAND and 1s for
NOR) and then use a final inverter gate to change the
output back again.
A3
A1
A3
A2
A
1
1
= A.B + C.D
C
1
= (A + B) + (C + D)
B
81
82
D
C
AB
CD
00
AB
00 01 11 10
C
0
01
11
10
00
01
11
10
00
01
11
10
E=0
83
E=1
84
A1
1
B
= A3.B + A2.B
1
A3
= (A3.B).(A2.B)
A2
A1
A3
1
B
= A2.A3 + B
= (A2 + A3) + B
A2
= (A2 + A3) + B
86
Hazards
A static hazard is when a signal undergoes a momentary transition when it is supposed to remain unchanged.
A2
B
Y
A dynamic hazard is when a signal changes more
than once when it is supposed to change just once.
A3
A3
A2
Logic 1
Logic 0
Static 1-hazard
Logic 1
Logic 0
Static 0-hazard
Logic 1
Logic 0
Dynamic hazard
Logic 1
Logic 0
Dynamic hazard
Time
87
88
Static 1-Hazard
Removing Hazards
X
Y
U
T
This circuit
W implements
W=X.Y+Z.Y
Consider what
happens when
Z=1 and X=1
and Y changes
from 1 to 0.
W
Time
89
90
Hazard-Free Circuit
X
1
1
X
Y
W
X
Z
1
1
Y
91
92
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
B
Note the potential for ambiguity during the transition
from 0111 to 1000.
93
A
0
0
0
0
0
0
0
0
B
0
0
0
0
1
1
1
1
C
0
0
1
1
1
1
0
0
D
0
1
1
0
0
1
1
0
A
1
1
1
1
1
1
1
1
B
1
1
1
1
0
0
0
0
C
0
0
1
1
1
1
0
0
D
0
1
1
0
0
1
1
0
95
96