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Overview
With NI Multisim and NI LabVIEW software, you can implement desktop simulation of your entire analog and digital system before prototyping. This tutorial shows you how to use the Multisim and
LabVIEW cosimulation feature to achieve closed-loop simulation of transistor-level power electronics as well as implement FPGA-based digital logic used for control.
It also examines the system simulation of a 3-phase inverter. Because the high-power analog circuit is developed in Multisim, it benefits from the new SPICE-based power electronics models
featured in Multisim 12.0 such as the MOSFET switches and the nonideal RLCs. The digital logic blocks controlling the Multisim design are developed in LabVIEW.
A simultaneous point-by-point simulation that includes all of the system dynamics between the analog circuitry and the FPGA-based digital control system is performed. During this, processing
resources are negotiated between both simulation engines in a variable time-step fashion. Accurate and complete desktop system simulation is now possible at an early stage of the design
process.
Table of Contents
1. System Requirements
2. Introduction
3. Design Flow
4. Multisim Analog Circuitry
5. LabVIEW Control Blocks
6. Complete System Simulation
7. Hardware Implementation
1. System Requirements
Multisim 12.0
LabVIEW 2011
LabVIEW 2011 Control Design and Simulation Module
LabVIEW 2011 FPGA Module
2. Introduction
What Is a Multisim and LabVIEW Complete System Simulation?
In traditional control logic design, engineers develop embedded code separate from the analog circuitry, but they eventually need to interact at a system level that is difficult to simulate
simultaneously. This lack of simulation capabilities can result in embedded logic that does not properly account for analog circuitry (for example, the power design) and performs below
expectations/specifications. This forces algorithm change and recompiles.
Multisim and LabVIEW enable codesign of an entire system, ensuring that algorithms and code simulated for the field-programmable gate array (FPGA) in LabVIEW are verified for performance
with analog circuitry and can be directly implemented in hardware with minimal changes. This design approach is new in Multisim 12.0 and is called LabVIEW cosimulation.
Cosimulation allows a unique time-step negotiation between two simulation engines to create a closed-loop simulation of the complete system. The result is an evaluation of a design that includes
all of the system dynamics between the analog and digital modules. Multisim, which is optimized for accurate analog and mixed-signal circuitry, includes a large set of predefined SPICE models
from leading semiconductor manufacturers such as Analog Devices, NXP, ON Semiconductor, Texas Instruments, and others. The LabVIEW simulation engine is dedicated to the effective design
and implementation of control logic through a graphical, dataflow representation. This engine provides high-level simulation optimized for embedded digital code for mechanical and power
systems.
The result of this is a reduction in prototype iterations (up to three saved PCB turns) and accurate embedded code with fewer compiles (saving as much as four hours per compile).
3. Design Flow
The first step of this hardware design is the desktop simulation developed in Multisim and LabVIEW and highlighted in this tutorial. The different system blocks and the signal flow of the system are
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The first step of this hardware design is the desktop simulation developed in Multisim and LabVIEW and highlighted in this tutorial. The different system blocks and the signal flow of the system are
demonstrated in Figure 2.
The inputs to this Multisim design are the switch gate terminals (s1 to s6), and all of the other terminals connect to output signals either for monitoring or as part of the feedback loop.
The following table is exported from the Multisim LabVIEW terminals spreadsheet view and summarizes the connector modes.
LabVIEW terminal
Positive connection
Negative connection
Mode
Type
s1
s1
Input
Voltage
s2
s2
Input
Voltage
s3
s3
Input
Voltage
s4
s4
Input
Voltage
s5
s5
Input
Voltage
s6
s6
Input
Voltage
Input
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Output
Va
Va
Output
Voltage
Vb
Vb
Output
Voltage
Vc
Vc
Output
Voltage
Va_l
Va_l
Output
Voltage
Vb_l
Vb_l
Output
Voltage
Vc_l
Vc_l
Output
Voltage
I_Lf1
I_Lf1
Output
Voltage
I_Rload1
I_Rload1
Output
Voltage
Vdc_link
Vdc_link
Output
Voltage
Vneutral
Vneutral
Output
Voltage
Unused
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The simulation results show that after 0.02 s of running the system, the output voltage of the 3-phase inverter is not aligned to the grid voltages since the feedback system is still at its initial stage.
The simulation shows that it takes about 0.1 s for the inverter output to align to the grid line voltages.
This unparalleled approach of system simulation that includes all of the dynamics between the analog circuitry and the FPGA control logic enables early evaluation of the system performance as
well as saves simulation time and prototyping cost.
7. Hardware Implementation
The next design stage is to prototype the analog circuitry into hardware and to compile the FPGA IP and load it to target hardware to create an FPGA-based real-time HIL simulation as well as an
RCP simulation.
View a complete reference design of this system simulation and rapid prototyping and see a demonstration of a real-time simulation of a 3-phase single-level inverter with RLC filter and load. The
real-time HIL simulation is executed in FPGA hardware using LabVIEW at a 1 MHz loop rate. A basic sine-PWM control system is also executed at 500 kHz in the FPGA with an NI 9401 C Series
digital I/O module used for communication between the HIL and RCP loops.
You can achieve rapid and easy PCB prototyping using NI Ultiboard.
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