Beruflich Dokumente
Kultur Dokumente
PPT(10/1/2009)
5.1
Lecture 13
Adder Circuits
Objectives
Understand how to add both signed and unsigned
numbers
Appreciate how the delay of an adder circuit depends
on the data values that are being added together
Adder.PPT(10/1/2009)
5.2
Full Adder
S
Q
CI
+ CI
C
Output is a 2
2-bit
bit number counting how many inputs are
high
P
0
0
0
0
1
1
1
1
Q
0
0
1
1
0
0
1
1
CI
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
C P Q P CI Q CI
S P Q CI
Note:
N t P Q CI = (P Q) CI = P (Q CI)
Adder.PPT(10/1/2009)
5.3
Propagation delays:
From
To
Delay
P Q or CI
P,Q
P,Q or CI
Adder.PPT(10/1/2009)
5.4
N-bit adder
We can make an adder of arbitrary size by cascading full
adder sections:
P0
Q0
C1
P1
P
S
S0
Q1
Q
CI
C0
P2
P
S
S1
Q2
Q
CI
P3
P
S
S2
Q3
P
S
Q
C2
C1
CI
S3
CI
C3
P0
P1
P2
P3
Q0
Q1
Q2
Q3
C1
0
P
0
3
0
S0
S1
S2
S3
Q
3
CI
C3
C3
Adder.PPT(10/1/2009)
5.5
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
?
Q0
Q1
Q2
Q3
4
0
4
Q
?
0
C1
4
CI
C4
C4
Adder.PPT(10/1/2009)
5.6
0101
00000101
13
1101
00001101
Signed numbers
Expand a signed number by duplicating the MSB the
appropriate number of times:
5
0101
00000101
1101
11111101
Adder.PPT(10/1/2009)
5.7
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
0
Q0
Q1
Q2
Q3
4
0
4
Q
0
0
C1
4
CI
C4
C4
P0
P1
P2
P3
0
P
3
Q0
Q1
Q2
Q3
S0
S1
S2
S3
S4
3
Q
3
0
C1
CI
C3
C3
Adder.PPT(10/1/2009)
5.8
P0
P1
P2
P3
0
P
S0
S1
S2
S3
S4
0
4
Q0
Q1
Q2
Q3
4
Q
4
0
C1
CI
C4
C4
P=0000, Q=1111
Unsigned P+Q=01111
P+Q 01111, Signed P+Q=11111
P+Q 11111
Adder.PPT(10/1/2009)
5.9
P0
Q0
C1
P1
P
S
S0
Q1
Q
CI
P0
C0
C0
P2
P
S
S1
Q2
Q
CI
C0
C1
P3
S
S2
Q3
S3
S
Q
C2
C1
CI
C1
CI
C2
C2
S4
S3
3
P, Q, CI C = 2
Adder.PPT(10/1/2009)
5.10
Answer 1 (B=0):
Initially: A=0, B=0 X=1, Y=0, Z=0, Q=0
Then: A Y Q
2 gate delays
Answer 2 (B=1):
Initially: A=0, B=1 X=1, Y=0, Z=1, Q=1
Then: A X Z Q
3 gate delays
Adder.PPT(10/1/2009)
5.11
Worst-Case Delays
We are normally interested only in the worst-case delay
from a change in any input to any of the outputs.
The worst-case delay determines the maximum clock
speed in a synchronous circuit:
CLOCK
C1
W
C1
X
1D
Logic
1D
CLOCK
W
X
Y
Z
time
tp
tp+tg
tp + tg + ts < T
Since the clock speed must be chosen to ensure that the
circuit always works, it is only the worst-case logic delay
that matters.
Adder.PPT(10/1/2009)
5.12
Quiz
1
1.
In an full adder
adder, why is it normally more important to
reduce the delay from CI to C than to reduce the
delay from P to S ?
2.
3.
How do you convert a 4-bit signed number into an 8bit signed number ?
4.
5.
Adder.PPT(10/1/2009)
5.13
Lecture 14
Adder.PPT(10/1/2009)
5.14
P1
P
S
S0
Q1
Q
CI
P0
C0
C0
2
P2
P
S
S1
Q2
Q
CI
C0
P3
S
S2
Q3
P
S
CI
C1
CI
C2
S3
C2
C1
C1
2
C2
S4
S3
3
Adder.PPT(10/1/2009)
5.15
P0
Q0
C1
P1
Q1
P1
P
S
C
P2
S0
Q1
Q
CI
S1
C0
C0
S1
Q2
Q
CI
C1
C1
P
S
S2
Q
C2
CI
C1
P1
Q1
Adder Stage 0
C0
C0
P2
C1a
C1b
Q2
C1
C1c
Adder Stage 1
C1
Adder Stage 2
C2
Adder.PPT(10/1/2009)
5.16
C1a
C1b
C1c
C0a
C0a
C0b
C0c
C0
C0
C0b
C1a
C1b
C1c
C0c
P1
Q1
P0
Q0
Q2
C2a
C0a
C0c
C0b
C1a
C1b
C2b
C2c
C1c
C1
P2
C1
Adder Stage 0
Adder Stage 1
Adder Stage 2
Adder.PPT(10/1/2009)
5.17
Even stages:
Q
CIa,b,c
COa,b,c
Delays:
P,Q,CI S
P,Q,CI C
3
1
Odd stages:
Delays:
P,Q S
P,Q C
CI S
CI C
5
2
4
1
COa,b,c
CIa,b,c
Adder.PPT(10/1/2009)
5.18
P0
P1
P
S
Q0
S0
Q1
C1
CI
C0
C0
S1
Q2
Q
CI
P1
P0
P2
C0
C
2
1
C1
P3
P
S
S2
Q3
Q
CI
C2
C1
C1
P
S
Q
C3
CI
C2
C1
C2
C
4
C2
S3
S4
S3
2
S4
Adder.PPT(10/1/2009)
5.19
Carry Inhibit
Carry Propagate
Carry Generate
Adder.PPT(10/1/2009)
5.20
1???
+ 1???
11??
+ 01??
101?
+ 011?
1011
+ 0101
1011
+ 0100 +1
Thus
C3 = CG3 + CP3CG2 + CP3CP2CG1 +
CP3CP2CP1CG0+CP3CP2CP1CP0C1
As before,, we can use CGPn in place
p
of CPn.
Adder.PPT(10/1/2009)
5.21
S0
Q CGP CGP0
C1
CI CG CG0
P1
Q1
S1
Q CGP CGP1
C0
CI CG CG1
P2
S2
Q2
Q CGP CGP2
C1
CI CG CG2
S3
Q3
Q CGP CGP3
C2
CI CG CG3
Logic
Logic
To later
stages
Logic
P3
C0 = CG0 + CGP0C11
C1 = CG1 + CGP1CG0 + CGP1CGP0C1
C2 = CG2 + CGP2CG1 + CGP2CGP1CG0 +
CGP2CGP1CGP0C1
Adder.PPT(10/1/2009)
5.22
CG0
To 8
logic
blocks
Adder.PPT(10/1/2009)
5.23
Quiz
1 What does it mean to say that a full
1.
full-adder
adder is self-dual
self dual
?
2. How does placing an inverter between each stage of a
multi-bit adder allow the merging of gates in
consecutive stages ?
3. In a 4-bit adder, give an example of a propagation
delay that increases when alternate bits are inverted.
4. Why is a carry-lookahead adder generally
implemented using CGP rather than CP outputs ?
Adder.PPT(10/1/2009)
5.24
Lecture 15
Adder.PPT(10/1/2009)
5.25
P2,Q2
P1,Q1
C1
P4,Q4
P3,Q3
S0
S1
P6,Q6
P5,Q5
S2
S3
P8,Q8
P7,Q7
S4
S5
P10,Q10
P9,Q9
S6
S7
P11,Q11
S8
S9
S10
C11
S11
The worst-case
worst case delay path is from C
C1
1 to S11
S11.
In carry skip, we speed up this path by allowing the carry
signal to skip over several adder stages at a time:
P0,Q0
P2,Q2
P1,Q1
C1
S0
P4,Q4
P3,Q3
S1
S2
P6,Q6
P5,Q5
S3
S4
P8,Q8
P7,Q7
S5
S6
P10,Q10
P9,Q9
S7
P11,Q11
S8
S9
S10
C11
S11
Adder.PPT(10/1/2009)
5.26
P0
P1
P
S
Q0
S0
Q1
C1
CI
P0
C1
C
1
1
C0
P2
P
S
S1
Q2
Q
CI
C0
P1
C0
C0
C
2
1
C1
S
C
Q3
C3
CI
C2
C1
C2
S3
C2
C1
C1
S2
Q
CI
P3
C2
C
4
1
S3
C3
0101
1010
1
10000
C1 C3 = 4 gate delays
0101
1110
1
10100
C11 C3 = 0 gate delays
Adder.PPT(10/1/2009)
5.27
CP0
CP
P0
Q0
S0
Q1
C1
CI
C0
CP
P2
P
S
S1
Q2
Q
C1
CI
CP2
CP
P1
CP1
P
S
C
MUX
P
Q3
C2
CP3
CP
P3
S2
Q
CI
CSK
S3
G1
Q
CI
C3
C
C3X
1
1
P0
P0
C1
2
1
1
CP0
C0
C0
2
P1
C0
2
1
C1
C1
C2
C1
C2
C2
4
1
CSK
S3
C3
C3X
1
C3X
C3X
C1
C3X
Adder.PPT(10/1/2009)
5.28
G1
C3X
C3
C1
CSK
!C3X
0
1
!C3
!C1
CSK
C3
C3
C1
C
1
C1
C
1
C3X
C3
C3X
C1
C1
Adder.PPT(10/1/2009)
5.29
P3:0
P3:0
Q3:0
Q3:0
S3:0
S3:0
C1
CI C3X
P0
C1
5
1
C3
P7:4
P3:0
Q7:4
Q3:0
S7:4
S3:0
CI C3X
P11:8
Q11:8
C7
P15:12
P3:0
P3:0
Q15:12
Q3:0
Q3:0
S11:8
S3:0
S3:0
CI C3X
CI C3X
P12
C3
C3
C11
C3
C7
C7
C11
C11
7
7
S15:12
C15
S15
S15
2N+1
N+3
N+10
6
Adder.PPT(10/1/2009)
5.30
E
F
Y3:0
Z3:0
Adder.PPT(10/1/2009)
5.31
Addition Tree
In practice we use a tree arrangement of adders:
Number of values, K
16
log 2(K)
Adder.PPT(10/1/2009)
5.32
Carry-Save Adder
Take a normal 4-bit adder but dont connect up the
carrys:
P0
Q0
R0
P1
P
S
S0
Q1
Q
CI
C0
R1
P2
P
S
S1
Q2
Q
CI
C1
R2
P
S
C
Q3
C2
We have P+Q+R = 2C + S
S2
Q
CI
P3
P:
Q:
R:
S:
C:
R3
CI
1001
1100
1101
1000
1101_
CS
P
S
Q
R
S3
C3
Adder.PPT(10/1/2009)
5.33
P
S
B
C
CS
P
Q
R
CS
CS
D
S
C
S
2
Q
C
S
2
J
C
A:
B:
C:
G:
H:
1101
1010
0101
0010
1101_
D:
E:
F:
I
I:
J:
1011
1100
0001
0110
1001_
Notes:
1.
2.
3.
4.
G : _0010
2H: 1101_
I: _ 0 1 1 0
K: 11110
L: _0010_
M:
01000
2N: 1011__
X: 0110100
K: 11110
2L: 0010_
2J: 1001_
M : 01000
N: 1011__
Adder.PPT(10/1/2009)
5.34
Carry-Save Tree
We can construct a tree to add sixteen values together:
CS
CS
CS
CS
CS
CS
CS
CS
Number of
values, K
CS
CS
CS
CS
CS
CS
16
13
4
log2(K)
Delay
0
Delay/log2(K)
3.7
3
3.17
6
2.58
9
2
12
1.58
15
1
18
0
24
10
5.65
5.13
5.13
7.23
5.13
Adder.PPT(10/1/2009)
5.35
Merryy Christmas
The End
Adder.PPT(10/1/2009)
5.36
Quiz
1 In a 4
1.
4-bit
bit adder,
adder how can you tell from P0:3 and Q0:3
whether or not C3 is dependent on C1 ?
2. A multiplexer normally has 2 gate delays from its data
inputs to its output. How is this reduced to 1 gate delay
in the carry skip circuit ?
3. If five 4-bit numbers are added together, how many
bits are needed to represent the result ?