Combinational Circuits

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Combinational Logic
Circuits

Any combinational circuits can be realized

using complementary MOS (CMOS) transistor
Using static CMOS logic, given a Boolean
equation, the circuit realization using static
CMOS is done by drawing:
pull-down network using nMOS transistors
and
pull-up network using pMOS transistors

By: Assoc. Prof. Siti Hawa Ruslan

Siti Hawa Ruslan 2015

Combinational Circuits (comb.)

Combinational Circuits (cont.)

If the Boolean equation is in the form of Andor-Invert (AOI) or Or-and-Invert (OAI), then
For pull-down network or nMOS transistors
AND function
series
OR function
parallel
But for the pull-up network using pMOS
transistors
AND function
parallel
OR function
series

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Basic Gates nMOS network

NAND

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For the fully complementary

static CMOS logic circuit the
pull-up and pull-down network
are always opposite
They are a mixture of AND
and OR structures (or vice
versa) with a final inversion

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Basic Gates pMOS network

NOR

NAND

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NOR

Basic Gates Combination

Example 1
Y AB CD

NAND

nMOS

pMOS

Combining nMOS
and pMOS network

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Example 1 (cont.)
Y AB CD

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Example 2
F ab c

Final circuit using static CMOS

For term : b c

nMOS
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Example 2 (cont.)

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pMOS

Example 2 : Stick Diagram

F ab c

F ab c

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Example 3

Example 3 : Stick Diagram

X a b c d

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Example 4

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Example 4 (cont.)
Look at the nMOS network:

Find the Boolean

equation for the circuit.

Y (a e) (b f )
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Exercise 1

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Exercise 1 : Solution

Design a circuit using static CMOS technique

to realize the following Boolean equation :

Y A B C D

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Y A B C D

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Exercise 2:

Exercise 2: Solution

Draw the stick diagram for

Y A B C D

The stick diagram

Y A B C D

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Exercise 3

Exercise 3 (cont.)

Realize the following equation using static CMOS

logic and determine the size of the transistor to be
used such that it will be equivalent to the driving
capability on an inverter

Y D A( B C )

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For the inverter:

The pull down W/L
ratio is 2/2, and the
pull up W/L ratio is
4/2
Note: Minimum L = 2

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Transistor Sizing

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A

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Y D A( B C )

1
B

2C

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Example 5

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B
3

Combinational Gates

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Transistor Sizing

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Exercise 4

Example 6

Transistor Sizing

Determine the
equation for the
output of the shown
circuit and draw the
stick diagram
Y A BC DE

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Eliminating Gap

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Rearrange the position of the transistor to avoid gap

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Assignment 1 :
Draw the schematic
and layout for:

Use Tanner Tools EDA to draw the schematic and

layout, simulate it and get the simulation and output
result for both the schematic and layout. Write a short
report on this assignment.
E-mail the respective files created along with the
output file using the Tanner Tools to:
sitihawa@uthm.edu.my

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EX-OR

Y ABC D E

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Eliminating Gap (cont.)

Gap should be avoided whenever possible

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a b a b ab

Due date: Sunday 22 March 2015 (Before 5 pm)

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EX-OR (cont.)

EX-OR (cont.)
a b a b ab

a b a b ab
The equation is in the form of
AND-OR (AO), thus draw the
p-MOS network first:
AND series
OR parallel
But with input inverted
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For the nMOS network:

AND parallel
OR series
with input inverted

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EX-OR (cont.)

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EX-OR (OAI form)

a b a b ab

Same as
previous
circuit

ab ab
ab ab

Overall circuit realization

using static CMOS
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(a b)( a b)
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EX-OR (AOI form)

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EX-OR (cont.)

Draw the stick diagram for EX-OR

a b ( a b) ( a b)

ab a b
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EX-OR (cont.)

EX-OR (cont.)

Draw the stick diagram for EX-OR

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EX-OR : Layout

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EX-OR (AOI form)

Which one is
the best
layout ?

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Draw the stick diagram for EX-OR

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Transmission Gate

Exercise:
Draw the stick
diagram for the
shown EX-OR
circuit

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EX-OR using Transmission Gate

Symbol

Or :

a b

y as
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If s =1: y = a
If s =0: y a
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(both transistors ON)

(both transistors OFF)
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a b

Only 4 transistors are used

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EX-NOR

EX-OR using Transmission Gate

If b = 0
both upper transistors are ON
so y = a

a b

a b ab ab

If b = 1
both lower transistors are ON
so y = a
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EX-NOR (cont.)

a b ab ab

Same as
previous
circuit

(a b)(a b)

In AOI form

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EX-NOR (cont.)

a b ab ab

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EX-NOR (cont.)

In OA form

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EX-NOR (cont.)

Draw the stick diagram for EX-NOR

a b ab ab
(a b)( a b)
ab a b
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EX-NOR (cont.)

EX-NOR using Transmission Gate

Exercise: Draw the
stick diagram for EXNOR

a b ab ab
(a b)( a b)
ab a b

Only 4 transistors are used

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Combinational Circuit

EX-NOR using Transmission Gate

Or :

f2

x1
x2

a b

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x3
f1

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THANK YOU

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