MOSFET

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MOSFET

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(MOSFETs)

MICROELECTRONIC CIRCUITS

Sedra/Smith

Sixth Edition

Oxford University Press

2011

2015/2/23

Chih-Wen Lu

Current-Voltage Characteristics.

MOSFET Circuits at DC.

Applying the MOSFET in Amplifier Design.

Small-Signal Operation and Models.

Basic MOSFET Amplifier.

Biasing in MOS Amplifier Circuits.

Discrete-Circuit MOS Amplifiers.

The Body Effect and Other Topics.

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Chih-Wen Lu

Introduction

The voltage between two terminals of the FET controls the current

in the third terminal.

The FET can be used both as an amplifier and as a switch.

The current-control mechanism is based on an electric field

established by the voltage applied to the control terminal.

The current is conducted by only one type of carrier (electrons or

holes).

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Introduction (contd)

Enhancement-Type MOSFET

MOSFET

FETs

Depletion-Type MOSFET

JFET

FETs: Field-Effect Transistors

MOSFET: metal-oxide semiconductor field-effect transistor

JFET: Junction field-effect transistor

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The enhancement-type MOSFET is the most widely used fieldeffect transistor. In this section, we shall study its structure and

physical operation. This will lead to the current-voltage

characteristics of the device, studied in the next section.

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Physical structure of the enhancement-type NMOS transistor: (a)

perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W =

0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the

range of 2 to 50 nm.

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Four terminals: Gate (G), Source (S), Drain (D), and Substrate or

body (B)

Polysilicon is used to form the gate electrode in the modern

technology.

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The substrate forms pn junctions with the source and drain regions.

These pn junctions are kept reversed-biased at all times.

Thus, the substrate will be considered as having no effect on device

operation, and the MOSFET will be treated as a three-terminal

device, with the terminals being the gate, source, and drain.

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A voltage applied to the gate controls current flow between source

and drain.

This current will flow in the longitudinal direction from drain to

source in the region labeled channel region.

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Operation with No Gate Voltage.

With no bias voltage applied to the gate, two back-to-back diodes

exit in series between drain and source.

These back-to-back diodes prevent current conduction from drain

to source when a voltage vDS is applied.

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Creating a Channel for Current Flow.

The enhancement-type NMOS transistor with a positive voltage

applied to the gate. An n channel is induced at the top of the

substrate beneath the gate.

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13

Ground the source and drain and apply a positive voltage to the

gate.

The positive voltage on the gate causes the free holes to be repelled

from the region of the substrate under the gate (channel region).

As well, the positive gate voltage attracts electrons from the n+

source and drain regions into the channel region.

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When a sufficient number of electrons accumulate near the surface

of substrate under the gate, an n region is in effect created,

connecting the source and drain regions.

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Now if a voltage is applied between drain and source, current flows

through this induced n region, carried by the mobile electrons.

Correspondingly, this MOSFET is called an n-channel MOSFET

or, an NMOS transistor.

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An n-channel MOSFET is formed in a p-type substrate.

The channel is created by inverting the substrate surface from p

type to n type.

Hence the induced channel is also called an inversion layer.

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The value of vGS at which a sufficient number of mobile electrons

accumulate in the channel region to form a conducting channel is

called the threshold voltage and is denoted Vt. Vt for an n-channel

FET is positive.

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The gate and body of the MOSFET form a parallel-plate capacitor

with the oxide layer acting as the capacitor dielectric.

The positive gate voltage causes positive charge to accumulate on

the top plate of the capacitor (gate electrode).

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The corresponding negative charge on the bottom plate is formed

by the electrons in the induced channel.

An electric field thus develops in the vertical direction.

It is the field that controls the amount of charge in the channel, and

thus determines the channel conductivity and the current that will

flow through the channel when a voltage vDS is applied.

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Applying a Small vDS

An NMOS transistor with vGS > Vt and with a small vDS applied.

The device acts as a resistance whose value is determined by vGS.

Specifically, the channel conductance is proportional to vGS Vt

and thus iD is proportional to (vGS Vt) vDS.

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Apply a small positive voltage vDS.

A current in the channel, iD, will flow from drain to source.

The magnitude of iD depends on the density of electrons in the

channel, which in turn depends on the magnitude of vGS.

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For vGS = Vt the channel is just induced and current is still small.

As vGS exceeds Vt, more electrons are attracted into the channel.

The result is a channel of increased conductance.

In fact, the conductance of the channel is proportional to the excess

gate voltage (vGS Vt). iD is proportional to vGS Vt and to vDS.

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The iDvDS characteristics of the MOSFET when the voltage

applied between drain and source, vDS, is kept small. The device

operates as a linear resistor whose value is controlled by vGS.

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The MOSFET is operating as a linear resistance whose value is

controlled by vGS.

The resistance is infinite for vGS < Vt, and its value decreases as vGS

exceeds Vt.

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Increasing vGS above Vt enhances the channel, hence the names

enhancement-mode operation and enhancement-type MOSFET.

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Operation as vDS Is Increased

Operation of the enhancement NMOS transistor as vDS is

increased. The induced channel acquires a tapered shape, and its

resistance increases as vDS is increased. Here, vGS is kept constant

at a value > Vt.

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As vDS is increased.

The voltage between the gate and points along the channel

decreases from vGS at the source end to vGS vDS at the drain end.

The channel will take the tapered form.

As vDS is more increased, the channel more tapered and its

resistance increases.

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Thus iD vDS curve does not continue as a straight line but bends.

Eventually, when vDS is increased to the value that reduces the

voltage between gate and drain to Vt, that is, vGS vDS = Vt or vDS =

vGS Vt the channel depth at the drain end decreases to almost zero,

and the channel is said to be pinched off.

versus the drain-tosource voltage vDS

for an enhancementtype NMOS

transistor operated

with vGS > Vt.

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Increase vDS beyond this value has little effect on the channel

shape, and the current through the channel remains constant at the

value reached for vDS = vGS Vt

The drain current thus saturates at this value, and the MOSFET is

said to have entered the saturation region.

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The voltage vDS at which saturation occurs is denoted vDSsat, vDSsat =

vGS - Vt

Obviously, for every value of vGS Vt, there is a corresponding

value of vDSsat. The device operates in the saturation region if vDS

vDSsat .

The region of the iD vDS characteristic obtained for vDS < vDSsat is

called the triode region.

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vDS is increased while vGS is kept constant.

Theoretically, any increase in vDS above vDSsat (which is equal to

vGS - Vt ) has no effect on the channel shape and simply appears

across the depletion region surrounding the channel and the n+

drain region.

Eventually, as vDS reaches vGS Vt the channel is pinched off at the

drain end. Increasing vDS above vGS Vt has little effect

(theoretically, no effect) on the channels shape.

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Derivation of the iD-vDs Relation

A voltage vGS is applied between gate and source with vGS > Vt, and

a voltage vDS is applied between drain and source.

First consider operation in the triode region. i.e. let vDS < vGS Vt.

The channel will have the tapered shape illustrated in this figure.

characteristic of the

NMOS transistor.

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In the MOSFET, the gate and the channel region form a

parallelplate capacitor for which the oxide layer serves as a

dielectric. If the capacitance per unit gate area is denoted Cox and

the thickness of the oxide layer is tox, then

Cox

e ox

tox

and tox the thickness of the oxide layer.

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Consider an infinitesimal portion of the channel of length dx at a

point x from the source.

The electron charge dq(x) in this infinitesimal portion can be

expressed as dq x C (Wdx) v v x V

ox

t

GS

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The voltage vDS produces an electric field along the channel in the

negative x direction. At point x, this field can be expressed as

E x

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dv x

dx

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36

The electric field E(x) causes the electron charge dq(x) to drift

toward the drain with a velocity dx/dt

dv x

dx

mn E x mn

dt

dx

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37

The resulting drift current

dv x

dq dq x dx

i

CoxW vGS v x Vt mn

dt

dx dt

dx

dv x

mnCoxW vGS v x Vt

dx

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38

Although evaluated at a particular point in the channel, the current i

must be constant at all points along the channel, and thus i must be

the negative of the drain-to-source current iD, giving

dv( x)

iD i mnCoxW vGS v x Vt

dx

iD dx mnCoxW vGS Vt v x dv( x)

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Integrating both sides of this equation for x = 0 to x = L, and for

v(0) = 0 to v(L) = vDS.

L

vDS

0 iD dx 0 mnCoxW vGS Vt v x dv x

Gives

1 2

W

iD mnCox vGS Vt vDS vDS

2

L

region.

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The expression for the saturation region can be obtained by

substituting vDS = vGS Vt, resulting in

1

2

W

iD mnCox vGS Vt

2

L

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Process transconductance parameter

k mnCox

'

n

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Triode region:

iD kn'

Saturation region:

where

W

1 2

vDS

GS

t

DS

L

2

1 W

2

iD kn' vGS Vt

2 L

kn' m nCox

W to the channel length L, known as the aspect ratio of the

MOSFET.

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43

Example

Consider a process technology for which Lmin = 0.4 mm, tox = 8 nm,

mn = 450 cm2/Vs, and Vt = 0.7 V.

/

(a) Find Cox and k n.

(b) For a MOSFET with W / L = 8 mm/0.8 mm, calculate the values of

VGS and VDSmin needed to operate the transistor in the saturation

region with a dc current ID = 100 mA.

(c) For the device in (b), find the value of VGS required to cause the

device to operate as a 1000-W resistor for very small vDS.

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Solution

/

(a) Find Cox and k n.

Cox

e ox

tox

3.45 1011

3

2

4.32

10

F/m

8 109

4.32 fF/m m 2

kn mnCox 450 (cm 2 /V s) 4.32 (fF/m m 2 )

450 108 (m m 2 /V s)

194 10-6 (F/V s)

194 m A/V 2

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45

(b) calculate the values of VGS and VDSmin needed to operate the

transistor in the saturation region with a dc current ID = 100 mA.

For operation in the saturation region,

1 W

iD kn (vGS Vt )2

2 L

Thus,

1

8

100 194

(VGS 0.7)2

2

0.8

which results in

or

and

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VGS 1.02 V

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46

(c) For the device in (b), find the value of VGS required to cause the

device to operate as a 1000-W resistor for very small vDS.

For the MOSFET in the triode region with vDS very small,

W

iD kn (vGS Vt )vDS

L

From which the drain-to-source resistance rDS can be found as

rDS

Thus,

which yields

Thus,

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vDS

iD

small vDS

1 kn (VGS Vt )

L

1000

1

194 106 10(VGS 0.7)

VChih-Wen

V

GS 1.22

Lu

47

The p-channel MOSFET

A p-channel enhancement-type MOSFET (PMOS transistor) is

fabricated on an n-type substrate with p+ regions for the drain and

source, and has holes as charge carriers.

The device operates in the same manner as the n-channel device

except that vGS and vDS are negative and the threshold voltage Vt is

negative.

Also, the current iD enters the source terminal and leaves through

the drain terminal.

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Both PMOS and NMOS transistors are utilized.

NMOS transistor is implemented directly in the p-type substrate.

PMOS transistor is fabricated in a specially created n region,

known as n well.

The two devices are isolated from each other by a thick region of

oxide that functions as an insulator.

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49

These characteristics can be measured at dc or at low frequencies

and thus are called static characteristics.

The dynamic effect that limit the operation of the MOSFET at high

frequencies and high switching speeds will be discussed in Section

3.8.

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Circuit Symbol

(a) Circuit symbol for the n-channel enhancement-type MOSFET.

(b) Modified circuit symbol with an arrowhead on the source

terminal to distinguish it from the drain and to indicate device

polarity (i.e., n channel). (c) Simplified circuit symbol to be used

when the source is connected to the body or when the effect of the

body on device operation is unimportant.

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51

The iD vDS Characteristics

There are three distinct regions of operation: the cutoff region, the

triode region, and the saturation region.

The saturation region is used if FET is to operate as an amplifier.

For operation as a switch, the cutoff and triode regions are utilized.

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52

To operate the MOSFET in the triode region we must first induce a

channel.

vGS Vt (Induced channel)

And then keep vDS small enough so that the channel remains

continuous.

This is achieved by ensuring that the gate-to-drain voltage is

vGS vDS Vt

vDS vGS Vt

Continuous channel

vGS vDS

W

1 2

iD k

vGS Vt vDS vDS

L

2

'

n

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53

If vDS is sufficiently small so that we can neglect the v2DS term.

iD

W

k

vGS Vt vDS

L

'

n

as a linear resistance rDS,

rDS

vDS

iD

'W

vDS small kn

L vGS Vt

vGS VGS

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54

Voltage,

VOV VGS Vt

as

rDS

' W

1 kn

L

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VOV

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55

To operate the MOSFET in the saturation, a channel must be induced,

vGS Vt

Induced channel

and pinched off at the drain end by raising vDS to a value that results

in the gate-to-drain voltage falling below Vt,

vGD Vt

vDS vGS Vt

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The boundary between the triode region and the saturation region is

characterized by

vDS vGS Vt

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Boundary

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57

Substituting the value of vDS into

W

1 2

iD k

vGS Vt vDS vDS

L

2

'

n

1 'W

2

iD kn vGS Vt

2 L

Thus in saturation the MOSFET

provides a drain current whose

value is independent of the drain

voltage vDS and is determined

by the gate voltage vGS according

to the square-law relationship.

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1 'W

2

iD kn vGS Vt

2 L

characteristic for an

enhancement-type NMOS

transistor in saturation (Vt = 1

V, kn W/L = 1.0 mA/V2).

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operating in the saturation region.

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Referring back to the iD-vDS characteristics, we note

that the boundary between the triode and the saturation regions is

shown as a broken-line curve. Since this curve is characterized by

vDS = vGS Vt, its equation can be found by substituting for vGS Vt

by in either the triode-region equation or the saturationregion equation.

This result is

1 'W 2

iD kn vDS

2 L

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NMOS transistor for operation in the triode region and in the

saturation region.

the terminal voltages of the

enhancement NMOS

transistor for operation in the

triode region and in the

saturation region.

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62

Finite Output Resistance in Saturation

Figure Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus

reducing the effective channel length (by DL).

length is in effect reduced, from L to L-L, a phenomenon known

as channel-length modulation.

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63

1

W

iD kn

(vGS Vt ) 2

2 L L

1 W

1

kn

(vGS Vt ) 2

2 L 1 (L / L)

1 W

kn

2 L

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L

2

1

(

v

V

)

t

GS

L

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64

1, if we

L vDS

where is a process-technology parameter with the

dimension of m m/V, we obtain for iD ,

1 W

iD kn 1 vDS (vGS Vt ) 2

2 L

L

Usually, / L is denoted ,

L

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1 'W

2

iD kn vGS Vt 1 vDS

2 L

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1 'W

2

iD kn vGS Vt 1 vDS

2 L

Figure Effect of vDS on iD in

the saturation region. The

MOSFET parameter VA

depends on the process

technology and, for a given

process, is proportional to the

channel length L.

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From this figure we observe that when the straight-line iD-vDS

characteristics are extrapolated they intercept the vDS-axis at the

point vDS = -VA, where VA is a positive voltage.

VA

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VA VA L

where V /A is entirely process-technology dependent with the

dimensions of V/m m.

1

iD

ro

k W

2

ro

VGS Vt

2 L

'

n

VA

1

ro

ID ID

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proportional to the dc bias current ID.

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69

Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation,

incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS

and is given by Eq. (4.22).

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Characteristics of the p-Channel MOSFET

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MOSFET. (b) Modified symbol with

an arrowhead on the source lead. (c)

Simplified circuit symbol for the

case where the source is connected to

the body. (d) The MOSFET with

voltages applied and the directions of

current flow indicated. Note that vGS

and vDS are negative and iD flows out

of the drain terminal.Chih-Wen Lu

71

To induce a channel

vGS Vt Induced-channel

where the threshold voltage Vt is negative.

or, equivalently,

vSG V

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72

W

1 2

iD k

vGS Vt vDS vDS

L

2

'

p

where vGS, Vt, and vDS are negative and the transconductance

parameter kp is given by

k p' m pCOX

where mp is the mobility of holes in the induced p-channel.

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vDS vGS Vt

Current

1 ' W

2

iD k p vGS Vt 1 vDS

2 L

where vGS, Vt, , and vDS are all negative.

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74

Relative levels of the terminal voltage of the enhancement-type

PMOS transistor for operation in the triode region and in the

saturation region.

terminal voltages of the

enhancement-type PMOS

transistor for operation in the

triode region and in the saturation

region.

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75

The Role of the Substrate The body Effect

In many applications the substrate terminal is connected to the

source terminal, which results in the pn junction between the

substrate and the induced channel having a constant zero bias.

In such a case the substrate does not play any role in circuit

operation and its existence can be ignored altogether.

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76

In integrated circuits, the substrate is usually connected to the most

negative power supply in an NMOS circuit.

The resulting reverse-bias voltage between source and body (VSB)

in an n-channel device) will have an effect on device operation.

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The reverse bias voltage will widen the depletion region.

The effect of VSB on the channel can be most conveniently

represented as a change in the threshold voltage Vt.

Increasing VSB results in an inverse in Vt according to the relationship

Vt Vt 0 g 2f f VSB 2f f

parameter with (2 ff) typically 0.6; g is a fabrication-process parameter

given by

2qN Ae s

COX

is the permittivity of silicon.

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78

Having studied the current-voltage characteristics of MOSFETs,

we now consider circuits in which only dc voltages and currents

are of concern.

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79

Example

Design the circuit so that the transistor

operates at ID = 0.4 mA and VD = +0.5 V.

The NMOS transistor has Vt = 0.7 V, mnCox =

100 m A/V2, L = 1 m m, and W = 32 m m.

Neglect the channel-length modulation effect

(i.e., assume that = 0).

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Solution

Since VD = 0.5 V is greater than VG, this means the NMOS

transistor is operating in the saturation region, and we use the

saturation-region expression of iD to determine the required value

of iD to determine the required value of VGS,

1

W

I D mnCox (VGS Vt )2

2

L

1

32 2

400 100 VOV

2

1

which results in

VOV 0.5 V

Thus,

VGS Vt VOV 0.7 0.5 1.2 V

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81

The gate is at ground potential. Thus the source must be at -1.2V, and

the required value of RS can be determined from

VS VSS

RS

ID

1.2 (2.5)

3.25 kW

0.4

To establish a dc voltage of +0.5 V at the drain,

we must select RD as follows:

VDD VD

RD

ID

2.5 0.5

5 kW

0.4

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Example

Design the circuit in this figure to obtain a current ID of 80 m A.

Find the value required for R, and find the dc voltage VD. Let the

NMOS transistor have Vt = 0.6 V, mnCox = 200 m A/V2, L = 0.8 m m,

and W = 4 m m. Neglect the channel-length modulation effect (i.e.,

assume = 0).

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83

Solution:

1

W

I D mnCox (VGS Vt ) 2

2

L

1

W 2

mnCox VOV

2

L

VOV

2I D

mnCox (W / L)

2 80

0.4 V

200 (4 / 0.8)

VGS Vt VOV 0.6 0.4 1 V

VD VG 1 V

VDD VD

R

ID

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Chih-Wen Lu

3 1

25 kW

0.080

84

Example

Design the circuit in this figure to establish a drain voltage of 0.1 V.

What is the effective resistance between drain and source at this

operating point? Let Vt = 1 V and k /n ( W / L ) = 1 mA/V2.

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85

Solution:

Since the drain voltage is lower than the gate voltage by 4.9 V and Vt =

1 V, the MOSFET is operating in the triode region. Thus the current ID

is given by

1

2

(VGS Vt )VDS 2 VDS

1

2

VDD VD 5 0.1

RD

12.4 kW

ID

0.395

I D kn

W

L

Since the transistor is operating in the triode region with a small VDS,

the effective drain-to-source resistance can be determined as follows:

VDS

0.1

rDS

253 W

I D 0.395

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Example

Analyze the circuit shown in this figure to determine the voltages at

all nodes and the currents through all branches. Let Vt = 1 V and k /n

( W / L ) = 1 mA/V2. Neglect the channel-length modulation effect

(i.e., assume = 0).

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Solution

Since the gate current is zero, the voltage at the gate is simply

determined by the voltage divider formed by the two 10-MW

resistors,

R

10

VG VDD

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G2

RG 2 RG1

10

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10 10

5 V

88

which this positive voltage at the gate, the NMOS transistor will be

turned on. We do not know, however, whether the transistor will be

operating in the saturation region or in the triode region. We shall

assume saturation-region operation, solve the problem, and then check

the validity of our assumption. Obviously, if our assumption turns out

not to be valid, we will have to solve the problem again for trioderegion operation. Refer to the previous figure. Since the voltage at the

gate is 5 V and the voltage at the source is ID (mA) X 6 (kW) = 6 ID, we

have

VGS 5 6I D

Thus ID is given by

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1 W

I D kn (VGS Vt ) 2

2 L

1

1 (5 6 I D 1) 2

2

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89

which results in the following quadratic equation in ID:

18I D2 25I D 8 0

This equation yields two values for ID : 0.89 mA and 0.5 mA. The first

value results in a source voltage of 6 X 0.89 = 5.34, which is greater

than the gate voltage and does not make physical sense as it would

imply that the NMOS transistor is cut off. Thus,

I D 0.5 mA

VS 0.5 6 3 V

VGS 5 3 2 V

VD 10 6 0.5 7 V

Since VD > VG Vt, the transistor is

operating in saturation, as initially assumed.

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90

Example

Design the circuit of this figure so that the transistor operates in

saturation with ID = 0.5 mA and VD = +3 V. Let the enhancementtype PMOS transistor have Vt = -1 V and k /n ( W / L ) = 1 mA/V2 .

Assume = 0. What is the largest value that RD can have while

maintaining saturation- region operation?

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91

Since the MOSFET is to be in saturation, we can write

1 W

I D k p (VGS Vt ) 2

2

L

1 W 2

k p VOV

2

L

Substituting ID : 0.5 mA and k /p W / L = 1 mA/V2 and recalling that for

a PMOS transistor VOV is negative, we obtain

and

VOV 1 V

VGS Vt VOV 1 1 2 V

can be achieved by the appropriate selection of the values of RG1 and

RG2. and possible selection is RG1 = 2 MW and RG2 = 3 MW.

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92

VD

3

RD

6 kW

I D 0.5

Saturation-mode operation will be maintained up to the point that VD

exceeds VG by |Vt|; that is, until

VD max 3 1 4 V

This value of drain voltage is obtain with RD given by

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4

RD

8 kW

0.5

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93

Example

The NMOS and PMOS transistors in the circuit of Fig. 4.25(a) are

/

/

matched with k n ( Wn / Ln ) = k p ( Wp / Lp ) = 1 mA/V2 and Vtn = Vtp = 1 V. Assuming = 0 for both devices, find the drain currents

iDN and iDP, as well as the voltage vO, for vI = 0 V, +2.5 V, and -2.5

V.

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94

Solution

The circuit for the case vI = 0 V. We note that since QN and QP are

perfectly matched and are operating at equal |VGS| (2.5 V), the circuit is

symmetrical, which dictates that vO = 0 V. Thus both QN and QP are

operating with |VDG| = 0 and, hence, in saturation. The drain currents

can be found from

I DP

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1

I DN 1 (2.5 1) 2

2

1.125 mA

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95

Next, we consider the circuit with vI = +2.5 V. Transistor QP will have

a VGS of zero and thus will be cut off, reducing the circuit to that shown

here. We note that vO will be negative, and thus vGD will be greater than

Vt, causing QN to operate in the triode region. For simplicity we shall

assume that vDS is small and thus use

1[2.5 (2.5) 1][vO (2.5)]

From the circuit diagram shown in Fig. 4.25(c),

we can also write

I DN

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0 vO

(mA)

10 (kW)

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96

These two equations can be solved simultaneously to yield

I DN 0.244 mA

vO -2.44 V

Finally, the situation for the case vI = -2.5 V will be the exact

complement of the case vI = +2.5 V: Transistor QN will be cut off. Thus

IDN = 0, QP will be operating in the triode region with IDP = 2.44 mA

and vO = +2.44 V.

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97

In this section we begin our study of the use of MOSFETs in the

design of amplifier circuits. The basis for this important MOSFET

application is that when operated in the saturation region, the

MOSFET acts as a voltage-controlled current source: Change in the

gate-to-source voltage vGS give rise to changes in the drain current

iD. Thus the saturated MOSFET can be used to implement a

transconductance amplifier.

We will study the total or large-signal operation of a MOSFET

amplifier. We will do this by deriving the voltage transfer

characteristic of a commonly used MOSFET amplifier circuit.

From the voltage transfer characteristic we will be able to clearly

see the region over which the transistor can be biased to operate as

a small-signal amplifier as well as those regions where it can be

operated as a switch.

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Large-Signal Operation-The Transfer Characteristic

Figure (a) Basic structure of the common-source amplifier. (b) Graphical construction to

determine the transfer characteristic of the amplifier in (a).

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100

Graphical Derivation of the Transfer Characteristic

VDD 1

iD

vDS

RD RD

The straight line intersects

the vDS -axis at VDD [since

vDS VDD at iD 0]

and has a slope of -1/RD

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The graphical construction

can now be used to determine vO (equal to

vDS ) for each given value of vI (vGS vI ).

vGS vI , vI Vt , cut off, iD 0, and

vO vDS VDD . Operate at point A.

vI exceed Vt , turn on, iD increases, and vO

decreases, operate at saturation region,

from A to B.

A particular point :Q. VGS VIQ and has

the coordinates VOQ VDSQ and I DQ .

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Saturation-region operation continues

until vO decreases to the point that it

is below vIB by Vt volts. vDS vGS Vt ,

enters triode region, point B.

VOB VIB Vt

vI VIB , deeper in to triode region,

output voltage decreases slowly

towards zero.

Point C, vI VDD

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103

When the MOSFET is used

as a switch, it is operated at

the extreme points of the

transfer curve.

Specifically, the device is

turned off by keeping vI < Vt

resulting in operation

somewhere on segment XA

with vO = VDD.

The switch is turned on by

applying a voltage close to

VDD, resulting in operation

close to point C with vO very

small ( at C, vO = VOC ).

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characteristic showing operation as an

amplifier biased at point Q.

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104

Operation as a linear

Amplifier

dvO

Av

dvI

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vI VIQ

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105

Figure Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for

positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the

triode region and might not allow for sufficient

negative

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Lu signal swing.

106

Analytical Expressions for the Transfer Characteristic

The Saturation-Region Segment, AQB , vI Vt, and vO vI Vt . Neglecting channel-length modulation and substituting for

iD from

into

gives

1

W

iD ( mnCox )

2

L

2

(

v

V

)

t

I

vO VDD RDiD

1

W

vO VDD RD mnCox (VI Vt )2

2

L

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107

dvO

A v

dvI

vI VIQ

W

Av RD mnCox (VIQ Vt )

L

VIQ Vt VOV

Av

2(VDD VOQ )

VOV

2VRD

VOV

The end point of the saturation-region segment

is characterized by

VOB VIB Vt

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The Triode-Region Segment, BC, vI Vt, and vO vI

- Vt .

W

1 2

(

v

V

)

v

vO

I

t

O

L

2

vO VDD RD iD

iD mnCox

W

1 2

(

v

V

)

v

vO

I

t

O

L

2

The portion of this segment for which vO is small is given aproximately by

vO VDD RD mnCox

W

vO VDD RD mnCox (vI Vt )vO

L

which reduces to

W

L

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109

L

rDS

vO VDD

rDS RD

rDS

RD

vO VDD

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rDS

RD

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110

Example

To make the above analysis more

concrete we consider a numerical

example. Specifically, consider the CS

circuit for the case k /n ( W / L ) = 1 mA/V2

, Vt = 1 V, RD = 18 kW, and VDD = 10 V.

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Solution

First, we determine the coordinates of important points on the transfer

curve.

(a) Point X:

(b) Point A:

vI 0 V,

vO 10 V

vI 1 V,

vO 10 V

vO VOB

2

9VOB

VOB 10 0

VOB 1 V

VIB 1 1 2 V

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112

(d) Point C:

VOC

10

0.061 V

1 18 1 (10 1)

saturation-region segment. Since this segment extends from vO = 1 V

to 10 V, we choose to operate at VOQ = 4 V.

ID

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VDD VOQ

RD

10 4

0.333 mA

18

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113

1 W 2

I D kn VOV

2 L

2 0.333

VOV

0.816 V

1

Thus, we must operate the MOSFET at a dc gate-to-source voltage

The voltage-gain of the amplifier at this bias point:

AV 18 1 (1.816 1)

14.7 V/V

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114

At vGS 1.816 V, iD 12 1 (1.816-1) 2 0.333 mA

At vGS 1.891 V, iD 12 1 (1.891-1) 2 0.397 mA

At vGS 1.741 V, iD 0.275 mA, and vO 10 0.275 18 5.05 V

At v

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115

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A Final Remark on Biasing

In the above example, the MOSFET was assumed to be biased at a

constant vGS of 1.816 V. Although it is possible to generate a

constant bias voltage using an appropriate voltage-divider network

across the power supply VDD or across another reference voltage

that may be available in the system, fixing the value of vGS is not a

good biasing technique.

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As mentioned in the previous section, an essential step in the

design of a MOSFET amplifier circuit is the establishment of an

appropriate dc operating point for the transistor. This is the step

known as biasing or bias design. An appropriate dc operating point

or bias point is characterized by a stable and predictable dc drain

current ID and by a dc drain-to-source voltage VDS that ensures

operation in the saturation region for all expected input-signal

levels.

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Biasing by Fixing VGS

1

W

I D mnCox (VGS Vt )2

2

L

Figure The use of

fixed bias (constant

VGS) can result in a

large variability in the

value of ID. Devices 1

and 2 represent

extremes among units

of the same type.

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Biasing by Fixing VG and Connecting a Resistance in the Source

VG VGS RS I D

Figure Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic

arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply;

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120

Figure (c) practical implementation using a single supply; (d) coupling of a signal source to

the gate using a capacitor CC1; (e) practical implementation using two supplies.

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121

Example

It is required to design the circuit to establish a

dc drain current ID = 0.5 mA. The MOSFET is

specified to have Vt = 1 V and k /n W / L = 1 mA/V2 .

For simplicity, neglect the channel-length modulation

effect (i.e., assume = 0). Use a power-supply VDD = 15

V. Calculate the percentage change in the value of ID

obtained when the MOSFET is replaced with another unit

/

having the same k n W / L but Vt = 1.5 V.

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Solution

VD 10 V and VS 5 V.

VDD VD 15 10

RD

10 kW

ID

0.5

VS

5

RD

10 kW

RS 0.5

2

I D 12 kn (W / L)VOV

2

0.5 12 1 VOV

VOV 1 V

VGS Vt VOV 1 1 2 V

VG VS VGS 5 2 7 V

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123

We may select RG1 8 MW and RG 2 7 MW.

The dc voltage at the drain (+10 V) allows for

a positive signal swing of +5 V (up to VDD ) and

a negative signal swing of -4 V [down to (VG Vt )]

If the NMOS transistor is replaced with another

having Vt 1.5 V:

I D 12 1 (VGS 1.5) 2

VG VGS I D RS

7 VGS 10 I D

I D 0.455 mA

I D 0.455 0.5 0.045 mA

0.045

which is

100 9% change.

0.5

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124

Biasing Using a Drain-to-Gate Feedback Resistor

VDD VGS RD I D

drain-to-gate feedback resistance, RG.

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125

Biasing Using a Constant-Current Source

whose drain is shorted to its gate and

thus is operating in the saturation

region, such that

1 W

kn (VGS Vt ) 2

2 L 1

assume 0. The drain current of Q1

I D1

Since the gate current are zero,

I D I REF

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Figure (a) Biasing the MOSFET using a constantcurrent source I. (b) Implementation of the constantChih-Wen Lu current source I using a current mirror.

126

Now consider transistor Q2 :

It has the same as :thus if we

assume that it is operating in

saturation, its drain current,

which is the desired current

of the current source, will be

I ID2

1 W

kn (VGS Vt ) 2

2 L 2

(W / L) 2

I I R EF

(W / L)1

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A Final remark

The bias circuit studied in this section are intended for discretecircuit application. The only exception is the current mirror circuit

which, as mentioned above, is extensively used in IC design.

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128

In our study of the large-signal operation of the common-source

MOSFET amplifier in Section 3.4 we learned that linear

amplification can be obtained by biasing the MOSFET to operate

in the saturation region and by keeping the input signal small.

Having studied methods for biasing the MOS transistor in the

previous section, we now turn our attention to exploring smallsignal operation in some detail.

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Here the MOS transistor is biased by applying a dc voltage VGS, a

clearly impractical arrangement but one that is simple and useful

for our purposes. The input signal to be amplified, vgs, is shown

superimposed on the dc bias voltage VGS. The output voltage is

taken at the drain.

utilized to study the operation

of the MOSFET as a smallsignal amplifier.

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The DC Bias Point

1 W

I D kn (VGS Vt ) 2

2 L

0, VDS or simply VD (since S is grounded), will be

VD VDD RD I D

To ensure saturation-region operation, we must have

VD VGS Vt

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The Signal Current in the Drain Terminal

vgs is applied, the total instantaneous gate-to-source voltage:

vGS VGS vgs

total instantaneous drain current:

1 W

iD kn (VGS vgs Vt ) 2

2 L

1 W

W

1 W 2

2

2 L

L

2 L

To reduce the nonlinear distortion, the input signal should be

kept small so that

1 W 2

W

2 L

L

vgs 2(VGS Vt ) or, equivalently, vgs

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2VOV

132

If the small-signal condition is satisfied,

iD I D id

where

W

(VGS Vt )vgs

L

id

W

gm

kn (VGS Vt )

vgs

L

id kn

W

g m kn VOV

L

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133

iD

gm

vGS

vGS VGS

enhancement MOSFET amplifier.

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134

The Voltage Gain

vD VDD RD iD

vD VDD RD ( I D iD )

vD VD RD id

vd id RD g m vgs RD

vd

Av

g m RD

vgs

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135

vd

Av

g m RD

vgs

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136

Separating the DC Analysis and the Signal Analysis

From the preceding analysis, we see that under the small-signal

approximation, signal quantities are superimposed on dc quantities.

It follows that the analysis and design can be greatly simplified by

separating dc or bias calculations from small-signal calculation.

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Small-Signal Equivalent-Circuit Models

ro

VA

ID

Figure Small-signal models for the MOSFET: (a) neglecting the dependence

of iD on vDS in saturation (the channel-length modulation effect); and (b)

including the effect of channel-length modulation, modeled by output

resistance ro = |VA| /ID.

ro

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VA

ID

1 W 2

I D kn VOV

2 L

Chih-Wen Lu

vd

Av

g m ( RD ro )

vgs

138

The Transconductance gm

g m kn (W / L)(VGS Vt ) kn (W / L)VOV

substitute (VGS Vt ) by 2 I D /( kn (W / L))

g m 2kn W / L I D

This expression shows that

1. For a given MOSFET, g m is proportional to the square

root of the dc bias current.

2. At a given bias current, g m is proportional to W / L .

Another useful expression for g m , substitute kn (W / L)

by 2 I D /(VGS Vt ) 2

2I D

2I D

gm

VGS Vt VOV

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139

Example: We wish to analyze this amplifier circuit to determine its

small-signal voltage gain, its input resistance, and the largest

/

allowable input signal. The transistor has Vt = 1.5, k n ( W / L ) =

0.25 mA/V2 , and VA = 50 V. Assume the coupling capacitors to be

sufficiently large so as to act as short circuits at the signal

frequencies of interest.

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140

Solution

I D 12 0.25(VGS 1.5) 2

VGS VD

I D 0.125(VD 1.5) 2

VD 15 RD I D 15 10 I D

I D 1.06 mA and VD 4.4 V

W

g m kn (VGS Vt )

L

0.25(4.4 1.5) 0.725 mA/V

VA

50

ro

47 kW

I D 1.06

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141

vo

g m vgs ( RD RL ro )

vgs vi

vo

Av g m ( RD RL ro )

vi

0.725(10 10 47) 3.3 V/V

ii (vi vo ) / RG

vi

RG

vo

1

vi

vi

4.3vi

[1 (3.3)]

RG

RG

vi RG 10

Thus, Rin

2.33 MW

ii 4.3 4.3

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142

The largest allowable input signal vi is determined by the need

to keep the MOSFET in saturation at all times; that is

vDS vGS Vt

Enforcing this condition, with equality, at the point vGS is maximum

and vDS is correspondingly minimum, we write

vDS min vGS max Vt

which results in

vi 0.34 V

In that in the negative direction, this input signal amplitude results in

vGS min 4.4 0.34 4.06 V

the

maximum allowable input signal

peakLuis 0.34 V.

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143

The T Equivalent-Circuit Model

equivalent-circuit model for

the MOSFET. For simplicity,

ro has been omitted but can be

added between D and S in the

T model of (d).

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144

Figure (a) The T model of the MOSFET augmented with the drain-to-source

resistance ro. (b) An alternative representation of the T model.

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145

Modeling the Body Effect

The signal vbs gives rise to a drain-current component, which we

shall write as gmbvbs, where gmb is the body transconductance,

defined as

g mb

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iD

vBS

v constant

GS

vDS constant

Chih-Wen Lu

146

g mb g m

where

Vt

g

VSB 2 2f f VSB

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model of a MOSFET in which the source

is not connected to the body.

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147

Having studied MOS amplifier biasing and the small-signal

operation and models of the MOSFET amplifier , we are now ready

to consider the various configuration utilized in the design of MOS

amplifiers.

Discrete MOS amplifiers are easier to understand than their IC

counterparts for two main reasons: The separation between dc and

signal quantities is more obvious in discrete circuits, and discrete

circuits utilize resistors as amplifier load.

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148

The Basic Structure

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to realize single-stage discrete-circuit

MOS amplifier configurations.

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149

The Common-Source (CS) Amplifier

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150

amplifier for small-signal analysis.

ig 0

RG

Rin RG

vgs vi

vi vsig

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RG

Rin

Chih-Wen Lu

Rsig

vi vsig

vo g m vgs (ro RD RL )

151

Av g m (ro RD RL )

Avo g m (ro RD )

RG

Rin

Gv

Av

g m (ro RD RL )

Rin Rsig

RG Rsig

Rout ro RD

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152

Figure (c) Small-signal analysis performed directly on the amplifier circuit with the

MOSFET model implicitly utilized.

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153

The Common-Source Amplifier with a Source Resistance

resistance RS in the source lead.

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154

circuit with ro neglected.

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155

Rin Ri RG

vi vsig

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RG

RG Rsig

vgs vi

Chih-Wen Lu

1

gm

1

Rsig

gm

vi

1 g m Rs

156

vi

g m vi

id i

1

RS 1 g m Rs

gm

g m ( RD RL )

Av

1 g m Rs

vo id ( RD RL )

g m ( RD RL )

1 g m Rs

g m RD

Avo

1 g m Rs

RG

g m ( RD RL )

Gv

RG Rsig 1 g m Rs

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157

The Common-Gate (CG) Amplifier

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158

of the amplifier in (a).

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159

1

Rin

gm

vi vsig

vi vsig

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1

gm

1

Rsig

gm

Chih-Wen Lu

Rin

Rin Rsig

1

vsig

1 g m Rsig

160

1

gm

Rsig

ii

1

gm

Av

Rin

Gv

Av

Av

1

Rin Rsig

1 g m Rsig

Rsig

gm

vi

v

i g m vi

Rin 1/ g m

Gv

g m ( RD RL )

1 g m Rsig

id i ii g m vi

vo vd id ( RD RL ) g m ( RD RL )vi

Rout Ro RD

Av g m ( RD RL )

Avo g m RD

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161

ii isig

Rsig

Rsig Rin

Normally, Rsig

isig

Rsig

1

Rsig

gm

1/ g m

ii isig

fed with a current-signal input.

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162

The Common-Drain or Source-Follower Amplifier

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163

Rin RG

vi vsig

RG

Rin

vsig

Rin Rsig

RG Rsig

vi vsig

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164

vo vi

Av

Avo

RL ro

( RL ro )

1

gm

RL ro

( RL ro )

1

gm

ro

1

ro

gm

Normally ro

1/ g m , Avo

1. Also, in many

discrete-circuit application, ro

Av

RL ,

RL

RL

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1

gm

Chih-Wen Lu

165

RG

RL ro

Gv

RG Rsig ( R r ) 1

L

o

gm

which approaches unity for

RG Rsig , ro 1 / g m , and ro

2015/2/23

RL .

Chih-Wen Lu

166

2015/2/23

Chih-Wen Lu

167

Rout

ro

gm

Normally, ro

Rout

gm

2015/2/23

1/ g m , reducing Rout to

Figure (d) Circuit for determining the output

resistance

Rout of the source follower. 168

Chih-Wen

Lu

the MOSFET:

1. The gate capacitive effect: The gate electrode (polysilicon) forms

a parallel-plate capacitor with the channel, with the oxide layer

serving as the capacitor dielectric.

2. The source-body and drain-body depletion-layer capacitances:

These are the capacitances of the reverse-biased pn junction formed

by the n+ source region (also called the source diffusion) and the ptype substrate and by the n+ drain region (the drain diffusion) and

the substrate.

2015/2/23

Chih-Wen Lu

169

2015/2/23

Chih-Wen Lu

170

For the source diffusion, we have the source-body capacitance:

Csb

Csb 0

VSB

1

V0

Cdb

Cdb 0

1

2015/2/23

VDB

V0

Chih-Wen Lu

171

circuit model for the MOSFET.

the source is connected to the substrate (body).

2015/2/23

Chih-Wen Lu

172

Figure (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis).

2015/2/23

Chih-Wen Lu

173

Io

gm

I i s (Cgs Cgd )

I o g mVgs sCgdVgs

Io

T g m /(Cgs Cgd )

g mVgs

gm

fT

2 (Cgs Cgd )

2015/2/23

Chih-Wen Lu

174

The basic CMOS inverter utilizes two matched enhancement-type

MOSFETs: one, QN, with an n channel and the other, QP, with a p

channel. The body of each device is connected to its source and

thus no body effect arises.

2015/2/23

Chih-Wen Lu

175

Circuit Operation

2015/2/23

inverter when vI is high: (a) circuit

with vI = VDD (logic-1 level, or VOH);

(b) graphical construction to determine

the operating point; (c) equivalent

circuit.

Chih-Wen Lu

176

obtained using Eq. (4.13) as

W

L n

inverter when the input is high. This circuit

confirms that vO VOL 0 V and that the power

dissipation in the inverter is zero.

2015/2/23

Chih-Wen Lu

177

(a) circuit with vI = 0 V (logic-0 level, or VOL); (b)

graphical construction to determine the operating point;

(c) equivalent circuit.

2015/2/23

Chih-Wen Lu

178

inverter when the input is low. Here we see that

QP provides a low-resistance path between the

output terminal and the dc supply VDD , with the

resistance given by

W

L p

vO VOH VDD and that the power dissipation in

the2015/2/23

inverter is zero.

Chih-Wen Lu

179

The Voltage Transfer Characteristic

2015/2/23

Chih-Wen Lu

180

For QN ,

iDN

iDN

1 2

W

k vI Vtn vO vO

2

L n

1 W

2

kn' vI Vtn

2 L n

'

n

for vO vI Vtn

for vO vI Vtn

For QP ,

iDP

W

k VDD vI Vtp

L p

'

p

1

2

VDD vO VDD vO

2

for vO vI Vtp

iDP

1 ' W

k p VDD vI Vtp

2 L p

2015/2/23

for vO vI Vtp

Chih-Wen Lu

181

The CMOS inverter is usually designed to have

Vtn Vtp

W

' W

k kp

L n

L p

'

n

mn

Wn m p

Wp

2015/2/23

Chih-Wen Lu

182

Determine VIH

QN: triode region

QP: saturation region

1

W

iDN kn' vI Vtn vO vO2

2

L n

2

1 ' W

iDP k p VDD vI Vtp

2 L p

iDN iDP

1 2 1

2

vI Vt vO vO VDD vI Vt

2

2

2015/2/23

Chih-Wen Lu

183

1 2 1

2

vI Vt vO vO VDD vI Vt

2

2

Differentiating both sides relative to vI

dvO

dvO

vI Vtn vO vO

dvI

dvI

VDD vI Vt

Substituting vI = VIH

and dvO/d vI = -1

VDD

vO VIH

2

1

VIH 5VDD 2Vt

8

2015/2/23

Chih-Wen Lu

184

VIL can be determined in a manner similar to that used to find VIH.

Alternatively, we can use the

symmetry relationship

VDD VDD

VIH

VIL

2

2

1

VIL 3VDD 2Vt

8

2015/2/23

Chih-Wen Lu

185

The noise margins

NM H VOH VIH

1

VDD 5VDD 2Vt

8

1

3VDD 2Vt

8

NM L VIL VOL

1

3VDD 2Vt 0

8

1

3VDD 2Vt

8

2015/2/23

Chih-Wen Lu

186

Dynamic Operation

Dynamic Operation

2015/2/23

Chih-Wen Lu

Figure Dynamic

operation of a

capacitively loaded

CMOS inverter: (a)

circuit; (b) input and

output waveforms; (c)

trajectory of the

operating point as the

input goes high and C

discharges through

QN; (d) equivalent

circuit during the

187

capacitor discharge.

tPHL1:

vO = VDD ~ (VDD Vt)

Qn: saturation region

iDN

1 ' W

2

kn VDD Vt constant

2 L n

tPHL2 :

vO = (VDD Vt) ~ VDD/2)

Qn: triode region

iDN

1 2

W

k VDD Vt vO vO

2

L n

'

n

2015/2/23

Chih-Wen Lu

188

Calculate tPHL1

1

vO

C

t t PHL1

i dt V

DN

DD

t 0

t t PHL1

t 0

1 ' W

2

kn VDD Vt dt VDD

2 L n

1 1 ' W

2

C 2 L n

1 1 ' W

2

VDD Vt

kn VDD Vt t PHL1 VDD

C 2 L n

C VDD VDD Vt

CVt

t PHL1

1 ' W

1 ' W

2

2

kn VDD Vt

kn VDD Vt

2015/2/23

Chih-Wen Lu 2

2 L n

L n

189

Calculate tPHL2

dvO

iDN C

dt

iDN dt CdvO

1 2

W

k VDD Vt vO vO dt CdvO

2

L n

'

n

kn' W L n

2C

2015/2/23

dt

dvO

2 VDD Vt

2Chih-Wen

VDD LuVt

vO2 vO

190

kn' W L n

2C

t t PHL 2

dt

2 VDD Vt

kn' W L n

2C

t 0

kn' W L n

2C

dvO

dt

t PHL 2

2 VDD Vt

vO VDD 2

vO VDD Vt

vO2 vO

dvO

2 VDD Vt

2 VDD Vt

dvO

vO VDD 2

2 VDD Vt vO VDD Vt

vO2 vO

2 VDD Vt

vO2 vO

dx

1

ax 2 x ln 1 ax

3VDD 4Vt

t PHL 2 '

ln

VLuDD

n

C

191

Vt

2C

1 3VDD 4Vt

'

ln

tPHL

1.6C

'

kn W L n VDD

2015/2/23

Chih-Wen Lu

192

Current Flow and Power Dissipation

voltage.

2015/2/23

Chih-Wen Lu

193

At t = 0-, vO = VDD

Energy stored on the capacitor is 0.5CVDD2

At t = 0, vI goes high to VDD, the capacitor voltage is reduced to zero

During the discharge interval, energy of 0.5CVDD2 is removed from C

and dissipated in Qn.

2015/2/23

Chih-Wen Lu

194

charges the capacitor.

The energy drawn from the power supplied to the capacitor:

DD

Q CVDD

Thus the energy drawn from the supply during the charging interval

is CVDD2.

2015/2/23

Chih-Wen Lu

195

VDD, and thus the energy stored in it will be 0.5CVDD2 .

It follows that during the charging interval, half of the energy

drawn from the supply, 0.5CVDD2 , is dissipated in QP.

In every cycle, 0.5CVDD2 of energy is dissipated in QN and

0.5CVDD2 dissipated in QP, for a total energy dissipation in the

inverter of CVDD2 .

2015/2/23

Chih-Wen Lu

196

dynamic power dissipation in it will be

2

CVDD

PD

T

2

fCVDD

technology is the delay-power product (DP),

2015/2/23

DP PDChih-Wen

tP

Lu

197

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