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# 3/16/2015

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3Counters
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Inparticular,wewanttodesigncircuitsthatcanincrementordecrementacountby1.Countercircuitsareusedindigital systems
for many purposes. They may count the number of occurrences of certain events, generate timing intervals for control of various
the contents of a counter by 1, it is not necessary to use such elaborate circuits. Instead, we can use much simpler circuits that
haveasignificantlylowercost.WewillshowhowthecountercircuitscanbedesignedusingTandDflipflops.

3.1Asynchronouscounters
The simplest counter circuits can be built using T flipflops because the toggle feature is naturally suited for the
implementationofcountingoperation.
3.1.1UpCounterwithTFlipFlops

Figure1agivesathreebitcounter capable of counting from 0 to 7. The clock inputs of the three flipflops are connected
incascade.TheTinputofeachflipflop is connected to a constant 1, which means that the state of the flipflop will be reversed
(toggled)ateachpositiveedgeofitsclock.Weareassumingthatthepurposeofthiscircuitistocountthenumberofpulsesthat
occurontheprimaryinputcalledClock.ThustheclockinputofthefirstflipflopisconnectedtotheClockline.Theothertwoflip
flopshavetheirclockinputsdrivenbytheQoutputoftheprecedingflipflop.

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Figure1Athreebitupcounter.

Therefore,theytoggletheirstatewhenevertheprecedingflipflopchangesitsstatefromQ=1toQ=0,whichresultsin
apositiveedgeoftheQsignal.
Figure1bshowsatimingdiagramforthecounter.ThevalueofQ0 toggles once each clock cycle. The change takes place
shortly after the positive edge of the Clocksignal. The delay is caused by the propagation delay through the flipflop. Since the
secondflipflopisclockedbyQ0,thevalueofQ1changesshortlyafterthenegativeedgeoftheQ0signal.Similarly,thevalueof
Q2 changes shortly after the negative edge of the Q1 signal. If we look at the values Q2Q1Q0 as the count, then the timing
diagramindicatesthatthecountingsequenceis0,1,2,3,4,5,6,7,0,1,andsoon.Thiscircuitisamodulo8counter. Because
itcountsintheupwarddirection,wecallitanupcounter.
Thecounter in Figure 1a has three stages,each comprising a singleflipflop. Only the first stage responds directly to the
Clock signal we say that this stage is synchronized to the clock. The other two stages respond after an additional delay. For
example,whenCount=3,thenextclockpulsewillcausetheCountto go to 4. As indicated by the arrows in the timing diagram
in Figure 1b, this change requires the toggling of the states of all three flipflops. The change in Q0 is observed only after a
propagationdelayfromthepositiveedgeofClock.TheQ1andQ2flipflopshavenotyetchangedhenceforabriefcountis000.
Finally,thechangeinQ2occursafterathirddelay,atwhichpointthestablestateofthecircuitisreachedandthecountis
100. This behavior is similar to the rippling of carries in the ripplecarry adder circuit. The circuit in Figure 1a is an asynchronous
counter,oraripplecounter.
3.1.2DownCounterwithTFlipFlops

AslightmodificationofthecircuitinFigure1aispresentedinFigure2a.TheonlydifferenceisthatinFigure2atheclock
inputs of the second and third flipflops are driven by the Q outputs of the preceding stages, rather than by the Q outputs. The
timingdiagram,giveninFigure2b,showsthatthiscircuitcountsinthesequence0,7,6,5,4,3,2,1,0,7,andsoon.Becauseit
ItispossibletocombinethefunctionalityofthecircuitsinFigures1aand2atoformacounterthatcancounteitherupor

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Figure2Athreebitdowncounter

3.2Synchronouscounters
TheasynchronouscountersinFigures1aand2a are simple, but not very fast. If a counter with a larger number of bits is
constructed in this manner, then the delays caused by the cascaded clocking scheme may become too long to meet the desired
performancerequirements.Wecanbuildafastercounterbyclockingallflipflopsatthesametime,usingtheapproachdescribed
below.
Table1showsthecontentsofathreebitupcounterforeightconsecutiveclockcycles,assumingthatthecountisinitially
0. Observing the pattern of bits in each row of the table, it is apparent that bit Q0 changes on each clock cycle. Bit Q1 changes
onlywhenQ0=1.BitQ2changesonlywhenbothQ1andQ0areequalto1.Ingeneral,forannbitupcounter, a given flipflop
changes its state only when all the preceding flipflops are in the state Q = 1. Therefore, if we use T flipflops to realize the
counter,thentheTinputsaredefinedas
T0=1
T1=Q0
T2=Q0Q1
T3=Q0Q1Q2
...
...
...
Tn=Q0Q1Qn1
does not slow down the response of the counter, because all flipflops change their states after a propagation delay from the
positiveedgeoftheclock.

Table1Derivationofthesynchronousupcounter

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Figure3Afourbitsynchronousupcounter

Note that a change in the value of Q0 may have to propagate through several AND gates to reach the flipflops in the
higher stages of the counter, which requires a certain amount of time. This time must not exceed the clock period. Actually, it
mustbelessthantheclockperiodminusthesetuptimefortheflipflops.
Figure3bgives a timing diagram. It shows that the circuit behaves as a modulo16 upcounter. Because all changes take
placewiththesamedelayaftertheactiveedgeoftheClocksignal,thecircuitiscalledasynchronouscounter.

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