White Paper

Power Hungry? Series

Advanced Dynamic Power

Reduction Techniques
January 2009

Author
Kajin Shi
Principal Consultant,
SPS, Synopsys, Inc.

Introduction
Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design
flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and
dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and

Neel Desai
Product Marketing
Manager, SPS,
Synopsys, Inc.

signal integrity closure is now tightly coupled with power optimization and power net distribution. More

David Stringfellow
Staff Consultant,
SPS, Synopsys, Inc.

paper, Advanced Dynamic Power Reduction Techniques, is a follow-on to a previously published white

importantly, increases in SoC size and speed have brought heat dissipation and reliability issues such as
electromigration and IR drop to center stage for a wide range of design applications.
Fortunately, design methods have evolved rapidly to address these critical power issues. This white
paper from Synopsys Professional Services, Power Hungry? Strategies to Trim Your Chips Appetite.
Intended to be an introduction to power management concepts, Power Hungry? Strategies to Trim Your
Chips Appetite serves as a fundamental starting point and provides an overview of the power dilemma.
It describes methods for estimating and analyzing power consumption based on the latest EDA tool
technology. A description of power-related tradeoffs, beginning at the architectural level, is also covered.
In this new white paper we will describe, in detail, three power-management methods that address
dynamic sources of power consumption: operand isolation, operand pre-computation and multiple
supply voltage (Multi-VDD).
For additional information on dealing with power-related reliability issues, please consult the Synopsys
Professional Services white paper entitled, Power Integrity for SoCs: Power Planning and Signoff Flows.

Operand Isolation and Operand Pre-Computation

Operand isolation
Todays complex designs have multiple parallel data paths, selected with data multiplexing logic (mux),
that result in redundant switching activity. This redundant activity results in unnecessary dynamic power
consumption. Operand isolation techniques are often used to reduce redundant switching in such data
paths by selectively blocking the propagation of switching activity through the unused portion of the
circuit. By adding gating cells at the inputs of the data paths feeding the mux, power can be saved. Muxselect signals control these gating cells to prevent any signal switching in the data paths except at the
selected input. Figure 1 shows an example of the technique.

Stops data feeding into

The operator, unless
output is required

Automatically inserts
activation logic

AS
SEL_0

SEL_1

DATA_1
+
DATA_2
Add_0

Automatically inserts
isolation logic

0
1

0
1

mux_0 mux_1

reg_0

Timing-driven automatic
or rollback

Figure 1: Operand Isolation (OI)

Synopsys synthesis tool, Design Compiler Ultra (DC Ultra), can identify opportunities for applying operand
isolation and insert the necessary control logic automatically:
# read in switching activity files
read_saif -input risc.saif -instance testrisc/proc
# issue OI constraints
set do_operand_isolation true
set_operand_isolation_style -logic adaptive -verbose
# set weight to a non-zero number to enable auto-rollback
set_operand_isolation_slack 0.3 -weight 1
# source design constraints
source design_constr.tcl
compile_ultra
# report and analysis
report_operand_isolation -verbose -all
report_timing
report_power
Furthermore, designers can often identify additional opportunities to apply this technique, based on their lowpower design expertise and understanding of the design (e.g., unused IP functionality). These opportunities
are defined by RTL pragmas or the command set_operand_isolation_cell, which is then used by DC
Ultra to insert the operand isolation logic.
It is important to keep in mind that the logic associated with isolating the operand itself consumes power and
will lead to use of additional area. As a result, this technique may not be worthwhile if the amount of isolated
combinational logic is relatively small. The operand isolation logic also introduces an extra path delay that can
result in timing violations in critical paths. Advanced tools such as DC Ultra evaluate the power savings against
the power overhead and only insert the operand isolation logic where the result is a reduction in power. The
tool will check the timing on affected paths during design optimization and remove any inserted operand
isolation logic that causes unfixable timing violations. Designers also have the ability to remove the inserted
operand isolation logic using the remove_operand_isolation command.

Advanced Dynamic Power Reduction Techniques

Operand pre-computation
Operand pre-computation is another technique that can be used for improving design speed and reducing
dynamic power consumption. This technique entails selectively pre-computing the output logic values of
the circuit one clock cycle before they are required and uses the pre-computed values to reduce internal
switching activity in the succeeding clock cycle. To implement this technique, the designer first needs to
identify a subset of input signals that determine the output of the datapath independent of other input signals.
A good example where this technique can be used is data comparison circuitry (a= =b). In a typical case,
the most significant bit (MSB) determines the result. By insert gating logic to prevent all but the MSB signals
from switching in the datapath, significant power savings can be achieved. As shown in Figure 2, if the MSBs
of signals a and b are not equal, the designer can eliminate switching power for registers a[6:0] and b[6:0] by
pre-comparing the MSBs of a and b and gating the clockstop of the rest of the registers. Similar to operand
isolation, clock gating is another form of dynamic power reduction, where the clock to sequential elements is
gated off, preventing those elements and the combinatorial logic they drive from switching unnecessarily.
Clock gating is generally performed with integrated clock gating (ICG) cells.

a[6:0]

b[6:0]

a[7]

b[7]

ICG

a == b

clk

Figure 2: Operand Pre-computation

Operand pre-computation is most effective in cases where the gated datapath logic is large and simple logic
can implement the pre-computation of a small subset of the inputs. Be aware that the techniques side effects
can include increased complexity, possible impact on worst negative slack (WNS), and required RTL changes.
Decisions about using the technique thus need to be made on a case-by-case basis. But effective use of this
technique can result in substantial reduction in dynamic power.

Multi-VDD design
Reducing supply voltage (VDD) is another effective way to reduce dynamic. This is because dynamic power is
proportional to the square of VDD, as shown in the following equation:
Dynamic Power = a * f * C * V2
As an added benefit, reducing supply voltage can also reduce leakage power, although to a lesser degree,
since leakage power varies linearly with VDD.
Since circuit timing will also vary with VDD, it is advisable to partition a design into multiple voltage (multi-VDD)
domains (also referred to as voltage areas or voltage islands in layout) based on timing criticality (Figure 3).

Advanced Dynamic Power Reduction Techniques

0.9V

0.7V

1.0V

0.9V

Figure 3: Multi-VDD design

For logic blocks that can operate at low clock speeds and are not timing critical, the supply voltage can be
reduced to a level that just maintains reliable operation of the block. Ideally each block will be supplied by
a dedicated VDD whose voltage level is just enough to guarantee acceptable operation. This would provide
optimal power utilization. However, such a circuit does require multiple power supplies, using internal or
external regulators, resulting in increased circuit area, design complexity, and cost. Designs implementing
multi-VDD would also need specialized matching libraries characterized at each of the required operating
voltages, further driving up costs. As a result of area penalties and added complexity to logic and physical
synthesis, production multi-VDD designs today generally do not use more than three core-logic supply
voltages.
Low-to-high level shifters are required to convert signals from low-VDD to high-VDD and prevent short circuit
current in the device at high VDD due to partial turn-off of the PMOS transistors. High-to-low level shifters are
only necessary at those power domain interfaces where the domain VDD difference is large enough to cause
significant leakage current increase in the PMOS transistors on the low VDD domain side. Utilization of level
shifters, both low-to-high and high-to-low, also ensures proper calculation of transition times and switching
thresholds across voltage domain boundaries.
With advancements in EDA tools such as DC Ultra and IC Compiler, the insertion and optimization of these
level shifters is an automatic process. Proper placement of the level shifters is even more challenging than the
insertion, since physical constraints need to be considered during placement. For example, if a low-to-high
level shifter is designed with the high VDD implemented as a standard power rail and the low VDD as a contact
pin, the level shifter must be placed in the high-VDD voltage island to correctly align the rails. The level shifters
also need to be placed near the boundaries of the voltage islands, to ensure interface signal integrity. When
voltage islands are far away from each other, it is often useful to define a level shifter region along a border of
a voltage island and create both low- and high-VDD supply power networks in the region for more easily making
the power connections to the level shifters in the region.
Each VDD used in a design usually requires the use of a cell library that has been characterized for a particular
operational voltage to ensure accurate timing calculation during design optimization and signoff a
requirement that constrains the usable supply voltages in multi-VDD designs. However, it is possible to create a
multi-VDD design that uses a voltage level without a matching characterized library by scaling cells delay and
power with respect to the required voltage. Advanced tools such as IC Compiler and PrimeTime are capable
of such voltage-based timing and power scaling to obtain accurate delay, transition time, and power numbers
at the required voltage.

Advanced Dynamic Power Reduction Techniques

Separating parts of a design to be driven by different VDDs requires careful architectural planning to achieve
maximum power savings. This planning is complicated, can sometimes be timeconsuming, and requires a
detailed understanding of the functionality of the design.

Summary
Successfully designing a leading-edge low-power SoC requires advanced EDA tools, knowledge of the best
methodologies for employing them, and as much low-power design expertise and experience as a design
team can get. This white paper provides a look at three key techniques in advanced low-power SoC design to
help designers better understand methodologies and solutions that have proven useful in many SoC projects
supported by Synopsys Professional Services.
While the techniques described here offer starting points toward complete low-power solutions, it is important
to bear in mind that low-power design requires a holistic approach and an end-to-end methodology covering
all design phases, from algorithm and system development to physical design and process development
such as the Eclypse Low Power Solution. EDA tools provide features to implement a variety of techniques for
automatic power reduction in SoCs, and these tools continue to improve as the techniques mature. Pushing
power conservation beyond conventional limits generally demands considerable expertise on the part of
designers and system architects, and the automation afforded by leading edge EDA tools, along with the
assistance of experienced design professionals, can help achieve the best possible low power design.

About Synopsys Professional Services

Synopsys Professional Services provides a broad range of consulting and design services to chip developers
worldwide to help them achieve success in their design programs. These services address all critical phases
of the SoC development process and are tightly aligned with Synopsys EDA tools and IP products to help
customers accelerate their learning curves, develop and deploy advanced methodologies, and achieve
successful tape-outs. We offer customers a variety of engagement models to address their project-specific
and long-term design needs. For more information on Synopsys Professional Services visit our website at
www.synopsys.com/sps.

About the Authors

Kaijin Shi, Principal Consultant, Synopsys Professional Services
Kaijian Shi is Principal Consultant in Synopsys Professional Services Group, specializing in low-power design
methodology and implementation. He holds a Ph.D. degree from University of Kent at Canterbury, UK since
1994 and has published 51 papers in journals and international conferences. He was Chairman of IEEE Dallas
Section in 2006 and Chairman of IEEE Circuits and System Society Dallas Chapter in 2004. He is Workshop
chair of IEEE SoC Conference 2008 and track chair of IEEE SoC conference and DesignCon, and program
committee member of IEEE ISVLSI. Dr. Shi has successfully consulted on more than ten leading-edge
commercial low-power designs.
Neel Desai, Product Marketing Manager, Synopsys Professional Services
Neel Desai is the product marketing manager for Synopsys Professional Services. He has over 14 years of
EDA and semiconductor experience spanning both technical and marketing responsibilities. He spent 8 years
as the Product Marketing Manager for Design Compiler, Synopsys flagship synthesis product. Neel received
his BSEE from University of Bombay, India, his MSEE from Pennsylvania State University and his MBA from
Santa Clara University.

Advanced Dynamic Power Reduction Techniques

David Stringfellow is a Staff Consultant at Synopsys Professional

Services specializing in low-power design, physical synthesis, rail analysis, SI noise analysis, and timing
closure. He has worked on designs including automotive engine controllers, x86 processors, wireless
handhelds, and HD television chipsets. He earned BS and MS degrees in Electrical and Computer
Engineering from Purdue University, holds four U.S. Patents, and was named a General Motors Fellow in 1991.
He has written several papers and articles, is a Synopsys Distinguished Author, and has been with Synopsys
for seven years.

Reference
1

David Flynn, Michael Keating, Robert Aitken, Alan Gibbons and Kaijian Shi , Low Power Methodology
Manual for System-on-Chip Design, Springer, 2007

Kiat-Seng Yeo and Kaushik Roy, Low-voltage, Low-power VLSI Subsystems, McGraw-Hill, 2005

Enrico Macii, Ultra low-power electronics and design, Kluwer Academic Pub. 2004

3
4

Jan M. Rabaey and Massound Pedram, Low power design methodologies, Kluwer Academic Pub. 2002

Massound Pedram and Jan M. Rabaey, Power aware design methodologies, Kluwer Academic Pub. 2002

Kaushik Roy and Sharat C. Prasad, Low-power CMOS VLSI Circuit Design, John Wiley &sons, 2000

Gary K. Yeap, Practical low power digital VLSI design, Kluwer Academic Pub. 1998

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