Electronic Circuits Laboratory

Lab #1: CE Amplifier Design with Passive

Load

Joe McMichael
Professor Takach
ECE 328: Electronic Circuits Laboratory
January 20th, 2008

Honor Code:

I have neither given or received, nor have I tolerated others’ use of

unauthorized aid.
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 19th, 2008
Page 2

ECEGR 328 -
Lab #1: CE Amplifier Design with
Passive Load
By: Joe McMichael
(Partners: Dean Hoaglan and Anthony Robbins)

Objective:

The common emitter amplifier (CE) forms the backbone of much of

electronic circuit design. We will explore the traditional CE amplifier with
passive (resistive) load in this session. In addition, we will learn to
measure voltage gain and input impedance for an amplifier.

Background Information:

The common emitter amplifier is used when voltage gain is required. A CE

amplifier can have reasonably high input impedance at the expense of a
lower voltage gain.

If a high voltage gain is desired, the most effective technique is to cascade

two CE stages together or to employ a DC current source as an “active
load” in place of the standard collector resistor-biasing scheme.

The DC design and the AC analysis are effectively decoupled, thereby

making it quite easy to do the design and analysis.

Figure 1: CE Amplifier Design with Passive Load

 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 19th, 2008
Page 3

Procedure:

1) Given Specifications:
Q2N2222 Transistor
Vcc = 10-15 V
RL = 2-10 kΩ
RE >= 100 Ω
ß = 150
VBE = 0.7 V

2) Designer Selected Specifications:

AV = 4
Vcc = 15 V
RL = 10 kΩ
Ic = 1 mA
c = 1µF

Figure 2: DC Analysis with Capacitors Open-Circuited

0

15 V

15 V

R1 RC

Q1

Q2N2222
R2

RE

3) Calculate RC:
VC 2V
RC = = = 2kΩ
I C 1mA

4) Calculate IB:
IC 1mA
IB = = = 6.67 µA
β 150
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 19th, 2008
Page 4

5) Find IE:
I E = I C + I B = 1mA +6.67 µA = 1.00667 mA

6) From AV, find RE:

VOUT RC R L
AV = =
V IN RE

2kΩ 10kΩ
AV = 4 =
RE

RE = 416Ω ⇒ 470Ω

7) Calculate VE:
VE = (470Ω)(1.00667mA) = 0.473V

Figure 3: Thevenin Equivalent Circuit

0

15 V

0 15 V

RC
V2
Vth

Q1
R3

Rth
Q2N2222

RE

8) Find VB from VE and VBE:

VB = VE + VBE = 0.473 + 0.7V = 1.173V

9) Let bias current IBIAS be 10 times IB:

I BIAS = 10 I B = 0.0667 mA
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 19th, 2008
Page 5

10) Calculate R2:

V 1.173V
R2 = B = = 17.46kΩ ⇒ 18kΩ
I BIAS 0.0667 mA

11) Calculate R1:

V − VB 15 − 1.173V
R1 = CC = = 206.4kΩ ⇒ 220kΩ
I BIAS 0.0667 mA

12) Capacitor Selected: 1µF

13) Capacitor Impedance at 10 kHz:

1 1
XC = = = 16Ω
2πfc (2π )(10kHz )(1µF )
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 19th, 2008
Page 6

Figure 4: DC and AC Load Lines

DC and AC Load Lines of CE Amplifier with Passive Load

7
Imax =0, 6.8

0, 6.07 6 AC Load Line

y = -0.468x + 6.8
5
DC Load Line
y = -0.4047x + 6.07
Ic (mA)

Quiescent Point
3
Vceq = 11.53 V
Ic = 1.4 mA
2

11.53, 1.4
1

Vcc =15, 0
0
0 2 4 6 8 10 12 14 16
Vmax =14.53, 0
-1

Vce (V)
14) Calculate AC & DC Load Line Intercepts:
VCC 15
= = 6.07 mA
RC + R E 2kΩ + 470Ω

VMAX = VCMAX − V E = 15 − 0.47V = 14.53V

V MAX 14.53V
I MAX = = = 6.8mA
( RC R L + RE ) (2kΩ 10kΩ + 470Ω)

15) Calculate Quiescent Point:

6.07 mA 6.8mA
−( )q + 6.07 mA = −( )q + 6.8mA
15V 14.53V

q = 11.53V

6.07 mA 6.8mA
I C = −( )11.53 + 6.07 mA = −( )11.53 + 6.8mA
15V 14.53V

I C = 1.4mA

Figure 5: CE Amplifier Design with Component Values

15 V

15 V

R1 RC
220k 2k

Q1
Cin Cout

1u
V3 Q2N2222
R2
1u
1n RL
18k RE
10k
470

0
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 8

Figure 6: BJT Terminals

16) Perform a transient analysis (time domain) of the circuit with

measured values of R’s and C’s. Set the frequency of the input
signal to 10 kHz and check the output signal to be sure BJT is not
saturated.

Figure 7: PSpice Bias Point Simulation of CE Amplifier Design

Target Vc=13 V
Target Vb=1.17 V
Target Ve=0.47 V
Target Ic = 1 mA
VCC

VCC V3
DC = 15
AC = 0
TRAN = 0

R5
R3 2k
V

220k I
C2
I
Q1
C1 15.00V
1u

1u
Q2N2222
V2 R7
VOFF = 0
R4 R6 1k
VAMPL = 0
FREQ = 1000 18k 470 13.27V
0V
0V 1.048V

0 0 0 0
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 9

Figure 8: PSpice CE Amplifier Bias Information

**** BJT MODEL PARAMETERS****************************************

Q2N2222
NPN
LEVEL 1
IS 14.340000E-15
BF 255.9
NF 1
VAF 74.03
IKF .2847
ISE 14.340000E-15
NE 1.307
BR 6.092
NR 1
ISS 0
RB 10
RE 0
RC 1
CJE 22.010000E-12
VJE .75
MJE .377
CJC 7.306000E-12
VJC .75
MJC .3416
XCJC 1
CJS 0
VJS .75
TF 411.100000E-12
XTF 3
VTF 1.7
ITF .6
TR 46.910000E-09
XTB 1.5
KF 0
AF 1
CN 2.42
D .87
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 10

Figure 9: PSpice Simulation of Vo and Vi at 10kHz

800mV
(122.222u,196.743m) (174.564u,651.155m)

400mV

0V

-400mV

-800mV
0s 100us 200us 300us 400us 500us
V(C2:2) V(V2:+)
Time

17) Perform an AC sweep in PSpice.

Figure 10: PSpice AC Sweep Vo/Vi

4.0

3.0

2.0

1.0

0
100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz
V(C2:2)/ V(C1:1)
Frequency
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 11

18) Find AC voltage gain.

Vout = 651.155 mV

Vin = 196.743 mV

Av = 651.155 mV/ 196.743 mV = 3.31 V/V

Figure 11: PSpice AC Sweep 20log(Vo/Vi). Note that bandwidth

is 41 kHz.
20

(3.4754K,10.402)
(19.058,7.3786) (40.657M,7.3786)

-0

-20

-40

-60

-80
100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz
20*LOG10(V(C2:2)/ V(C1:1))
Frequency

19) Find amplifier bandwidth.

fL = 19.06 Hz

fH = 40.657 MHz

Bandwidth = 40.657 MHz – 19.06 Hz = 40.7 MHz

 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 12

Figure 12: PSpice AC Sweep Input impedance versus frequency

15K

10K

5K

0
100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz
V(C1:2)/I(C1:1)
Frequency

20) Find input impedance.

Input Impedance = 14.07 kΩ

21) Use the curve tracer to print out the output characteristic (Ic versus
VCE) curves for the 2N2222 npn BJT.

I CQ 1.4mA
β DC = = = 210
I BQ 6.67 µA

∆I CQ 900µA
β AC = = = 180
∆I BQ 5µA

20V
rO = = 100kΩ
0.2mA

VA = −80V
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 13

22) Build the circuit using nominal values for resistors and capacitors.
Use a DMM to verify that indeed the transistor is operating at the
intended operating point by measuring the DC base-emitter and
collector-emitter voltages.

Figure 14: As-built schematic with measured values

VCC

VCC
V3
DC = 15
AC = 0
TRAN = 0

0
RC
R1 1.97k

V
202k
C2
Q1
V
C1
1.022u

.982u
Q2N2222
V4 RL
0.2Vac R2 RE 9.89k
0Vdc 17.87k 466

0 0 0 0
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 14

Measured Values for CE Amplifier Circuit:

VBEQ = 0.6163 V

VCEQ = 12.29 V

VRC 1.8V
I CQ = = = 0.914mA
RC 1.97kΩ

VB = 1.04 V

VR1 13.95V
I R1 = = = 69.1µA
R1 202kΩ

VB 1.04V
I R2 = = = 58.2µA
R2 17.87kΩ

IBQ = IR1 – IR2 = 69.1 µA – 58.2 µA = 10.9 µA

VRE 0.429V
I EQ = = = 0.921mA
RE 466Ω

nVT (1)25 *10 −3

rπ = = = 2.3kΩ
I BQ 10.9µA

23) Establish an input voltage ac signal at 10 kHz. Determine if this

frequency is indeed in the mid band range of frequencies (where the
gain remains constant and the output is 180 out of phase with the
input).
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 15

Figure 15: Oscilloscope Plot of Vin and Vout at 10 kHz

In this display the gain is constant, and the output voltage is clearly 180
degrees out of phase with the input voltage. 10 kHz is definitely in the
mid-band region for this amplifier.

24) With the input set at a frequency in the mid-band range, measure
the small signal ac voltage gain and compare it with the predicted
voltage gain.

Vout = 650 mV

Vin = 194 mV

Av = 650 mV/ 194 mV = 3.35 V/V

Our measured voltage gain of 3.35 V/V is fairly close to the

ideal circuit gain of 4 V/V and extremely close to the
simulated gain of 3.31 V/V.
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 16

25) Explore the issues of non-linear distortion and clipping by changing

the location of the Q point.

Figure 16: Oscilloscope Plot of Vin and Vout at 10 kHz with

Clipping

26) Identify the exact 3 dB-frequency points (low and high), which in
turn indicate the bandwidth of the amplifier.

Rather than using the 1-2-5 method, we used the second

method in Part B of the Appendix to calculate the 3 dB
points.

Gain at Mid-Band Frequency:

VOUT
b = 20 log = 20 log(3.35)
VIN
b = 10dB
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 17

VOUT at fL and fH:

b −3 10.5 −3

VOUT = VIN *10 = 400mV *10

20 20

VOUT = 0.948mV for fL and fH

Adjust frequency of function generator until VOUT is

approximately close to the calculated values. These are
the 3 dB frequencies:

fL = 20 Hz

fH = 430 kHz

Bandwidth = 430 kHz – 20 Hz = 429.98 kHz

27) Next, measure the input impedance of your amplifier. Set the
frequency of the input signal at the point where the simulated result
for the input impedance is taken.

Add an external and known resistor RK (close to the

expected RIN) in series between the ac voltage source
and the input coupling capacitor.

nVT (1)25 *10 −3

re = = = 27.1Ω
IE 0.921mA

RINEXPECTED = RBB ((β + 1)(re + RE )) =(202kΩ 17.87kΩ) ((180 + 1)(27.1 + 466))

RINEXPECTED = 13.9kΩ , so RK = 14.9kΩ

 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 18

Set the frequency generator to 10 kHz. Employing

the voltage divider formula, the input impedance Rin
can be expressed in terms of the known external
resistance Rk:

Figure 17: Add RK to measure input impedance

Vi RIN
=
Vg RK + RIN

247mV RIN
=
500mV 14.9kΩ + RIN

Therefore, RIN = 14.55 kΩ

 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 19

Comparisons:

Table 1: Comparisons of Design, Simulated, and Measured

Values

Design Simulated Measured

Av (Vo/Vi) 4 V/V 3.32 V/V 3.35 V/V
Frequency High - 41 MHz 430 kHz
Frequency Low - 19 Hz 20 Hz
Rin 13.9kΩ 14 kΩ 14.55 kΩ
Ic @ Q 1 mA 1.019 mA 0.914 mA
Vce @ Q 13 V 12.51 V 12.29 V
Rpi - - 2.3 kΩ
ßdc 150 - 210
ßac 150 - 180
Ro - - 100k
Va - -74 -80V

Conclusion:

In this lab, we explored the traditional CE amplifier with a passive resistive

load. Our group decided to aim for an ac voltage gain of 4 V/V, a source voltage
of 15 V, a collector current of 1 mA, and a load resistance of 10 kΩ. After
calculating the resistor and capacitor values, we were able to draw ideal DC and
AC “load lines” on a graph of collector current versus collector-emitter voltage.
The point where the curves meet is called the quiescent point, which was at 11.53
V and 1.4 mA for us.

Next, we learned to simulate our design in PSpice, verifying the voltage

gain and other characteristics. In the simulation, our voltage gain was 3.31 V/V,
slightly below the ideal of 4.00 V/V. We also ran an AC Sweep to determine the
bandwidth of the amplifier. In this case, PSpice claimed that the bandwidth was
nearly 41 MHz, which seemed quite high. The simulated output resistance was
approximately 14 kΩ.
 Joe McMichael
ECEGR 328: Electronic Circuits Lab
January 20th, 2008
Page 20

Finally, we constructed the CE amplifier circuit. In reality, the voltage

gain was 3.35 V/V, lower than the ideal of 4.00 V/V. The bandwidth of our
amplifier was approximately 430 kHz. We also used an external resistance RK as
a voltage divider to determine the true input resistance of our amplifier, which
was 14.55 kΩ.

The CE amplifier seems to be fairly reliable and simple to build. This

would probably explain why it is so popular in electronic circuit design. The main
limitation of the CE amplifier we designed in lab is its poor high frequency
operation. With a bandwidth of 430 kHz, the amplifier would be precluded from
many designs, including FM radios.