ELECTRICAL & ELECTRONIC ENGINEERING PROGRAM

FACULTY OF ENGINEERING

UNIVERSITI MALAYSIA SABAH

KE 26604
COMPUTER ARCHITECTURE AND
MICROPROCESSING (2014/15)
Computer Architecture &
Microprocessor
Tutorial 1

PREPARED BY:
Ramanan A/L Thangasalvam (BK13160570)
PREPARED FOR:
Lecturer: Assoc. Prof. Engr. Dr Ismail Saad
Lab Coordinator: Mr Chan Bun Seng

1) Stored program concept

Storage of instructions in computer memory to enable it to perform a variety of
tasks in sequence or intermittently. These stored instruction are able to be
fetched from the designated memory location(s) and be executed to give the
correct control signal so as to perform the desired task. A program is basically a
sequence of steps, where for each step an arithmetic or logical operation is done
and for each operation a different set of control signals are needed and for each
operation a unique code such as mov, add, jmp and etc., is provided. A
hardware segment such as a monitor, speaker etc., accepts the code and issues
the control signal.
2) Function of the following for the operation of stored program concept:
(i) Main memory - Main memory is for storing data so the CPU/MPU and other
direct
memory access devices can call up to fetch or store data for
processing
(ii) CPU - active part of the computer, which does all the work of data
manipulation and
decision making
(iii) Input/Output Module - transferring information between internal storage
and external
I/O devices and peripherals

Sketch the top level view of computer main components:

3)
Fetch instruction:

In the first step, the processor fetches the instruction from the memory. The
instruction is transferred from memory to instruction register.
In the following figure, the processor is ready to fetch instruction. The instruction
pointer contains the address 0100 contains the instruction MOV AX, 0.
The memory places the instruction on the data bus. The processor then copies
the instruction from the data bus to the instruction register.

Execute instruction:

In the last phase, the processor execute the instruction, it stores 0 in register AX.
In above figure, the processor execute the instruction MOV AX, 0. Finally it
adjusts the instruction pointer to point to next instruction to be executed stored
at address 0102.

In between the fetch and execute instruction there is an intermediate instruction

known as the decode instruction which is as follows:
Decode instruction:

In this step, the instruction is decoded by the processor. The processor gets any
operand if required by the instruction. For example, the instruction MOV AX, 0.
Stores the value 0 in Ax register. The processor will fetch the constant value 0
from the next location in memory before executing the instruction.
In the above figure, the processor transfers the instruction from instruction
register to the decode unit. The instruction tells the computer to store 0 into AX
register. The decode unit now has all the details of how to do this.

4)
Instruction Cycle State diagram without interrupts:

The instruction cycle has three code segments that do not perform I/O. WRITE
calls the OS to perform an I/O Write. A code sequence then prepares for the I/O
transfer (check device status, copy data to buffer, etc.). The OS issues I/O
command and OS then has to wait and poll device status until I/O completes. An
example of post I/O processing is set status flag. The users program is
suspended until I/O complete
Instruction Cycle State diagram with interrupts:

The figure above shows processing with interrupts. The WRITE call again
transfers control to the OS. After write preparation, control returns to user
program. The I/O proceeds concurrently with user program. When I/O completes,
device issues an interrupt request. OS interrupts user program and executes post
I/O code.

The instruction cycle with interrupts is more effective compared to that without interrupts.
The reason interrupts are used are for the following reasons. The interrupt cycle is added to
the instruction cycle. Processor checks for interrupt which is then indicated by an interrupt
signal if present. If there is no interrupt, the next instruction is fetched. If interrupt is pending
the execution of current the program will be suspended. The interrupt cycle process occurs as
such, the context is saved, PC is set to start address of interrupt handler routine, process
interrupt occurs and restores context and continue interrupted program.

5) (i) Multiple interrupt handling by Sequential process

Processor will ignore further interrupts whilst processing one

interrupt

Interrupts remain pending and are checked after first interrupt has
been processed

Interrupts handled in sequence as they occur

(ii) Multiple interrupt handling by Nested process

Low priority interrupts can be interrupted by higher priority

interrupts

When higher priority interrupt has been processed, processor

returns to previous interrupt

6) Some of the elements used in processor bus designing are as follows:

- Industry Standard Architecture (ISA)
standard bus (computer interconnection) architecture that is associated with the
IBM AT motherboard. It allows 16 bits at a time to flow between the motherboard
circuitry and an expansion slot card and its associated device(s)
- Enhanced Industry Standard Architecture (EISA)
Extended Industry Standard Architecture (EISA) is a bus architecture that
extends the Industry Standard Architecture (ISA) from 16 bits to 32 bits. EISA
extended the advanced technology (AT) bus architecture and facilitated bus
sharing between multiple central processing units (CPU).
- Video Electronic Standard Association (VESA)
VESA (VL bus) is a 33MHz extension of the ISA bus used of high-speed data
transfer applications. It contains 32-bit address and data bus and is mainly used
for video and disk interfaces. Requires a third connector (VESA connector) to be
added behind the standard 16-bit ISA connector.

- Peripheral Components Interconnect (PCI)

PCI is the most common bus found in computers today due to plug-and-play
characteristics and ability to function with 64-bit data bus. A PCI interface
contains a series of registers, located in a small memory device, that contain
information about the board. The information in this registers allow the computer
to automatically configure the PCI card (Plug-and-Play PnP feature). The
microprocessor connects to the PCI bus through an integrated circuit called a PCI
Bridge thus making the PCI bus independent of processor type and architecture.
PCI functions with either a 32-bit or 64-bit address and data bus. The address
and data buses are multiplexed to reduce the size of the edge connector. 32-bit
and 64-bit cards. Newest versions run at 66 MHz (twice the older 33 MHz
version).

7) Gordon Moore, the co-founder on Intel Corporation in 1975 stated a law knows
as the Moores Law which states that the number of transistor per square inch on
an integrated chip is to double every 18 months since its invention. This law has
become the heart of the development of the computer and processor and is
practiced in all semiconductor industries. In today's chips, a stretch of silicon

connects the source to the drain. Silicon is a type of material known as a

"semiconductor" because, depending on conditions, it'll either act as a conductor
that transmits electrons or as an insulator that blocks them. Applying a little
electrical voltage to the transistor's gate controls whether that electron current
flows. To keep up with Moore's Law, engineers must keep shrinking the size of
transistors. Intel, the leader in the race, currently uses a manufacturing process
with 22-nanometer features. That's 22 billionths of a meter, or roughly a 4,000th
the width of a human hair. For contrast, Intel's first chip, the 4004 from 1971,
was built with a 10-micron (10,000-nanometer) process. That's about a tenth the
width of a human hair. The smaller the size of the transistor, the more number of
transistors that can be placed within the microprocessor, thus, the performance
of the processor as well as computers increases as more transistors enable faster
clock cycles, thus, faster processing of data. The size of the computers can also
greatly decrease while maintaining or increasing its functionality.

8) Three types of computer buses:

(i) Address Bus identifies the source or destination of data. It is
unidirectional. The larger the address bus width, the more space available for
data storage. Example, 32-bits address bus provides approximately 4GB memory
space (2^32).
(ii) Data Bus carries data from source to destination and vice versa making
it bidirectional. The larger the data bus width, more bytes of data is able to be
transferred at a single time, thus, processor performance increases.
(iii) Control Bus used to send or receive control signals between CPU and
other peripheral devices making it bidirectional. Some of the control signals are
the memory read/write signal, interrupt request signal and clock signals.

9)
(a) Maximum directly addressable memory capacity in bytes = 32 bit/8 bit
= 4 bytes

(b) (i) a 32-bit local address bus allows more space for data storage 2^32 4GB
space and a 16-bit local data bus allows a maximum of 4 byte of data to be
written to/read off from the memory at a time.
(ii) a 16-bit local address bus allows very less for data storage 2^16 64kB
space and a 16-bit local data bus allows a maximum of 4 byte of data to be
written to/read off from the memory at a time.
(c) The Program Counter (PC) requires 24 bits and the Instruction Register (IR)
required 32 bits.

10) The optimal code for the four machines for the given equation X=(A+B*C)/
(D-E*F) and instructions is as follows:
zero-address

one-address

two-address

three-address

PUSH A

LOAD E

MOV R0, E

MUL R0,E,F

PUSH B

MUL F

MUL R0,F

SUB R0,D,R0

PUSH C

STORE T

MOV R1,D

MUL R1,D,R0

11) (i) Flat and segmented addressing modes differences

Flat mode
Simple mapping between addresses

Segmented mode
The mapping works within a segment

and

memory

but not between segments. A segment

location can be selected from a single

is a unit of contiguous address space.

continuous array by a single integer

Segment sizes may range from one

numbers

where

any

offset

byte up to a maximum of 2^(32)

bytes (4 gigabytes)

Not suitable for general computing or

Provides multi-mode operation and

multitasking

rarely

enhanced

operations

with

additional

unless
memory

hardware/software
Used in the Linux

operates

in

the

compatible

segmented mode
Used in the X86 models of intel

A pointer into this flat address space is

a 32-bit ordinal number that may

A complete pointer in this address

range from 0 to 2^(32) -1

space consists of two parts which is a

segment selector, which is a 16-bit
field that identifies a segment and the
other part an offset, which is a 32-bit
ordinal that addresses to the byte
level within a segment

Relocation
modules

of
in

this

separately-compiled
space

must

Separately compiled modules can be

be

relocated at run time by changing the

performed by systems software (e.g.,

base address of their segments. The

linkers, locators, binders, loaders).

size

of

segment

is

variable;

therefore, a segment can be exactly

the size of the module it contains.

(ii) The 386 microprocessor uses the segmented memory addressing mode
and has six
segment registers, code and stack both 64kb in size and (4x64kb) or
256kb for data.
Only these six segments can be addressed at any given time. Thus, the
total memory
that can be addressed at any given time is:
64kb + 64kb + 256kb = 384kb.
(iii) (a) for, 23FB:FAB3H

23FB0H + FAB3H = 33A63H

(b) for, 1234:FFB3H
12340H + FFB3H = 222F3H
(c) for, 23FB:89FAH
23FB0H + 89FAH = 2C9AAH

12) (i) Data Register general purpose register used as temporary data store
during execution
- examples: AL and AH registers = 8-bits
AX register = 16-bits
EAX register = 32-bits
(ii) Index and pointer register general purpose register used to hold the
offset of the
address of the data in memory
- examples: BP Base pointer (16-bits)
DI Destination Index (16-bits)
SP Stack pointer (16-bits)

(iii) Segment register each holds the base memory address of 64k memory
segment
- example: DS Data segment (16-bit)
CS Code segment (16-bit)
SS Stack segment (16-bit)
(iv) Flags register show the status of result stored in accumulator after
execution of an

instruction. First nine bits used in real mode, where first six
bits are
the status flags that states the change as result of
executing a certain
instruction and the following three bits are the control flags
that are
responsible for the control operation of the 386
microprocessor. Each
flag is 1-bit in size.
- example: CF carry flag
PF parity flag
IF interrupt enable flag