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Introduction:
is the most widely used serial
asynchronous communication protocol.
Typically uart is connected between a
processor and a peripheral.
UART
TRANSMITTER:
W
r
i
t
e
M
e
m
Baud
clock
R
e
a
d
TX
Contro
l
Shift
State
Reg
Parity
generato
o Parity generator.
o Baud clock generator.
o Data frame.
TX FIFO:
Process
W
r
i
t
e
M
e
m
Process
R
e
a
d
Tx_con
trol
state
Fifo_rd
_data[
3. Processor_valid:
7. FIFO_Empty:
SHIFT-REGISTER:
Tx_contr
ol state
machine
Shif
t
[7:0]
3. Shift_reg_out:
serially
to the peripheral.
Parity generator:
Tx_contro
Parity
genera
Data
Registe
r set
Parity
enable
Stick
parity
Even
parity
Parity bit
~^(data)
^(data)
Baud
clock
Data frame:
Data
frame
TX control
state
UART frame:
Star
t bit
D0 D1
D2
D3
D4
D5
D6
D7
Parity Stop
bit
bit1
Stop
bit2
5-bit
1-bit
6-bit
1.5 bits
7-bit/8-bit
2-bits
1.
TRANSMITTER IDLE
4h0000
2.
SEND BREAK
4h0001
3.
Transmit error
4h0010
4.
Single_mode_transfer
4h0011
5.
Multi_mode_transfer
4h0100
6.
FIFO_read
4h0101
7.
Send start
4h0110
8.
Send_data_bits
4h0111
9.
Send_parity_bit
4h1000
10
.
Send_stop_bit1
4h1001
11
.
Send_stop_bit2
4h1010
Baud clk
Shift
TX
Contr
ol
RD control
logic of
FIFO_re
State
Data
Fifo_rd
Machi
Parity
STATE DIAGRAM
H
Transmitter IDLE
Send break
Send_parity_bit
Single
transfer mode
DMA_signalli
ng mode &
processor
valid & !
Send_stop_bit1
Transmit Error
!
DMA_signalli
ng mode &
FIFO_read
FIFO_data
Send start
Send data