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55:131

Introduction to VLSI Design
Flash and DRAM
Adapted from Weste and Harris notes except as noted
Flash and DRAM sections adapted from “Digital
Integrated Circuits”, copyright 2003 Prentice Hall/
Pearson

Outline   Memory Arrays   Flash   DRAM 55:131 Introduction to VLSI Design 2 .

Memory Arrays 55:131 Introduction to VLSI Design 3 .

fold by 2k into fewer rows of more columns   Good regularity – easy to design   Very high density if good cells are used   55:131 Introduction to VLSI Design 4 .Array Architecture 2n words of 2m bits each   If n >> m.

Non-Volatile Memories   Floating-gate transistor Floating gate Gate Source D Drain G tox tox n+ Substrate p n+_ Device cross-section 55:131 Introduction to VLSI Design S Schematic symbol 5 .

Floating-Gate Transistor Programming FN Tunneling Remove eNegative Vt “1” FN Tunneling Add ePositive Vt “0” 55:131 Introduction to VLSI Design 6 .

NAND Flash Memory Word line (poly) Unit Cell Source line (Diff. Layer) Courtesy Toshiba 55:131 Introduction to VLSI Design 7 .

NAND Flash Memory Select transistor Word lines Active area STI Bit line contact Source line contact 55:131 Introduction to VLSI Design Courtesy Toshiba 8 .

Read-Write Memories (RAM)   Static (SRAM) Data stored as long as supply is applied   Large (6 transistors/cell)   Fast   Differential     Dynamic (DRAM) Periodic refresh required   Small (1-3 transistors/cell)   Slower   Single Ended   55:131 Introduction to VLSI Design 9 .

V T 55:131 Introduction to VLSI Design ΔV 10 .3-Transistor DRAM Cell No constraints on device ratios   Reads are non-destructive   Value stored at node X when writing a “1” = Vwwl-Vtn   BL 1 BL 2 WWL WWL RWL M3 M1 CS X M2 RWL V DD V T X BL 1 V DD BL 2 V DD .

3T-DRAM — Layout BL2 RWL BL1 GND M3 M2 WWL M1 55:131 Introduction to VLSI Design 11 .

1-Transistor DRAM Cell Write: Cs is charged or discharged by asserting WL and BL   Read: Charge redistribution takes place between bit line and storage capacitance   Voltage swing is small. typically around 250 mV   55:131 Introduction to VLSI Design 12 .

DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line. read and refresh operations are necessary for correct operation. a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD   55:131 Introduction to VLSI Design 13 .   Unlike 3T cell.   DRAM memory cells are single ended in contrast to SRAM cells.   When writing a “1” into a DRAM cell. due to charge redistribution read-out.   The read-out of the 1T DRAM cell is destructive. 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

Sense Amp Operation V BL V (1) V PRE ΔV (1) V (0) Sense amp activated Word line activated 55:131 Introduction to VLSI Design t 14 .

1-T DRAM Cell Capacitor M1 word line Metal word line SiO2 Poly n+ Field Oxide n+ Poly Inversion layer induced by plate bias Diffused bit line Cross-section Polysilicon Polysilicon plate gate Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area 55:131 Introduction to VLSI Design 15 .

Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell Stacked-capacitor Cell 55:131 Introduction to VLSI Design 16 .

DRAM Timing 55:131 Introduction to VLSI Design 17 .

Redundancy Row Address Redundant rows : Redundant columns Fuse Bank Memory Array Row Decoder Column Decoder 55:131 Introduction to VLSI Design Column Address 18 .