Powerful things you can do with

Template-Based Power Network Synthesis combined with

Basic Polygon Operations in IC Compiler

Johnie Au

Cypress Semiconductor
San Jose, USA
www.cypress.com

ABSTRACT
Template-based power network synthesis provides the means & flexibility to quickly tune-up the
power grid by turning some parametric knobs of the templates to adapt to on-going placement
and routing changes during floorplan exploration phase. It is extremely crucial for Low Power
System-On-a-Chip (SOC) to have precise power grid design to minimize multivoltage supply
variations for optimum performance due to on chip voltage variations. By specifying coordinates
of desired rectilinear power plan regions for the template, different favors of power network can
be built accordingly to the power requirement. As power network is mostly driven by placement
of I/O, macros and standard cells, clock tree and signal congestion, rectilinear power plan regions coordinates can be calculated from the bounding box of any cells or features on the chip
with respect to the core area. By using the basic polygon operating functions in IC Compiler,
complex power plan regions serving various purposes can then be derived quickly and easily
without too much effort. The paper will attempt to discuss a few examples and illustrate their
applications.

Table of Contents
1.

Introduction ........................................................................................................................... 3

2.

Low Power Integrated Circuits demand adaptive power nework design ............................ 3

3.

Template-based Power Netowrk Synthesis with polygon operations................................... 5

4.

Flow Advantages and Results ............................................................................................. 13

5.

Conclusions ......................................................................................................................... 13

6.

References ........................................................................................................................... 13

Table of Figures
Figure 1. Simple Design with Single Power Domain ..................................................................... 3
Figure 2. Multiple Power domain and Voltage Area. ..................................................................... 4
Figure 3. Power swtich array in Shutdown Domains .................................................................... 4
Figure 4. Dynamic IRdrop with package RLC .............................................................................. 5
Figure 5. Template-based PNS Flow Chart .................................................................................... 5
Figure 6. Simple Power Plan Region .............................................................................................. 6
Figure 7. Complex Power Plan Regions ......................................................................................... 6
Figure 8. Using "compute_polygon " inline with "create_power_plan_regions" ........................... 7
Figure 9. Template for Top Metal Layer N, N-1 ............................................................................ 8
Figure 10. 2 top layers (N) versus Single top layer (N) with jumpers (N-1) ................................. 8
Figure 11. Application for XOR and RESIZE ............................................................................... 9
Figure 12. Overlapping irregular shaped macros ......................................................................... 10
Figure 13. Resized then OR before power plan region creation ................................................... 10
Figure 14. Column of MTCMOS in a power domain ................................................................... 11
Figure 15. create_power_plan_regions ... get_cells *mtcmos* .................................................... 11
Figure 16. MTCMOS power strapping ........................................................................................ 12
Figure 17. Centroid of a polygon ................................................................................................. 12

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1. Introduction
This paper reviews the usage of Template-based power network synthesis and explore the possible application with the help of basic polygon operations supported in ICC. The Templatebased power network synthesis flow was first introduced in 2010 SNUG. As described in the
paper and application notes, this flow helps to automate multivoltage power network design for
integrated circuits. Power plan region was introduced as yet another user defined region to
bound dedicated power network based on voltage area, polygon list, group of macros or the core.
The flow works perfectly with simple rectilinear shaped features and polygons but sometimes
stumbles on multivoltage design with irregular shaped or overlapping features. Luckily, the flow
can be enhanced as the irregular shaped features can be pre-processed and reshaped all within IC
Compiler using the supported basic polygon operations.

2. Low Power Integrated Circuits demand adaptive power network design

Power Grid Design is crucial in todays low power design. The design usually needs to support a
set of power supplies feeding into different power domain and voltage areas alongside with
power management cells. Traditionally, a decent amount of time was spent in power grid design
during floor planning stage. Simple designs power grid as shown in Fig.1 can easily be redesigned without much effort. But complex low power designs power grid, with numerous power
domain and voltage areas as shown in Fig.2, is extremely time consuming to explore new power
grid as the grid is not programmable nor parameterized.

Figure 1. Simple Design with Single Power Domain

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Figure 2. Multiple Power domain and Voltage Area.

Advanced low power design may also have on-chip power switches of different type (Fig.3) to
control power supply in the shutdown power domain to conserve power when the block is disabled. The number of power switches must be sufficient to support functional as well as scan
switching current requirement.

Figure 3. Power switch array in Shutdown Domains

Low power SoC feature sets are evolving quickly as the mobile market and touch screen market
are expanding. As complex power grid plays an important role in floor planning, being able to
rapidly generate a prototype power network is advantageous in speeding up the entire place and
route process. Traditional power design approach is to layout a general power grid manually and
modify and enhance as needed, mostly due to design change, voltage area change, ir drop feedback and others. Nevertheless nowadays low power designs power grid interact with cell
placement quite often especially with power management cells like power switches, level shifters
and isolation cells. Any change in power management cells triggers power grid ECO. Worst of
all, static and dynamic voltage drop final feedback also come at the end close to tapeout. Any IR

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drop surprises (Fig.4) which requires power grid enhancement would definitely stall tapeout.

Figure 4. Dynamic IRdrop with package RLC

Only if we can better predict the low power architecture, the cell placement, the potential buffers
or repeaters needed, the power consumption profiles, that we can design and build a bullet proof
power grid sitting on the shelf waiting for tapeout.

3. Template-based Power Network Synthesis with polygon operations

Template-based Power Network Synthesis was introduced in last years SNUG which shows a
path to rapid power network prototyping. As shown in last years SNUG presentation, Template-based power network synthesis is based on predefined templates which describe the dimensions and characteristics of the physical implementation of the power network per layer for each
power net. Figure 5. Shows the Flow recommended by Synopsys (see references)

Figure 5. Template-based PNS Flow Chart

As shown in (Fig.5), the template-based flow allows user to create new regions, so call power
plan regions, on the floorplan. These regions are solely for power grid creation guided by the
power grid strategies and templates for creating complex multivoltage power grid. In other
words, power plan regions are physical regions which are defined to bound the implementation
of the selected template. With a set of predefined templates, of which dictates the metal strapSNUG 2012

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ping specifications, the power plan strategies then select the appropriate templates for each
power plan region for specific power net and further re-shaping of the region. Power plan regions
are simply rectilinear physical regions. Simple power plan regions could be just a group of voltage areas, including or excluding a selected set of hard macros like I/O or memories (see Fig. 6).

Figure 6. Simple Power

Plan Region

For multvoltage design, the power plan regions would look a little busy (see Fig.7).

Figure 7. Complex Power Plan Regions

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As shown in Fig.7, complex power plans consist of many groups of irregular shapes of hard macros; disjoint voltage areas, always-on regions all over the chip. One example to automate the
generation of all necessary power_plan_regions, without stretching them manually, is to use a
foreach loop on the voltage_areas collection. Nevertheless, voltage areas often do have the optimal shape for laying down power ring and power grid as its purpose is for cell placement only.
To make use of the floorplan features and create usable power plan regions, the existing features
polygon coordinates must be re-shaped for the automation to be usable. The create_power_plan_regions"command does have options to remove notch and jog and expand but
lagging options to merge polygons and does any AND, OR, NOT, XOR functions. Nevertheless,
as described in reference.2, IC Compiler(s) can perform the basic polygon operations. And to
streamline the polygon merging, for example, before running the create_power_plan command,
once can run the polygon operation inline with the command as shown in Fig.8.

Figure 8. Using "compute_polygon " inline with "create_power_plan_regions"

As power plan regions can be derived from any existing floorplanning features. With the help of
basic polygon operations supported by IC Compiler , complex power plan regions can then be
derived automatically and react instantly to any floorplan/macro placement updates along the
entire design cycle. Basic Polygon Operation Commands are convert_to_polygon, compute_polygons, convert_from_polygon, get_polygon_area and resize_polygon.

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Another application of pre-processing the polygons before feeding into create_power_plan_regions is as follows. Generating top level power grid with top metal layer N
and Layer N-1 is straight forward using the template for the 2 layers as shown in Fig.9.

Figure 9. Template for Top Metal Layer N, N-1

However, to generate a top level power grid with only the Layer Metal N, allowing only jumper
in Layer Metal N-1 is tricky.

Figure 10. 2 top layers (N) versus Single top layer (N) with jumpers (N-1)

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One solution is to make use of the polygon operations like OR and XOR.

Figure 11. Application for XOR and RESIZE

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Besides basic power plan region formation, custom power plan or power grid can be accommodated with a twist of the flow. For instance, resize_polygon seems straight forward but can be
quite powerful if use wisely. For example, design with hard macro of irregular shapes cannot be
simply grouped to form a power plan region if macro overlapped and causing self-cutting polygon (see Fig.12) when grouped (OR) together, due to tool limitation.

Figure 12. Overlapping irregular shaped macros

By simply resizing the left macro to the right before ORg with the macro to the right (see
Fig.13), the self-cutting polygon is eliminated and therefore forming a legal and desired power_plan_regions.

Figure 13. Resized then OR before power plan region creation

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Another example of utilizing polygon operations to guide power strapping is as follows.

Figure 14. Column of MTCMOS in a power domain

In Fig 14. multiple columns of MTCMOS (header cells) are placed and required lower layer N-3
vertical as well as Layer (N-2) horizontal strapping to the Top Layer N strapping right on top of
the columns. One way to accomplish the task is to form a power plan region around the
MTCMOS cells ( see Fig 15. )

Figure 15. create_power_plan_regions ... get_cells *mtcmos*

However, the columns are bound together to form a single polygon which includes an unwanted
channel between columns. To get ride of the channel, polygon coordinates of the
power_plan_region can be extracted by:
get_attribute [get_power_plan_regions pp_mtcmos] points
and then the resulting polygon coordinates specified by the points can be recalculated to get
ride of the unwanted channels.
Finally, vertical and horizontal straps can be generated by the template-based flow as follows:
Set_power_plan_strategy strategy_mtcmos_merged \
-power_plan_regions $pp_mtcmos_merged \
-nets {vccd vccd_virt} \
-extension {stop:first_target} \
-template $scrdir/mtcmos.tpl:met23_strap

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Compile_power_plan strategy {strategy_mtcmos_merged}

Fig.16 shows the vertical and horizontal straps put in by compiler power_plan.

Figure 16. MTCMOS power strapping

Calculating and displaying the Skeleton & centroid of a polygon helps build a rigid grid.
The centroid can be defined as the point about which the polygon would balance if it were cut
out in plywood of uniform thickness and suspended.
Figure 17. Centroid of a polygon

Using convert_from_polygon can spit complex polygon

into multiple simple polygons. By using simple skeleton algorithm, the skeleton of the polygon can be derived to better
form a fairly distributed power grid with strong structural support. The numbers, location and
spacing of the stripes of the power network can then be derved from the skeleton characteristics.
These data would help set and automate the location and strapping of the polygon.
Non uniform Power Mesh can minimize voltage drop variations due to increasing IRdrop from
pads to center of the Chip. Most common hot spots happen at the center of the die or the spot
furthest away from any power and ground sources, simply because the center region of the power
grid sees the highest resistance to the sources. However , if the width of the power and ground
stripes are increased further from the sources, the resistance will be reduced, which will also reduce the voltage drop. By applying custom algorithm manipulation on the power grid, any high
variation of on chip ir drop can be reduced by varying the width of the stripes according. It can
even be somewhat automated by first dumping out the voltage drop of the power grid. By feeding the x,y coordinates and the voltage drop values back to the power grid template, custom
power grid can be tailored fit for each chip.
Knowing the area of the power plan regions by using get_polygon_area is advantageous. With
the reported area, power consumption can be estimated based on num of rows, register counts,
buffer counts, etc. Best fit power templates can then be selected based on the power consumption

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values to further automate the power strategy decision. In additions, if the power plan region is a
shutdown power plan which requires power switches, the number of power switches can also be
derived automatically based on the power consumption and the driving capabilities of the power
switches.

4. Flow Advantages and Results

Using the features described provide a speedy power network prototype of which can be easily
enhanced and adapted to any upcoming floorplan changes due to design changes. Simple power
network completes in minutes, really complex power network completes within hours. But since
the flow is automated, the design can react to ECO quickly. Physical designers can then spend
less time and resources on power network design and focus more on cell placement, clock tree
synthesis and timing closure.

5. Conclusions
Template-based Power Network Synthesis, combined with the basic polygon operations, provides a flexible and automated flow for generating or prototyping complex power network for
integrated circuits. Nevertheless, more polygon operations can be added to enable even more
complex operations which would ease polygon formation. I would also like to see power consumption values as an input in the template-based power network to automatically derive the
number of stripes needed to meet voltage drop requirement.

6. References
[1] Synopsys Template-Based Power Network Synthesis Application Note Version E-2010.12-SP2,
March 2011
[2] Synopsys Basic Polygon Operations in IC Compiler Application Note Version C-2009.06, December
2009

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