Beruflich Dokumente
Kultur Dokumente
P.G. Scholar (M. Tech), Dept. of ECE, BITIT College of Engineering, Anantapur
2
Asst Professor, Dept. of ECE, BITIT College of Engineering, Anantapur
Email: 1pc.shilpa31@gmail.com, 2mhpradeepk@gmail.com
AbstractA model of a switched capacitor digital-toanalog converter (DAC) based on a split capacitor
array is presented for use during the design of a
successive approximation register (SAR) analog-todigital converter (ADC). The model takes the effects of
parasitic capacitors into account, and the values of these
parasitic capacitors can be extracted from the circuit
topology by using Calibre by Mentor Graphics or a
similar tool. The influence of the two main parasitic
capacitor types (those parallel to and those common to
the capacitors in the arrays) on the DAC characteristics
is analyzed. We provide expressions for fast manual
calculation of the integral non-linearity (INL) and
differential non-linearity (DNL) errors according to the
value of the parasitic capacitors. Simulation results
from a Verilog-A module based on this model are given.
The model provides higher simulation speeds with
accuracy close to that of a transistor-level model by
using the extracted parasitic parameters.
I. INTRODUCTION
The use of the top-down methodology can
dramatically speed up the IC design process because
it avoids the difficulties of transistor-level simulation
of the whole system [1], [2]. As shown in [3], [4], this
approach involves behavioral modeling at different
levels of abstraction. The use of behavioral models
describing the low-level effects that arise in real
circuits can save time while providing levels of
accuracy close to that of transistor-level simulations.
Use of such a model gives designers the opportunity
to analyze how these low-level effects affect the
whole chip on a system level [5] and also to find the
possible range of low-level effects (for example,
parasitic capacitance) that is acceptable for the
design. The split capacitor array, used as both a DAC
and a sampleand- hold circuit, is an important
element of the SAR ADC.
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QM = (Vref Vp)CpM,
QL = (Vref Vp)CpL, (4)
where Vp is the voltage on the top plates of the
capacitors in the array. (4) can be rewritten as
follows:
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w
hich is code dependent error of DAC. Thus, we can
see that only CpL has an influence on the DAC
output voltage. Also, from equation (8), it follows
that a nonlinearity in the transfer function occurs only
when a capacitor in the MSB half of the array is
switched. We calculate the DNL based on the work of
[9]:
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V. VERILOG-A MODEL
A Verilog-A model is based on the expressions (8 12). The model allows to enable and disable some
features through OffsetError, GainError and
NonLinearity control parameters. The values of CpL,
and Ca are also the parameters of the model. They
can be extracted from the layout by using the
software tools such as Mentor Graphics Calibre. All
transistors are replaced by ideal switches. The
expressions (8 - 12) take C0 from (19) instead of C0
[3]
[4]
[5]
[6]
[7]
[8]
[9]
VII. CONCLUSION
In this work, a model of a split capacitor array for a
DAC that is usually used in SAR ADC design was
presented. This model provides simple expressions
for fast manual calculations of the DACs INL and
DNL. This model can also be used for fast simulation
of the DAC in a top-down design flow, saving
simulation time. This model gives the designer an
opportunity to see the impact of device physics on the
system behavior on the higher steps of the top-down
methodology.
REFERENCES
[1]
[2]
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