Lecture 11

Digital Circuits (I)

THE INVERTER

Outline
Introduction to digital circuits
The inverter
NMOS inverter with resistor pull-up

Reading Assignment:
Howe and Sodini; Chapter 5, Sections 5.1-5.3

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Lecture 11

1. Introduction to digital circuits: the inverter

In digital circuits, digitally-encoded information is
represented by means of two distinct voltage ranges:
V
VMAX
logic 1
VOH
VOL

undefined
region
logic 0

VMIN

The Static Definition

Logic 0:

VMIN V VOL

Logic 1:

VOH V VMAX

Undefined logic value: VOL V VOH

Logic operations are performed using logic gates.

Simplest logic operation of all: inversion inverter
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Lecture 11

Ideal inverter
OUT=IN

IN

IN

OUT

Circuit representation and ideal transfer function:

VOUT

v+

V+

VOUT=VIN

V+

VIN

VOUT
-

0
0

V M= V
2

V+ VIN

Define switching point or logic threshold :

VM input voltage for which VOUT = VIN

For 0 VIN < VM
For VM < VIN V+

VOUT = V+
VOUT = 0

Ideal inverter returns well defined logical outputs (0 or

V+) even in the presence of considerable noise in VIN
(from voltage spikes, crosstalk, etc.)
signal is regenerated!
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Lecture 11

Real inverter
VOUT

logic 1

VMAX
VOH

slope=-1

transition
region
logic 0

VOL
VMIN
0

V+

VIN

In a real inverter, valid logic levels defined as follows:

Logic 0:
VMIN output voltage for which VIN = V+
VOL smallest output voltage where slope = -1

Logic 1:
VOH largest output voltage where slope = -1
VMAX output voltage for which VIN = 0

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Lecture 11

Two other important voltages:

VOUT
VMAX
VOH

logic 1

slope=-1

undefined
region
logic 0

VOL
VMIN
0

VIL

VIH

V+

VIN

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Define:
VIL smallest input voltage where slope = -1
VIH highest input voltage where slope = -1
If range of output values VOL to VOH is wider than the
range of input values VIL to VIH, then the inverter
exhibits some noise immunity. (|Voltage gain| > 1)

Quantify this through noise margins.

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Lecture 11

Chain of two inverters:

noise

VOUT
VOH

VOL

VIN

NMH

VIH
VIL

NML

inverter M
output

inverter N
input

Define noise margins:

NMH VOH - VIH
NML VIL - VOL

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noise margin high

noise margin low

Lecture 11

Simplifications for hand calculations:

Logic levels and noise margins
It is hard to compute points in transfer function with
slope = -1.
Approximate in the following way:
VOUT
VOH=VMAX

slope= Av
VOUT=VIN

VM

VOL=VMIN
0

VIL VM VIH

V+

VIN

Assume VOL VMIN and VOH VMAX

Trace tangent of transfer function at VM
Slope = small signal voltage gain (Av) at VM

VIL intersection of tangent with VOUT = VMAX

VIH intersection of tangent with VOUT = VMIN

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Transient Characteristics
Inverter switching in the time domain:
VIN

VOH

90%
50%
10%
0

VOL

tPHL

VOUT

tF

tR

tPLH
VOH

90%
50%
10%
0

tF

VOL
t

tR
tCYCLE

tR
rise time between 10% and 90% of total swing
fall time between 90% and 10% of total swing
tF
tPHL propagation delay from high-to-low between
50% points
tPLH propagation delay from low-to-high between
50% points

Propagation delay :

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1
tP = (t PHL + t PLH )
2
Lecture 11

Simplifications for hand calculations:

Propagation delay

Consider input waveform is an ideal square wave

Propagation delay times = delay times to 50% point
VIN
VOH

tCYCLE

VOL
t
VOUT

tPHL

tPLH

VOH

VOH
50%

tCYCLE

VOL
t

SPICE essential for accurate delay analysis

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Lecture 11

2. NMOS inverter with pull-up resistor

V+=VDD

IR
VOUT
ID

VIN

CL
load capacitance
(from following
stages)

Essential features:

VBS = 0 (typically not shown)

CL summarizes capacitive loading of the following
stages (other logic gates, interconnect lines, etc.)

Basic Operation:

If VIN < VT, MOSFET is OFF

VOUT = VDD

If VIN > VT, MOSFET is ON

VOUT small
Value set by resistor / nMOS divider

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VDD
+
R

IR V R
-

VOUT

ID
VIN

Transfer function obtained by solving:

IR = ID
Can solve graphically: IV characteristics of load:

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Overlap IV characteristics of resistor pull-up on IV

characteristics of transistor:
load line

IR=ID

VGS=VDD

VDD
R

VGS=VIN

VGS=VT
0
0

VDD

VDS =VOUT

Transfer function:
VOUT=VDS
VDD

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VT

VDD

Lecture 11

VIN=VGS

12

Logic levels:
VOUT=VDS
VMAX=VDD

VOUT=VIN
VM

VMIN
0

VT

VM

VDD

VIN=VGS

For VMAX, transistor is cut-off, ID = 0:

VMAX = VDD
For VMIN, transistor is in linear regime; solve:
W
V
V VMIN

n Cox VDD MIN VT VMIN = IR = DD

2
R
L

ID =

For VM, transistor is in saturation; solve:

ID =

W
V VM
2
n Cox (VM VT ) = I R = DD
R
2L

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Noise Margins:
VOUT=VDS
VMAX=VDD

VOUT=VIN

Av

VMIN
0

VDD

VT

VIN=VGS

Small signal equivalent circuit model at VM

(transistor in saturation):
R
D

vin

vgs

gmvgs

Av =
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vout
-

vin

ro

gmvin

(ro//R) vout
-

v out
= g m(ro // R) gm R
vin
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14

What did we learn today?

Summary of Key Concepts

Logic circuits must exhibit immunity to noise in the

input signal
Noise margins

Logic circuits must be regenerative

Able to restore clean logic values even if input is
noisy.

Propagation delay: time for logic gate to perform

its function.
Concept of load line: graphical technique to
visualize transfer characteristics of inverter.
First-order solution (by hand) of inverter figures-ofmerit easy if regions of operation of transistor are
correctly identified.
For more accurate solutions, use SPICE (or other
CAD tool).

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