NAME __Solutions _______________________

FINAL EXAM
(Closed book)

ECE 442

Fall 2009
2 hours

Instructions: Write your name where indicated. This examination consists of 4 problems. You
are allowed to use a calculator and 2 formula sheets (81/2 by 11 in). Show all work.

Problem 1

Problem 2

Problem 3

Problem 4

Total

(30 pts)

(20 pts)

(20 pts)

(30 pts)

(100 pts)

Formula Sheet
DIODE

I D = I S (eVD / VT 1) , where VT =

k BT
= 26 mV
q

BIPOLAR (NPN forward active IB>0, VCE>VCE,sat)

V
kT
I C = I S eVBE / VT 1 + CE I S eVBE / VT where VT = B = 26 mV
q
VA

I C = I E = I B 1 + CE I B
=
+1
VA

Small Signal Characteristics:

V
I
V
g m = C ; = g m r ; r = re ( + 1) ; re = T ; ro = A
VT
IE
IC

MOSFET (long channel model equations)

Define VDSP = VGS-VT, where VT is the threshold voltage
NMOS

PMOS

Triode Region (Linear)

VGS < VT & VDS > VDSP ,

Triode Region (Linear)

VGS > VT & VDS < VDSP ,
ID =

V2
W
n Cox (VGS VT ) VDS DS
L
2

ID =

V2
W
p Cox (VGS VT ) VDS DS
2
L

Active Region (Saturation)

VGS > VT & VDS VDSP ,
W C
I D = n ox (VGS VT ) 2 [1 + VDS ]
L
2

Active Region (Saturation)

VGS < VT & VDS VDSP ,
W C
I D = p ox (VGS VT ) 2 [1 VDS ]
L
2

Body Effect

Body Effect

VT = VTo +

VSB + 2F 2F

VT = VTo

VGS VT , I D = 0

VSB + 2F 2F

VGS VT , I D = 0

Small Signal Characteristics (NMOS):

V
1
W
g m = 2n Cox I D ; rds = A =
L
ID ID

-2-

1. For the circuit shown, assume that =100, VBE = 0.6 V, fT = 107 Hz and C =10 pF at the bias
point used.

Determine the following quantities

(a) The DC base voltage VB

VCC R2
18 8
=
= 2.05 V
R1 + R2 62 + 8

VB =

VB = ____2.05 V
(b) The DC collector current IC
VE = VB VBE = 2.05 0.6 = 1.45 V
VE =

VE 1.45
=
= 2.91 mA
RE 0.5

+1

= 100 /101

I C = I E = 2.88 100 /101 = 2.88 mA

IC = ____2.88 mA____
-3-

(c) The midband voltage gain

gm =

IC
2.88
=
= 110.97 mA / V
VT 0.026

r = / g m = 100 /110.97 = 0.901 k

AMB =

RC
r + Rg

100 1
= 66.6
0.901 + 0.6

AMB = ____66.6___
(d) The upper 3-dB frequency
C + C =

gm

C =

gm

C =

110.97 103
1011 = 1756 pF
+7
2 10

Ceq = C + C (1 + g m RC ) = 1756 + 10(1 + 110.97) = 2875.7 pF

R = Rg & r =
f3dB =

(0.901)(0.6)
= 0.360 k
0.901 + 0.6

1
1
=
= 153.6 kHz
+3
2 RCeq 2 0.360 10 2875.7 1012

f3dB = ___153.6 kHz__

More accurate approach:
f 3dB =

f 3dB =
f 3dB =

1 + Ri g

2 Ri C + C ( 1 + g m RC' ) + C RC' ( 1 + Ri g )

1 + ( 0.6 10 +3 1.1098 10 3 )

2 0.6 10 +3 1756 10 12 + 2875 10 12 + 10 10 12 1 10 +3 1 + ( 0.6 10 +3 1.1098 10 3 )

1.6658 10 +9
= 95.18 kHz
2 ( 2778.6 + 6.658 )

f3dB = ___95.18 kHz__

-4-

2. Using an ideal op amp, design an inverting circuit for which the voltage gain is -5 V/V and the
total value of resistance used is 120 k. (Draw circuit schematic and show component values.)

For inverting amplifier, closed-loop gain is: G =

RF
R1

Thus, we must have:

RF
= 5
R1

and RF + R1 = 120

5R1 + R1 = 120 6 R1 = 120 R1 = 20 k

RF = 5R1 RF = 100 k
R1 = ____20 k___
RF = ____100 k___

-5-

3. The current source shown in the figure utilizes a pair of matched pnp transistors having
IS=10-15 A, = 50, and |VA| = 50V. It is required to design the circuit to provide an output
current Io = 1 mA at Vo = 2 V.

(a) What values of IREF and R are needed?

IREF = Io = 1 mA
VREF =5-0.7=4.3
R = 4.3/1=4.3 k

IREF = __1 mA _________

R = __4.3 k ________

-6-

(b) If this current source is to be used as an active load for a common-emitter amplifier, what
is the equivalent load impedance presented by the active load.

RL = ro =

| VA | 50
=
= 50k
1
IC

RL = ___50 k___________

-7-

4. In the differential amplifier shown, Q1 and Q2 form the differential pair while the current
source transistors Q4 and Q5 form the active loads for Q1 and Q2 respectively. The dc bias circuit
that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. The following
specifications are desired: differential gain Ad = 100 V/V, IREF = 100 A, the dc voltage at the
gates of Q6 and Q3 is +1.5V; the dc voltage at the gates of Q7, Q4 and Q5 is 1.5V.

The technology available is specified as follows: nCox=3pCox = 100A/V2; Vtn=|Vtp| = 0.7 V,

VAn=|VAp| = 20V. Specify the required value of R and the W/L ratios for all transistors. Also,
specify ID and VGS at which each transistor is operating. For dc bias calculations, you may
neglect channel-length modulation. Fill in the entries in the table provided to show your results.

-8-

I REF = 100 A =

1.5 (1.5)
3V
R=
= 30k
0.1mA
R
R = ____30 k_____

ro1 = ro 2 = ro 4 = ro 5 =

VAp
I1

20
= 400 k
50 106

Drain currents are determined by symmetry and inspection

VGS values are also determined by inspection for all transistors except Q1 and Q2. To determine
VGS for Q1 and Q2, we do the following: the equivalent load resistance will consist of ro1 in
parallel with ro4 for Q1 and ro2 in parallel with ro5 for Q5. Since the ros are equal, this
corresponds to ro/2.
We have
gm

ro
2A
2 100
= Ad g m = d =
= 0.5 mA / V
2
ro
400k

gm =

2I D
2I
2 0.05
Vov = D =
= 0.2 V
Vov
gm
0.5

Take polarity into account for PMOS

VGS 1,2 = 0.2 VT = 0.9 V
To find W/L ratios, use: I D = Cox

2I D
W
W
(VGS VT ) 2 =
2L
L Cox (VGS VT ) 2

taking into account PMOS and NMOS devices separately

CMOS OP-AMP DESIGN TABLE
Q1

Q2

Q3

Q4

Q5

Q6

Q7

Units

Cox

33.33

33.33

33.33

100

100

33.33

100

A/V2

ID

50

50

100

50

50

100

100

VGS

-0.9

-0.9

-1

+1

+1

-1

+1

W/L

75

75

66.67

11.11

11.11

66.67

22.22

-9-