Digital Systems - 2

Pere Pal`a - Alexis L

opez
iTIC http://itic.cat

February 2015

Numeric Basics

Coding of numeric information:

Decimal system: 3710 means 3 101 + 7 100 .

Decimal system: 20310 means 2 102 + 0 101 + 3 100 .

3710 = 1 25 + 0 24 + 0 23 + 1 22 + 0 21 + 1 20 .

3710 = 1001012 .

n bits : 0 2n 1.

To represent 0 N 1 we need log2 N bits.

Unsigned Integers

Declaration: signal s_unsig : unsigned(3 downto 0);

Assignments
Legal: s_unsig <= "1110";
Illegal: s_unsig <= 0;
Legal: s_unsig_dest <= s_unsig+1;

Conversions
I

my_slv <= std_logic_vector(my_unsigned);

my_unsigned <= unsigned(my_slv);

A VHDL type test example

library ieee ; use ieee . std_ logic_1 164 . all ;
use ieee . numeric_std . all ;
entity num_tb is
end num_tb ;
architecture behav of num_tb is
signal s_logic : st d _ l o g i c _ v e c t o r (3 downto 0) ;
signal s_unsig : unsigned (3 downto 0);
begin
s_logic <= s t d _ l o g i c _ v e ct o r ( s_unsig );
process
begin
s_unsig <= " 1110 " ;
wait for 1 sec ;
s_unsig <= s_unsig +1;
wait for 1 sec ;
s_unsig <= s_unsig +1;
wait for 1 sec ;
s_unsig <= s_unsig +1;
wait for 1 sec ;
wait ;
end process ;
end behav ;

Assignments
Resizing an unsigned integer
signal a : unsigned (3 downto 0);
signal b : unsigned (7 downto 0);
b <= " 0000 " & a ;
a <= b (3 downto 0);

Concatenation operator:

Only in the right hand of assignments!

&

Alternate way
signal a : unsigned (3 downto 0);
signal b : unsigned (7 downto 0);
b <= resize (a ,8);
a <= resize (b ,4);

Adding Unsigned Integers

Algorithm
1

0
1
0

0
1
0

1
0
0

1
0
0

1
1
0

0
1
1

0
0
0

xi

yi

1
0
1

Implementation
xn1 yn1
cn
sn

full
adder

sn1

cn1

ci+1

full
adder

si

x1
ci

c2

y1

full
adder

s1

x0
c1

y0

full
adder

c0

s0

c_out <= (a and b) or (c_in and (a xor b)); This is slooow!

Adders
Fast-carry-chain adder
I

Carry kill: ki = not xi and not yi

Carry propagate: pi = xi xor yi

xi

yi

pi

ci+1

Carry generate: gi = xi and yi

pi = xi yi

gi

g i = xi yi

ci

ci +1 = g i + pi ci
si = pi ci

si

si = pi xor c_in;
co = gi or pi and c_in;

Carry-lookahed generator
I

x3

y3

x2

y2

x1

y1

x0

y0

Example for 4 bits

g3

c4 = g3 or (p3 and g 2)
or (p3 and p2 and g1)
or (p3 and p2 and p1 and g 0)
or (p3 and p2 and p1 and p0 and c0)

c4

p3

g2

p2

g1

p1

g0

carry-lookahead generator
p3

s3

c3

p2

s2

c2

p1

s1

c1

p0

s0

p0

c0

Adder in VHDL

library ieee ;
use ieee . std_log ic_1164 . all ;
use ieee . numeric_std . all ;
...
signal a ,b , s : unsigned (3 downto 0);
...
s <= a + b ;
I

Do not specifiy the equations!

The software automatically detects the best type of adder.

This is dependent on the technology and the requirements of

the designer (speed, area).

Adder with Carry Out

library ieee ;
use ieee . std_log ic_1164 . all ;
use ieee . numeric_std . all ;
...
signal a ,b , s : unsigned (7 downto 0);
signal temp : unsigned (8 downto 0); -- MSB : carry
signal c_out : std_logic ;
...
temp <= ( 0 & a ) + ( 0 & b ); -- compute sum with 9 bits
s
<= temp (7 downto 0);
-- true sum is in LSBs
c_out <= temp (8);
-- carry is the MSB

Comparing unsigned integers

library ieee ;
use ieee . std_log ic_1164 . all ;
use ieee . numeric_std . all ;
entity ...
port temp
: in unsigned (7 downto 0);
port target : in unsigned (7 downto 0);
port heat
: out std_logic ;
architecture ...
heat <= 1 when temp < target - 5 else 0 ;
I

Synthesis software will implement the function.

Comparing unsigned integers

library ieee ;
use ieee . std_log ic_1164 . all ;
use ieee . numeric_std . all ;
entity ...
port temp
: in unsigned (7 downto 0);
port target : in unsigned (7 downto 0);
port heat
: out std_logic ;
architecture ...
heat <= 1 when temp < target - 5 else 0 ;
I

Synthesis software will implement the function.

xn1
yn1

xn1 > yn1

xn2
yn2

xn2 > yn2

gt

xn1 = yn1
xn20 > yn20

xn2 = yn2

x1 > y1

x0
y0

x0 > y0

x1 = y1

x1
y1

x10 > y10