Beruflich Dokumente
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FEATURES
ADG714 SPI/QSPI/MICROWIRE-Compatible Interface
ADG715 I2C-Compatible Interface
2.7 V to 5.5 V Single Supply
2.5 V Dual Supply
2.5 On Resistance
0.6 On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
ADG714
S1
D1
S1
D1
S2
D2
S2
D2
S3
D3
S3
D3
S4
D4
S4
D4
S5
D5
S5
D5
S6
D6
S6
D6
S7
D7
S7
D7
S8
D8
S8
D8
INPUT SHIFT
REGISTER
INTERFACE
LOGIC
DOUT
RESET
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
GENERAL DESCRIPTION
SDA
SCL
A0
A1
On power-up of these devices, all switches are in the OFF condition, and the internal registers contain all zeros.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual 2.5 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS
REV. C
Document Feedback
ADG714/ADG715SPECIFICATIONS1(V
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
40C
+25C
to +85C
2.5
4.5
0.6
0.01
0.1
0.01
0.1
0.01
0.1
0.3
0.3
0.1
0.005
0.05 VDD
6
V min
V max
V min
V max
A typ
A max
V min
pF typ
0.4
0.6
20
95
8
15
tOFF ADG715
85
130
8
3
60
80
70
90
155
11
11
22
V min
V max
A typ
A max
pF typ
0.7 VDD
VDD + 0.3
0.3
0.3 VDD
140
tOFF ADG714
nA typ
nA max
nA typ
nA max
nA typ
nA max
V max
pF typ
32
tON ADG715
Unit
0.4
4
DYNAMIC CHARACTERISTICS 2
tON ADG714
0.3
0 V to VDD V
typ
5
max
0.4
typ
0.8
max
typ
1.2
max
2.4
0.8
0.005
DD
20
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = VS = 1 V, or 4.5 V
ISINK = 6 mA
VIN = 0 V to VDD
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 3 V, RL = 300 , CL = 35 pF
A typ
A max
10
Test Conditions/Comments
VS = 3 V, RL = 300 , CL = 35 pF
VS = 3 V, RL = 300 , CL = 35 pF
VS = 3 V, RL = 300 , CL = 35 pF
VS = 3 V, RL = 300 , CL = 35 pF
VS = 2 V, RS = 0 , CL = 1 nF
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: 40C to +85C.
2
Guaranteed by design, not subject to production test.
Specications subject to change without notice.
REV. C
SPECIFICATIONS
ADG714/ADG715
(VDD = 3 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted.)
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
40C
+25C
to +85C
6
11
0.01
0.1
0.01
0.1
0.01
0.1
0.005
0.05 VDD
6
0.4
V max
pF typ
ISINK = 6 mA
0.7 VDD
VDD + 0.3
0.3
0.3 VDD
V min
V max
V min
V max
A typ
A max
V min
pF typ
0.4
0.6
35
130
11
20
tOFF ADG715
115
180
8
2
60
80
70
90
155
11
11
22
NOTES
1
Temperature range is as follows: B Version: 40C to +85C.
2
Guaranteed by design, not subject to production test.
Specications subject to change without notice.
VS = VD = 1 V, or 3 V
VIN = 0 V to VDD
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 2 V, RL = 300 , CL = 35 pF
A typ
A max
10
20
REV. C
VS = 0 V to VDD, IS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V
0.1
200
tOFF ADG714
VS = 0 V to VDD, IS = 10 mA
V min
V max
A typ
A max
pF typ
0.3
65
tON ADG715
VS = 0 V to VDD, IS = 10 mA
VS = 1 V/3 V, VD = 3 V/1 V
0.3
Test Conditions/Comments
nA typ
nA max
nA typ
nA max
nA typ
nA max
0.3
DYNAMIC CHARACTERISTICS 2
tON ADG714
0 V to VDD V
typ
12
max
0.4
typ
1.2
max
3.5
typ
2.0
0.8
0.005
Unit
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 2 V, RL = 300 , CL = 35 pF
VS = 1.5 V, RS = 0 , CL = 1 nF
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG714/ADG715SPECIFICATIONS1
DUAL SUPPLY (V
DD
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
2.5
4.5
0.6
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
VSS to VDD V
typ
5
max
0.4
typ
0.8
max
typ
1
max
0.3
0.3
0.3
1.7
0.7
0.005
Unit
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
V min
V max
A typ
A max
pF typ
0.4
V max
pF typ
ISINK = 6 mA
0.7 VDD
VDD + 0.3
0.3
0.3 VDD
V min
V max
V min
V max
A typ
A max
V min
pF typ
0.1
3
2
0.005
0.05 VDD
6
0.4
0.6
20
32
tON ADG715
133
200
tOFF ADG714
8
18
tOFF ADG715
124
190
8
3
60
80
70
90
155
11
11
22
25
ISS
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 1.5 V, RL = 300 , CL = 35 pF
A typ
A max
A typ
A max
15
15
25
NOTES
1
Temperature range is as follows: B Version: 40C to +85C.
2
Guaranteed by design, not subject to production test.
Specications subject to change without notice.
VIN = 0 V to VDD
VS = 1.5 V, RL = 300 , CL = 35 pF
VS = 1.5 V, RL = 300 , CL = 35 pF
VS = 1.5 V, RL = 300 , CL = 35 pF
VS = 1.5 V, RL = 300 , CL = 35 pF
VS = 0 V, RS = 0 , CL = 1 nF
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF, f = 10 MHz
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF
REV. C
ADG714/ADG715
ADG714 TIMING CHARACTERISTICS1, 2 (V
DD
Parameter
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9 3
30
33
13
13
0
5
4.5
0
33
20
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
NOTES
1
See Figure 1.
2
All input signals are specied with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
CL = 20 pF, RL = 1 k.
Specications subject to change without notice.
t1
SCLK
t8
t2
t3
t7
t4
SYNC
t6
t5
DB7
DIN
DB0
t9
DB7*
DOUT
*DATA
DB6*
DB2*
DB1*
DB0*
REV. C
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1 (V
DD
Parameter
Unit
Conditions/Comments
fSCL
t1
t2
t3
t4
t5
t6 2
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
kHz max
s min
s min
s min
s min
ns min
s max
s min
s min
s min
s min
300
20 + 0.1Cb3
250
300
0.1Cb3
400
50
ns max
ns min
ns max
ns max
ns min
pF max
ns max
t7
t8
t9
t10
t11
t11
Cb
tSP4
NOTES
1
See Figure 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undened region of
SCLs falling edge.
3
Cb is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 VDD.
4
Input ltering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specications subject to change without notice.
SDA
t9
t3
t4
t11
t10
SCL
t4
t6
t2
t5
START
CONDITION
t7
REPEATED
START
CONDITION
t1
t8
STOP
CONDITION
REV. C
ADG714/ADG715
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 3.5 V
Analog Inputs2 . . . . . . . . . . . . . . . . . VSS 0.3 V to VDD +0.3 V
or 30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD +0.3 V
or 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40C to +85C
Storage Temperature Range . . . . . . . . . . . . 65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300C
Infrared Reflow (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 235C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specication is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
24-Lead TSSOP
REV. C
SCLK
24
SYNC
SCL
24
A0
VDD
23
RESET
VDD
23
RESET
DIN
22
DOUT
SDA
22
A1
GND
21
VSS
GND
21
VSS
S1
20
S8
S1
20
S8
D1
D1
ADG714
ADG715
S2
TOP VIEW 19 D8
(Not to Scale)
7
18 S7
S2
TOP VIEW 19 D8
(Not to Scale)
7
18 S7
D2
17
D7
D2
17
D7
S3
16
S6
S3
16
S6
D3 10
15
D6
D3 10
15
D6
S4 11
14
S5
S4 11
14
S5
D4 12
13
D5
D4 12
13
D5
ADG714/ADG715
ADG714 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
SCLK
2
3
VDD
DIN
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
22
GND
Sx
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices can accommodate serial input rates of up to 30 MHz.
Positive Analog Supply Voltage.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
Ground Reference
Source. May be an input or output.
Dx
VSS
DOUT
23
24
RESET
SYNC
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of
the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the
switches.
ADG715 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire
serial interface.
2
3
VDD
SDA
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
GND
Sx
Dx
VSS
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
22
A1
Address Input. Sets the second least signicant bit of the 7-bit slave address.
23
RESET
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
24
A0
Address Input. Sets the least signicant bit of the 7-bit slave address.
REV. C
ADG714/ADG715
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
RON
RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
CS (OFF)
CD (OFF)
REV. C
CD, CS (ON)
8
TA = 25C
VSS = GND
7
6
VDD = 2.7V
ON RESISTANCE
ON RESISTANCE
VDD = 3V
VSS = GND
5
VDD = 3.3V
4
VDD = 4.5V
VDD = 5.5V
+85C
4
40C
3
+25C
0
0
1
2
3
4
VD, VS, DRAIN OR SOURCE VOLTAGE V
0.5
1.0
1.5
2.0
8
7
ON RESISTANCE
ON RESISTANCE
TA = 25C
5
4
VDD = +2.25V
VSS = 2.25V
VDD = +2.5V
VSS = 2.5V
5
4
+25C
3
+85C
2
VDD = +2.5V
VSS = 2.5V
2.7
VDD = +2.75V
VSS = 2.75V
40C
1
0
2.5
2.7
2.0
1.5
1.0
0.5
0.5
1.0
1.5
2.0
2.5
0.04
VDD = 5V
VSS = GND
TA = 25C
VDD = 5V
VSS = GND
7
6
0.02
CURRENT nA
ON RESISTANCE
3.0
2.5
5
4
+85C
+25C
I S , I D (ON)
I D (OFF)
I S (OFF)
0.02
2
40C
1
0.04
0
0
1
2
3
4
VD OR VS DRAIN OR SOURCE VOLTAGE V
VD OR VS Volts
10
REV. C
ADG714/ADG715
0.04
0.1
VDD = 3V
VSS = GND
TA = 25C
0.02
VDD = 3V
VSS = GND
VD = 3V/1V
VS = 1V/3V
0.05
0
I S (OFF)
I D (OFF)
I D , I S (ON)
CURRENT nA
CURRENT nA
I S , I D (ON)
0.02
0
I D (OFF)
I S (OFF)
0.05
0.04
0
0.5
1.0
1.5
VOLTAGE V
2.0
0.1
10
3.0
2.5
20
30
50
60
40
TEMPERATURE C
80
70
0.04
VDD = +2.5V
VSS = 2.5V
TA = 25C
VDD = 5V
TA = 25C
20
ATTENUATION dB
0.02
CURRENT nA
I D (OFF)
I S (OFF)
0
I S , I D (ON)
40
60
80
0.02
100
0.04
0
VOLTAGE V
120
30k
10M
100M
VDD = +2.75V
VSS = 2.75V
VD = +2.25V/1.25V
VS = 1.25V/+2.25V
VDD = +5V
VSS = GND
VD = 4.5V/1V
VS = 1V/4.5V
I S , I D (ON)
ATTENUATION dB
CURRENT nA
1M
FREQUENCY Hz
0.1
0.05
100k
I S (OFF)
0
I D (OFF)
10
0.05
12
0.1
10
20
30
40
50
60
TEMPERATURE C
70
14
30k
80
REV. C
100k
1M
10M
FREQUENCY Hz
100M
11
300M
ADG714/ADG715
GENERAL DESCRIPTION
40
VDD = 5V
TA = 25C
ATTENUATION dB
50
60
70
When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. To minimize glitches on the output
of these switches, the part cleverly compares the state of switches
from the previous write cycle. If the switch is already in the
ON condition, and is required to stay ON, there will be minimal
glitches on the output of the switch.
80
90
100
30k
100k
1M
FREQUENCY Hz
100M
10M
POWER-ON RESET
On power-up of the device, all switches will be in the OFF condition and the internal shift register is lled with zeros and will
remain so until a valid write takes place.
10
TA = 25C
VDD = +3.3V
VSS = GND
SERIAL INTERFACE
3-Wire Serial Interface
QINJ pC
0
VDD = +5V
VSS = GND
VDD = +2.5V
VSS = 2.5V
10
Data is written to the 8-bit shift register via DIN under the control of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.
15
20
3
1
2
VOLTAGE V
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on the falling edge of
SCLK. Each bit of the 8-bit word corresponds to one of the eight
switches. Figure 3 shows the contents of the input shift register.
Data appears on the DOUT pin on the rising edge of SCLK
suitable for daisy chaining, delayed of course by eight bits. When
all eight bits have been written into the shift register, the SYNC
line is brought high again. The switches are updated with the
new conguration and the input shift register is disabled. With
SYNC held high, the input shift register is disabled, so further data
or noise on the DIN line will have no effect on the shift register.
45
VSS = GND
40
TO N , V DD = 3V
35
TIME ns
30
TO N , V DD = 5V
25
20
DB7 (MSB)
S8
TOFF , V DD = 3V
15
S7
S5
S4
S3
S2
S1
DATA BITS
10
5
0
10
DB0 (LSB)
S6
TOFF , V DD = 5V
20
30
40
50
60
TEMPERATURE C
70
SERIAL INTERFACE
2-Wire Serial Interface
80
The ADG715 has a 7-bit slave address. The ve MSBs are 10010
and the two LSBs are determined by the state of the A0 and
A1 pins.
12
REV. C
ADG714/ADG715
The 2-wire serial bus protocol operates as follows:
Write Operation
When writing to the ADG715, the user must begin with an address
byte and R/W bit, after which the switch will acknowledge that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in the Figure 4.
3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is
dened as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a no acknowledge
for the ninth clock pulse (i.e., the SDA line remains high).
The master will then bring the SDA line low before the tenth
clock pulse and then high during the tenth clock pulse to establish a STOP condition.
READ Operation
When reading data back from the ADG715, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to transmit data by pulling SDA
low. The readback operation is a single byte that consists of the
eight data bits in the input register. The read operation for the
part is shown in Figure 5.
SCL
SDA
START
COND
BY
MASTER
A1
A0
R/W
S8
S7
S6
S5
ACK
BY
ADG715
ADDRESS BYTE
S4
S3
S2
S1
DATA BYTE
ACK
BY
ADG715
STOP
COND
BY
MASTER
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
SCL
SDA
START
COND
BY
MASTER
ADDRESS BYTE
A1
A0
R/W
S8
ACK
BY
ADG715
S7
S6
S5
DATA BYTE
REV. C
13
S4
S3
S2
S1
ADG714/ADG715
APPLICATIONS
Multiple Devices On One Bus
VDD
RP
RP
SDA
MASTER
SCL
VDD
SDA
SCL
A1
SCL
SDA
A1
A0
VDD
VDD
SDA
SDA
A1
A0
ADG715
SCL
A0
ADG715
SCL
A1
A0
ADG715
ADG715
VDD
R
SCLK
SCLK
SYNC
DIN
SYNC
R
SCLK
ADG714
DIN
DOUT
VDD
ADG714
DIN
R
SCLK
DOUT
SYNC
ADG714
DIN
SYNC
DOUT
TO
OTHER
SERIAL
DEVICES
14
REV. C
ADG714/ADG715
devices on the SPI bus. Figure 8 illustrates the ADG739 and multiple ADG714s in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device will
receive the SYNC signal at any one time. The ADG739 is a serially
controlled device also. One bit programmable pin of the microcontroller is used to enable the ADG739 via SYNC2, while
another bit programmable pin is used as the chip select for the
other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By bringing
SYNC1 low, the selected serial device hanging from the SPI bus
will be enabled and data will be clocked into its shift register on
the falling edges of SCLK. The convenient design of the matrix
switch allows for different combinations of the four serial
devices to be addressed at any one time. If more devices need
to be addressed via one chip select line, the ADG738 is an 8channel device and would allow further expansion of the chip
select scheme. There may be some digital feedthrough from the
digital input lines because SCLK and DIN are permanently
connected to each device. Using a burst clock will minimize the
effects of digital feedthrough on the analog channels.
VDD
ADG714
SYNC
DIN
SCLK
VDD
ADG714
SYNC
VDD
DIN
SCLK
1/2 of ADG739
S1A
SYNC1
DA
VDD
S2A
R
S3A
S4A
DIN
SYNC2
DIN
SCLK
OTHER
SPI
SYNC DEVICE
SCLK
VDD
R
OTHER
SPI
SYNC DEVICE
DIN
SCLK
REV. C
15
ADG714/ADG715
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8
0
0.75
0.60
0.45
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
ORDERING GUIDE
Model1
ADG714BRU-REEL
ADG714BRU-REEL7
ADG714BRUZ
ADG714BRUZ-REEL
ADG714BRUZ-REEL7
ADG715BRU
ADG715BRU-REEL
ADG715BRU-REEL7
ADG715BRUZ
ADG715BRUZ-REEL
ADG715BRUZ-REEL7
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
Package Description
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
Package Option
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
REVISION HISTORY
1/13Rev. B to Rev. C
Changes to Dual Supply Table Summary and IDD Test
Conditions/Comments ..................................................................... 4
Changes to Ordering Guide ...........................................................16
11/02Rev. A to Rev. B
Edits to Features ................................................................................ 1
Edits to General Description ........................................................... 1
Edits to Product Highlights ............................................................. 1
Edits to Specifications ...................................................................3, 4
Edits to TPCs 2 and 5 .....................................................................10
Edits to TPCs 8 and 9 .....................................................................11
Edits to TPCs 14 ..............................................................................12
Edits to Figure 8...............................................................................15
2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00043-0-1/13(C)
16
REV. C