INTRODUCTION TO MICRO COMPUTER AND MICROPROCESSOR

Introduction
A Microprocessor is a multipurpose programmable logic device which reads the binary
instructions from a storage device called Memory , accepts binary data as input and process
data according to the instructions and gives the results as output. So, you can understand the
Microprocessor as a programmable digital device, which can be used for both data processing
and control applications. In view of a computer student, it is the CPU of a Computer or heart of
the computer. A computer which is built around a microprocessor is called a microcomputer. A
microcomputer system consists of a CPU (microprocessor), memories (primary and secondary)
and I/O devices as shown in the block diagram in Fig 1. The memory and I/O devices are linked
by data and address (control) buses. The CPU communicates with only one peripheral at a time
by enabling the peripheral by the control signal. For example to send data to the output device,
the CPU places the device address on the address bus, data on the data bus and enables the
output device. The other peripherals that are not enabled remain in high impedance state called
tri-state.

Fig.1 Block diagram of a Microcomputer

Evolution of Microprocessors
The first Microprocessor (4004) was designed by Intel Corporation which was founded by
Moore and Noyce in 1968. In the early years, Intel focused on developing semiconductor
memories (DRAMs and EPROMs) for digital computers. In 1969, a Japanese Calculator
manufacturer, Busicom approached Intel with a design for a small calculator which need 12
custom chips. Ted Hoff, an Intel Engineer thought that a general purpose logic device could
replace the multiple components. This idea led to the development of the first so called
microprocessor. So, Microprocessors started with a modest beginning of drivers for calculators.
Fedrico Faggin and Stanely Mazor implemented the ideas of Ted Hoffs and designed the Intel
4000 family of processors comprising 4001 (2K-ROM), the 4002 (320 bit RAM), the 4003 (10 bit
I/O shift-register) and the 4004, a 4 bit CPU. Intel introduced the 4004 microprocessor to the
world wide market on November 15, 1971. It was a 4-bit PMOS chip with 2300 transistors.
Around the same time Texas Instruments developed a 4-bit microprocessor TMS 1000 and
became the owner of microprocessor patent. Later Intel introduced worlds first 8 bit general
purpose microprocessor 8008 in 1972. This processor was used in the popular computer Mark8 in those days. In 1974, Intel introduced the improved version of 8008, the 8080
microprocessor. This 8080 is the much more highly integrated chip than its predecessors which
is built around N-channel MOS technology. It could execute up to 290,000 operations per second

and could address up to 64K.bytes of memory. The other notable 8 bit microprocessors include
Motorola 6800, Rockwell PPS-8 and Signetics 2650 with powerful architecture and instruction
set.
With developments in integration technology Intel was able to integrate the additional chips like
8224 clock generator and the 8228 system controller along with 8080 microprocessor with in a
single chip and released the 8 bit microprocessor 8085 in the year 1976. The 8085
microprocessor consisted of 6500 MOS transistors and could work at clock frequencies of 3-5
MHz. It works on a single +5 volts supply. The other improved 8 bit microprocessors include
Motorola MC 6809, Zilog Z-80 and RCA COSMAC.
In 1978, Intel introduced the 16 bit microprocessor 8086 and 8088 in 1979. IBM selected
the Intel 8088 for their personal computer (IBM-PC).8086 microprocessor made up of 29,000
MOS transistors and could work at a clock speed of 5-10 MHz. It has a 16-bit ALU with 16-bit
data bus and 20-bit address bus. It can address up to 1MB of address space. The pipelining
concept was used for the first time to improve the speed of the processor. It had a pre-fetch
queue of 6 instructions where in the instructions to be executed were fetched during the
execution of an instruction. It means 8086 architecture supports parallel processing. The 8088
microprocessor is similar to 8086 processor in architecture ,but the basic difference is it has only
8-bit data bus even though the ALU is of 16-bit.It has a pre-fetch queue of 4-instructions only.
In 1982 Intel released another 16-bit processor called 80186 designed by a team under the
leadership of Dave Stamm. This is having higher reliability and faster operational speed but at a
lower cost. It had a pre-fetch queue of 6-instructions and it is suitable for high volume
applications such as computer workstations, word-processor and personal computers. It is made
up of 134,000 MOS transistors and could work at clock rates of 4 and 6 MHz. This is also comes
under first generation of Microprocessors.
Intel released another 16 bit microprocessor 80286 having 1, 34,000 transistors in 1981. It was
used as CPU in PC-ATs in 1982. It is the second generation microprocessor, more advanced to
80186 processor. It could run at clock speeds of 6 to 12.5 MHz .It has a 16-bit data bus and 24bit address bus, so that it can address up to 16MB of address space and 1GB of virtual memory.
It had a pre-fetch queue of 6 instructions .Intel introduced the concept of protected mode and
virtual mode to ensure proper operation. It also had on-chip memory management unit (MMU)
.This was popularly called as Intel 286 in those days.
In 1985, Intel released the first 32 bit processor 80386, with 275,000 transistors. It has 32bit data bus and 32-bit address bus so that it can address up to a total of 4GB memory also a
virtual memory space of 64TB.It could process five million instructions per second and could
work with all popular operating systems including Windows. It has a pre-fetch queue of length 16bytes with extensive memory management capabilities. It is incorporated with a concept called
paging in addition to segmentation technique. It uses a math co-processor called 80387.

Intel introduced 80486 microprocessor with a built-in maths co-processor and with 1.2
million transistors. It could run at the clock speed of 50 MHz This is also a 32 bit processor but it
is twice as fast as 80386.The additional features in 486 processor are the built-in Cache and
built-in math co-processors. The address bus here is bidirectional because of presence of cache
memory.
On 19th October, 1992, Intel released the Pentium-I Processor with 3.1 million transistors. So,
the Pentium began as fifth generation of the Intel x86 architecture. This Pentium was a backward
compatible while offering new features. The revolutionary technology followed is that the CPU is

able to execute two instruction at the same time. This is known as super scalar technology. The
Pentium uses a 32-bit expansion bus, however the data bus is 64 bits.
The 7.5 million transistors based chip, Intel Pentium II processor was released in 1997. It
works at a clock speed of 300M.Hz. Pentium II uses the Dynamic Execution Technology which
consists of three different facilities namely, Multiple branch prediction, Data flow analysis, and
Speculative execution unit. Another important feature is a thermal sensor located on the mother
board can monitor the die temperature of the processor. For thermal management applications.
Intel Celeron Processors were introduced in the year 1999. Pentium-III processor with 9.5 million
transistors was introduced in 1999. It also uses dynamic execution micro-architecture, a unique
combination of multiple branch prediction, dataflow analysis and speculative execution. The
Pentium III has improved MMX and processor serial number feature. The improved MMX
enables advanced imaging, 3D streaming audio and video, and speech recognition for enhanced
Internet facility.
Pentium-IV with 42 million transistors and 1.5 GHz clock speed was released by Intel in
November 2000. The Pentium 4 processor has a system bus with 3.2 G-bytes per second of
bandwidth. This high bandwidth is a key reason for applications that stream data from memory.
This bandwidth is achieved with 64 bit wide bus capable of transferring data at a rate of 400
MHz. The Pentium 4 processor enables real-time MPEG2 video encoding and near real-time
MPEG4 encoding, allowing efficient video editing and video conferencing.
Intel with partner Hewlett-Packard developed the next generation 64-bit processor architecture
called IA-64 .This first implementation was named Itanium. Itanium processor which is the first in
a family of 64 bit products was introduced in the year 2001.The Itanium processor was specially
designed to provide a very high level of parallel processing ,to enable high performance without
requiring very high clock frequencies .Key strengths of the Itanium architecture include ,up to 6
instructions/cycle. The Itanium processor can handle up to 6 simultaneous 64 bit instructions
per clock cycle.
The Itanium II is an IA-64 microprocessor developed jointly by Hewlett-Packard (HP)
and Intel and released on July 8,2002..It is theoretically capable of performing nearly 8 times
more work per clock cycle than other CISC and RISC architectures due to its parallel computing
micro-architecture. The recent Itanium processor features a split L2 cache, adding a dedicated
1MB L2 cache for instructions and thereby effectively growing the original 256KBL2 cache, which
becomes a dedicated data cache. The first Itanium 2 processor (code named McKinley) was
more powerful than the original Itanium processor, with approximately two times performance.
Pentium 4EE was released by Intel in the year 2003 and Pentium 4E was released in the
year 2004.
The Pentium Dual-Core brand was used for mainstream X86-architecture
microprocessors from Intel from 2006 to 2009 The 64 bit Intel Core2 was released on July
27,2006. In terms of features, price and performance at a given clock frequency, Pentium DualCore processors were positioned above Celeron but below Core and Core 2 microprocessors in
Intel's product range. The Pentium Dual-Core was also a very popular choice for over clocking,
as it can deliver optimal performance (when over clocked) at a low price.
The Pentium Dual Core, which consists of 167 million transistors was released on January 21,
2007. Intel Core Duo consists of two cores on one die, a 2 MB L2 cache shared by both cores,
and an arbiter bus that controls both L2 cache and FSB access.
Core 2 Quad processors are multi-chip modules consisting of two dies similar to those used in
Core 2 Duo, forming a quad-core processor. While this allows twice the performance to a dualcore processors at the same clock frequency in ideal conditions, this is highly workload specific
and requires applications to take advantage of the extra cores.

In September.2009, new Core i7 models based on the Lynnfield desktop quad-core processor
and the Clarksfield quad-core mobile were added, and models based on the Arrandale dual-core
mobile processor have been announced. The first six-core processor in the Core lineup is the
Gulftown, which was launched on March 16, 2010. Both the regular Core i7 and the Extreme
Edition are advertised as five stars in the Intel Processor Rating.
The Intel 8085 Microprocessor:
Intel 8085A is a single chip 8-bit N-channel microprocessor which works at +5V DC power
supply. It is a 40 pin IC available as a DIP (Dual Inline Package) chip. 8085A can operate with a
3MHZ single phase clock and 8085A-2 version can operate at a maximum frequency of 5MHZ.
This 8085 is an enhanced version of its predecessor the 8080A. Its instruction set is upward
compatible with that of the 8080A. 8085A has an on-chip clock generator with external crystal,
LC or RC network. This 8085 microprocessor is built with nearly 6200 transistors. The enhanced
version of 8080 is the Intel 8085AH. It is an N channel depletion load, silicon gate (HMOS) 8-bit
processor. Here 3MHZ, 5MHZ and 6MHZ selections are available. It has 20% lower power
consumption than 8085A for 3MHZ and 5MHZ. Its instruction set is 100% software compatible
with the 8085A. It is also 100% compatible with 8085A.

Central Processing Unit (CPU)

The Central Processing Unit of any microcomputer is the microprocessor. Hence
microprocessor is also known as the heart of the computer. The CPU performs the various
activities in response to a set of instructions called a program. Programs are stored in the
memory. The CPU reads in data control signals (instructions) through the input ports and
executes one instruction at a time. So, generally speaking, a microprocessor is nothing but the
CPU .The Intel 8085 CPU is an 8-bit device with a clock speed of 3 - 5 MHZ. It has 80 basic
instructions and 246 op-codes. Its clock cycle is 320 ns. The time for the clock cycle of Intel 8085
is 200 ns. The block diagram of 8085 microprocessor is shown in Fig 2. The 8085 CPU consists
of three major sections,
They are:
(i). Arithmetic and logic unit (ALU)
(ii).Registers
(iii).Timing and Control unit.

Arithmetic and logic unit (ALU)

The ALU performs all the arithmetic and logical operations like addition, subtraction,
complementing, logical AND, logical OR, logical Exclusive OR, incrementing and decrementing,
rotate, shift and clear. An ALU is made of many logic gates and adders etc.
The arithmetic and logic unit consists of the following units
(a).Accumulator (A).
(b).Temporary register.
(c).Flag register.
(a) Accumulator (A):
It is an 8-bit register which is treated as a special function register. Most of the arithmetic
and logic operations are performed using this accumulator. All the I/O data transfers between
8085 and I/O devices are performed via accumulator. One of the operands for arithmetic
operations in ALU is from the accumulator. After performing the arithmetic operations the result is
stored back in accumulator. It is from the accumulator only, the data is sent out to an output
device. Similarly, the data from an input device is read only through the accumulator. The data in
the accumulator alone can be rotated or shifted. No other register can be used for these
operations. Certain instructions like DAA are performed using only accumulator. So, many times
the Accumulator register is treated as a default register.

Figure 2 .The Block Diagram of 8085 Microprocessor

(b) Temporary register:
This is an 8-bit register which is not accessible to the user. This register is used by the
microprocessor to load the second operand during arithmetic/logical operations in ALU. The final
result is stored in the Accumulator and the flags are set or reset according to the result of the

operation. For example when MVI M, 17H instruction is fetched, IR register will receive the
opcode for MVI M and the Temporary register will receive 17H.
In arithmetic and logical operations, that involves two operands ,the accumulator provides one
operand. The other is provided by the temporary register. For example in ADD C instruction C
register contents are moved to the Temp. Register and the addition of A and Temp. Register
contents is performed by the ALU.
(c).Flag register: The flag register is an 8- bit register which generally reflect data conditions in
the accumulator with certain exceptions. Hence this flag register is also known as Status register.
Though this flag register is an eight bit register, it contains only 5 flag bits and the remaining
three bits are undefined as shown in Fig.3.3 In the Flag register each flag bit is a Flip-Flop. i.e.,
the bit may be either in the flip state or flop state

Figure 3. Flag Register

S - Sign Flag
After execution of an arithmetic and logic operation, if bit D7 of the result (Normally in the
Accumulator) is 1, the sign flag is set. This Flag is used with signed numbers.For example in a
given byte, if D7 is 1, the number is treated as a negative number. Else (if it is zero), it is viewed
as a positive. In arithmetic operations with signed numbers bit D7is reserved for indicating the
sign and the remaining seven bits are used to denote the magnitude of the number.
Z - Zero Flag
This Flag is set (made 1) if the result after any arithmetic operation is zero, and the flag is reset
(made 0) if the result is not zero. So, this flag is set or reset based on the results in the
accumulator as well as in the other registers.
AC Auxiliary carry Flag
In this arithmetic operation, when a carry is generated by and passed on to bit 4 , the AC flag is
set. This flag is used internally for BCD arithmetic and is not available for the programmer to
change the sequence of a program with a jump instruction. But the Z and CY flags can be used
for this purpose.
P-Parity Flag
If the result after an arithmetic and logical operation has an even number of 1s, this parity flag is
set to 1 otherwise (if number of 1s is odd) the flag is reset (made0).
For example the data byte 10111101 has even parity and the data byte 10011011 has odd parity.
So P bit=0.
CY-Carry flag
After an arithmetic operation, like addition, subtraction if there exists a carry or barrow, this flag
CY is set to 1 else it is reset (made0)
Example : Let us consider the addition of two binary numbers 11011001 and 11101101 and
check the Flag register.

D7
D0
11011001
11101101
11 1 0 0 0 1 1 0
In the result, the sum is not zero, So Z-Flag is reset (Z=0).
There is a carry from the third bit to fourth bit. So AC Flag is set (AC=1).
The D7 bit=1, so, the sign Flag is set (S=1).
In the result, the no. of 1s is even. So, parity is even (P=1).
After addition, there is a carry. So carry Flag is set (CY=1).
The Flag register contents after addition are shown below:
D7
D0

Register Organization
The 8085 microprocessor has different types of registers. It includes six , 8 bit registers
(B, C, D. E, H and L), one 8-bit Accumulator and two 16-bit registers (SP and PC). Also there
are two 8-bit temporary registers W and Z. Among these registers W and Z are not accessible to
the user, They are used by the processor for internal, intermediate operations. The remaining
registers are accessible to the user. The organization of 8085 registers is shown in Fig. 3.4
The various registers of 8085 are classified into three types. They are
(i).Temporary registers.
(ii).General purpose registers
(iii).Special purpose registers.
(i) Temporary registers :
The Temporary registers are temporary data registers, W register and Z register. All are 8bit registers. The temporary data register is associated with the ALU operations. One of the
operand is stored in this register. This is not accessible to user.
Similarly W and Z are also temporary registers used to hold 8-bit data during execution of certain
instructions.As these registers are internally used by the CPU, they are not accessible to the
user.
The W and Z registers are used by the processor during CALL instruction. When a CALL
instruction is encountered in any program, the current Program counter (PC) contents are
pushed on to the stack and the given address is loaded on to PC. The given address is
temporarily stored in W and Z registers and placed on the bus for the fetch cycle. Thus the
program control is transferred to the address given in the instruction.
Another example is, during the execution of XCHG instruction, the contents of H-L pair are
exchanged with D-E pair. At the time of exchange W and Z registers are used for temporary
storage of data.
(ii) General purpose registers :
B, C, D, E, H and L are six, 8-bit general purpose registers to store data. These registers
can be used as separate 8-bit registers and also can be paired as 16-bit registers to store the
address of a memory location. But they must be paired as B-C; D-E and H-L register pairs only
as shown below.

Figure 4. Register organization

When used as pair, for example B-C, the higher order byte moves to the first register (B) and the
low order byte moves to the second register (C). The H-L pair also functions as a data pointer or
memory pointer
For Ex: LXI H, 8500 H.
This will load immediately the address of memory location (8500H) in to H-L pair .Now the H-L
pair points to the location 8500 H.
(iii) Special purpose registers:
The Special purpose registers ,as their name indicates, are used for some specific
purpose. The Special purpose registers are Accumulator (A), Flag Register, Instruction
Register(IR), Program Counter (PC) and Stack Pointer (SP).
Accumulator (Register A): It is an 8-bit tri-state register. It is mainly used for arithmetic, logic, load
and store operations. It is also used in I/O operations. In most of operations, the result is stored
in Accumulator after execution.
Flag Register: It is an 8-bit register, Which consists of only five flags.Each flag bit is a flip flop that
indicates either a set or reset state. The five flags are Sign, Zero, Auxiliary carry, Parity and
Carry as shown below

Here X means undefined.

Sign Flag: The sign flag is set to1 if the most significant bit of the result of an arithmetic or logic
operations is 1. Else it is reset (0).
Zero Flag: The Zero status flag is set to 1 if the result of an arithmetic or logic operation is Zero
For non-Zero result it is reset to 0.G

Auxiliary carry Flag: This flag is set if there is a carry from 3rd bit to 4th bit during BCD
operations (carry from lower nibble to higher nibble). This flag is not accessible to the user.
Parity Flag: Parity is defined by the number of 1s present in a binary number stored in A
register. After any arithmetic or logical operation, if the result has an even number of 1s it is
called even parity and the Parity Flag is set to 1. Otherwise. i.e. If there is odd number of 1s in
the result, it is called Odd Parity and the Parity flag is set 0.
Program Counter (PC):
It is a 16-bit special purpose register, which stores the address of the next instruction to be
fetched or executed. The execution of a program is initiated by loading the PC by the address of
the first instruction of the program. Once the first instruction is executed, the PC is automatically
incremented to point to the next instruction unless a jump to some specific address occurs. This
process is repeated till the last instruction of the program.
In case of JUMP or CALL instructions, current address is stored in the Program Counter.
The processor then fetches the next instruction from the new address specified by the JUMP or
CALL instruction. In conditional JUMP and conditional CALL instructions, if the condition is not
satisfied, the processor increments the Program Counter by three so that it points the instruction
followed by the conditional JUMP or CALL instruction. Otherwise the processor fetches the next
instruction from the new address specified by JUMP or CALL instruction.
Stack Pointer (SP):
It is a 16-bit special purpose register which always stores the address of top of the Stack.
i.e. it always points to top of the Stack. Stack is a part of the memory location used to store the
data temporarily. A stack works on Last in First out (LIFO) basis. As the Stack pointer always
points to the top of the Stack, only top of the Stack of the memory can be accessed. When a
Write operation (PUSH) takes place, the contents of the stack pointer is decremented by two so
that the SP points to the new location. Similarly when the Read operation (POP) occurs, the
Stack pointer is incremented by two to point to the next data on top of the Stack.
The Stack Pointer is initialized by load register pair immediate instruction.
Ex: LXI SP, 8530 H
Here 8530 H is the 16 bit address of the top of Stack location.

The remaining blocks of 8085 microprocessor block diagram

Instruction Register and Decoder: The instruction register and the decoder are also part of the
ALU. When an instruction is fetched from memory, it is loaded in the instruction register. The
Decoder decodes the instruction and develops the sequence of events to follow. The instruction
register is a 8 bit special register, but it is not a programmable and is not accessible to the user.
The instruction decoder decodes the instruction at a binary level and sends the appropriate
signals to the control unit.
Increment/ Decrement Address Latch: This is a 16 bit special register not accessible to the
user. This register is used by the CPU to increment/ decrement the contents of the Stack Pointer
(SP) and increment program counter (PC) during instruction execution. During first T - state of op
code fetch machine cycle (T1) the microprocessor increments the PC register contents to point to
the next location. This increment operation takes place on increment/ decrement register address
latch. The 16 bit address that is sent out through AD0-AD7 and A8-A15 are latched into this
register. The address bus AD0-AD7 continues to be available on the bus after T1 state from this
latch.

Address Buffer: This is an 8-bit unidirectional buffer. It is used to drive external higher order
address bus. It is also used to tri-state the higher order address (A8-A15) bus under certain
conditions like reset, hold, and halt and also when address lines are not in use.
Address/Data Buffer: This is an 8-bit bi-directional buffer. It is used to drive multiplexed
address/data bus. It means low order address bus (A7-A0) and data bus (D7-D0). It is also used
to tri-state the multiplexed address/data bus under certain conditions like reset, hold, and halt
and also when A/D bus lines are not in use.
The address and data bus buffers are used to drive external address and data buses
respectively. Due to these buffers the address and data buffers can be tri-stated when they are
not in use. In actual practice, in a microprocessor the driving capacity of the address pins after
the internal buffering may not be adequate. So, there will be external buffer chips also available.
Serial I/O control:
This control provides two lines SOD (Serial Out Data) and SID (serial In Data) for serial
communication. These lines are used during serial data transmission over long distance where
data is transmitted and received bit by bit. The Serial Output Data (SOD) pin is used to send
data out serially and serial Input Data (SID) pin is used to receive data serially by the 8085
microprocessor.
Interrupt control:
This is an important block related to interrupts. This block is linked to the CPU through the
8-bit internal data bus. This interrupt control has five interrupt signals. They are TRAP, RST 7.5,
RST 6.5, RST 5.5 and INTR. The control block will take care of enabling and disabling of these
interrupts etc

8085 Interrupts:
The 8085 microprocessor has five interrupts. They are TRAP, RST 7.5, RST 6.5, RST5.5 and
INTR. Among all these interrupts TRAP has the highest priority and INTR (Interrupt Request) has
the lowest priority. The TRAP is also a non maskable interrupt. The numbers succeeding the
RST (7.5, 6.5, and 5.5) are related to the call locations. The various interrupts, their locations in
the order of highest to lowest priority are given in Table 3.1. Here RST means RESTART. Among
these interrupts INTR is the only non-vector interrupt whereas the other interrupts are vectored
interrupts.
TRAP: It is a non maskable interrupt with highest priority. It means that whenever the pin is
activated, the 8085 will always get interrupted even if the 8085 is in DI (Disable Interrupt) state.
Trap input is both edge and level sensitive. So, the microprocessor is interrupted when the input
is both edge and level sensitive. So, the microprocessor is interrupted when the input pulse goes
from low to high or when it remains high .When interrupted, the microprocessor loads the
program counter with 0024H.
RST 7.5: It is an edge sensitive pin. Internal to 8085 there is a flip-flop connected to RST 7.5
interrupt pin . This flip flop is set 1, when a positive going edge occurs on RST 7.5 input. RST
7.5 interrupt has a higher priority than RST 6.5, RST 5.5 and INTR. This RST 7.5 is a maskable
interrupt known as MI. This interrupt is enabled under program control with two instructions EI
(Enable Interrupt) and SIM (Set Interrupt Mask)
RST 6.5and RST 5.5: These interrupts are level sensitive, it means the triggering level should
be on until the microprocessor completes the execution of the current instruction. If the
microprocessor is not able to respond to the requests immediately, they should be stored or held
by external hardware. These two interrupts are also maskable interrupts. RST 6.5 and RST 5.5
have higher priority than INTR interrupt. The condition of these interrupts can be known using

10

RIM (Read Interrupt Mask) instruction and the condition of the masking interrupt can be set and
reset using SIM instruction (Set Interrupt Mask).
INTR: It is only non-vectored interrupt in 8085 microprocessor. This interrupt has the lowest
priority among all the interrupts. This is also a maskable interrupt and can be disabled using the
instruction DI (Disable Interrupt). The mask on INTR can be removed by executing EI (Enable
Interrupt) instruction. When EI instruction is executed, the flip flop associated with this is set and
the mask is removed. This is a non-vectored interrupt because when the remaining interrupts are
initialized, they are automatically transferred (vectored) to specific locations on memory page
00H without any external hardware. They do not require the
signal. The necessary
hardware is already implemented inside the 8085. But coming to INTR, interrupt, it executes
interrupt acknowledge machine cycle. During this cycle, the device that has interrupted this
microprocessor will provide the operation code. The
signal works as a
signal during
acknowledge machine cycle. During this time, the microprocessor loads the code into instruction
register from I/O device. Based on the code, the remaining operation is executed by the
processor
S.N o

Interrupts

Call locations

TRAP (Highest priority)

0024H

RST 7.5

(7.5 x 8)H = 003CH

RST 6.5

(6.5 x 8)H = 0034H

RST 5.5

(5.5 x 8)H = 002CH

INTR (least priority)

No location

Table 1 . Various Interrupts ,Call locations in order of highest to lowest priority

Timing and control Unit

This unit of the microprocessor issues necessary timing and control signals for the
execution of instructions. It generates three types of signals namely status, control and timing
signals required for the operation of memory and I/O devices. This unit with the help of these
signals controls the entire operation of the microprocessor and the peripherals. The signals
associated with this unit are two control signals.
and
three status signals IO/ , S1 and
S0 to identify the nature of the operation and one special signal ALE which indicates the starting
of the operation. These signals are explained below in detail.
-Read (active low): This is a Read control signal. This signal indicates that the selected I/O or
memory device is to be read and data are available on the data bus.
- Write (active low): This is a Write control signal. This signal indicates that the data on the
data bus are to be written into a selected memory or I/O device.

S. No

S1

IO/

S0

Status

Memory Write

Memory Read

11

I/O Write

I/O Read

1/0

Opcode fetch

Interrupt
Acknowledge
Halt

Hold

RESET

Table 2. Status signals of 8085

IO/ : This is a status signal used to differentiate between I/O and memory operations. When
this signal is high, it indicates an I/O operation, when it is low it denotes a memory operation.
This signal is combined with Read ( ) and Write
to generate necessary I/O and memory
control signals.
S1 and S0: These signals are also status signals like IO/ , used to identify various operations.
The complete operation of the microprocessor can be understood by these three signals. The
various operations and the associated status signals are shown in Table 3.2 .
ALE (Address Latch Enable): This is a positive going pulse generated every time the 8085
begins an operation, It indicates that the bits on AD7 - AD0 are address bits. This signal is used
primarily to latch the low-order address from the multiplexed bus and generate a set of eight
address lines A7 A0.

Address, Data and Control Buses:

Intel 8085 has 16-bit unidirectional address bus which carries the address of memories
and peripheral devices. A bus is nothing but a group of electrical lines used to transmit the
information as electrical signals. So, this 16-bit parallel address bus carries address from
microprocessor to memories/peripherals. Hence it is Uni-directional(because the converse is not
possible). The width of the parallel bus determines how much memory that a microprocessor can
address.The 8085 microprocessor with 16-bit address bus can address a maximum of 216=
65536=64 KB of memory locations. The size of the address bus is independent of the size of the
microprocessor.
In INTEL 8085 microprocessor, the 8 most significant bits of the address are transmitted
by the high order address bus A8-A15. But the 8 least significant bits of the addresses are
transmitted by Address/Data bus or A/D bus. i.e. the lower order address lines are multiplexed
with the data bus. So, the A/D bus operates in a time shared mode. i.e. the data and address are
sent on the same lines but at different instants of time. A0-A7 will always have the address during

12

the first T state (T1) of the machine cycle. To demultiplexe the A/D bus the pin ALE is used.
When ALE=1 (high) the A/D bus acts as a lower order address bus else it acts as Data bus.
The Data bus is a bidirectional bus which is used to send data to and from the microprocessor.
This is also a parallel bus. The size of the data bus determines the size of the microprocessor.
The 8085 microprocessor has 8-bit data bus and hence it is called an 8-bit microprocessor. This
refers to the width of the data bus but not the address bus. Similarly8086 is a 16-bit
microprocessor and its data bus width is 16 bits
INTEL 8085 has Address/ Data bus namely AD7-AD0. i.e. at some instances it acts as a
8- bit address bus and at other instances it works as a 8-bit data bus. INTEL used this time
multiplexing technique to save the pins. Generally the size of the internal general purpose
registers matches the size of the data bus. Thus, the INTELs 8-bit general purpose registers
matches with its 8-bit data bus. The size of the data bus matches the size of the internal
registers, so that all the bits on the bus can at one time come into or go out of any of the
registers.
The control bus of 8085 is a uni-directional bus because the microprocessor alone sends
control signals to memories or peripheral devices. The size of the control bus depends upon the
specific microprocessor. Typical control signals are Read or Write signals. It means whether the
microprocessor operation is a read or writes and whether it is memory or I/O operation. In
addition to this it includes state signals, and address latch enables. A microprocessor may also
have certain additional control signals and such as interrupt signals, acknowledgement signals
and hold signals. But they are not considered as part of control bus even through they take part
in control of microprocessor based systems.
The above three buses that interface the CPU to the system components are combinedly
known as the System bus.

Pin configuration
The pin diagram of 8085 microprocessor is shown in Fig 5. From the figure it is clear that it is
40 pin DIP chip. The various pins of 8085 microprocessor can be grouped in the following
categories
Power Supply and Clock pins
Data bus and Address bus
Control and Status signals
Interrupt signals
DMA signals
Serial I/O signals
The description of various pins is given below.
Power supply and clock pins:
Vcc: +5V power supply

Vss: Ground reference.

X1 and X2: A Crystal (or RC, LC Network) is connected at these two pins. The internal
clock generator divides oscillator frequency by 2, therefore to operate a system at 3MHZ,
the crystal of the tuned circuit should have a frequency of 6MHZ.

CLK (OUT): This signal is used as a system clock for other devices. Its frequency is half
the oscillator frequency

Data bus and Address bus:

13

 AD0-AD7: These lines are Address/Data lines, which are bidirectional with dual purpose.
They are used as the low-order address bus as well as the data bus. During the first part
of the machine cycle (T1), lower 8 bits of memory address or I/O address appear on the
bus. During the remaining part of the machine cycle (T2,T3) these lines are used as a bidirectional data bus

Figure 5. Pin Diagram of 8085 A

A8-A0: These are the upper half of the 16 bit address lines. These lines are exclusively
used for the most significant 8 bits of the 16 bits of the16 bit address bus.

Control and Status Signals:

ALE (Address Latch Enable): This is a positive going pulse generated every time the
8085 begins an operation. The ALE=High indicates that the bits on AD7-AD0 are address
bits. This signal is mainly used to latch the low order address from the multiplexed bus
and generate a separate set of eight address lines (A7-A0)

(Read): This is an active low read control pin. This signal indicates that the selected
I/O or memory device is to be read and data are available on data bus.

(Write): This is an active low write control pin. It indicates that the data on the data
on the data bus are to be are to be written into a selected memory or I/O location

IO/ : This is a status signal used to differentiate between IO and memory operations.
When it is high, it indicates an I/O operation and when it is low, it indicates a memory
operation. This signal is combined with
and
signals to generate I/O and memory
control signals.

14

S1 and S0: These are status signals and they indicate the type of machine cycle in
progress during execution of an instruction.

READY (Input): Through this pin, the microprocessor will know whether peripheral device
is ready or not for data transfer. If the device is not ready the processor waits. So, this pin
helps to synchronize slow devices to the microprocessor.

Interrupt signals:
TRAP, RST 7.5, RST 6.5, RST5.5 and INTR: These are the interrupt signals which are externally
initiated.

INTR (Interrupt Request): This is used as a general purpose interrupt. It has a lowest
priority and it is the only non-vectored interrupt.

RST 7.5: It is a restart interrupt pin. It has higher priority than RST 6.5, RST5.5 and INTR.
It is a maskable vectored interrupt.

RST 6.5 and RST5.5: These two are maskable vectored interrupt with higher priority than
INTR.

TRAP: It is a non-maskable vectored interrupt. It has higher priority.

(Output): It is an active low interrupt acknowledge pin. This will acknowledge the
receival of interrupt request to the peripheral device.

DMA Signals:
Hold: This pin is used during the Direct Memory Access. A high on this pin indicates that,
a peripheral like DMA controller is requesting the use of address and data buses.

HLDA (Output): A high on this p in acknowledges the hold request from peripheral.

: It is an active low signal. When the signal on this pin goes low, the system is in
reset i.e. the program counter is set to zero, the address & data buses are tristated.

RESETOUT: This signal is used to Reset other devices in microprocessor system.

Serial input/ Output signals:

SID: Serial input Data is a pin through which serial data are brought into the micro
processor accumulator after the RIM instruction is executed.

SOD: Serial output Data pin is used by the microprocessor to output data serially to the
external devices. Serial data is sent out of the microprocessor by executing SIM
instruction. The most significant bit of accumulator should have the serial bit and D6 bit of
the accumulator must be made high to enable the serial data transfer.

Timing Diagram :
The graphical representation of the time taken for the execution of each instruction by a
microprocessor is known as timing diagram. The execution time is denoted by T-states. One Tstate is equal to the time period of the internal clock signal of the microprocessor
For Ex: If the internal clock frequency of 8085 microprocessor is 3 MHZ, One T-state is equal to

15

=0.333x10-6sec=333x10-9sec. (333 nano seconds nearly)

As far as execution of instructions is concerned, in 8085 microprocessor, each instruction is

divided into two parts: The operation code (opcode) and the operand. The opcode tells us what
the operation is and the operand is the necessary information required for the instruction. The
operand may be either data or an address or other information required for the instruction.
Each instruction is divided into machine cycles and each machine cycle is divided into clock
cycles or T- states
The first machine cycle is every instruction is the op-code fetch. During this time the
opcode is fetched from memory and returned on the data bus to the microprocessor. The 8085
machine cycles are divided into following six types. They are
1. Opcode fetch
2. Memory read
3. Memory write
4. I/O read
5. I/O write
6. Interrupt acknowledge

Opcode fetch Machine cycle:

The first operation in every instruction is the opcode fetch. The opcode fetch cycle is
called the M1 machine cycle and is usually for four T-states or clock cycles (certain instructions
may also have 6T states in their opcode fetch machine cycle). During T1-T3 states the address is
placed on the address bus and the opcode is returned on the data bus. The T4-state is used to
decode and execute the opcode. The next machine cycles (M2, M3------) that follow depend upon
what the instruction actually is.
The timing diagram for execution of MVI A, 25 machine cycle is shown in Fig 6 as shown in the
timing diagram, in T1 state, the 8085 places the contents of the program counter o n the address
bus. The high order byte of the P.C (80) is placed on the A8-A15 lines. The low-order byte of the
P.C(00) is placed on the AD0-AD7 line which stays only on only during T1. So, the microprocessor
activates the ALE (Address Latch Enable) pin which is used to latch the low-order byte of the
address in external latch before it vanishes. During T1 state, 8085 also sends status signals
IO/ , S1 and S0. The IO/ signal specifies whether the operation is read or write. In opcode
fetch machine cycle status signals are IO/ =0, S1 =1 and S0=0
In T2 state, the lower order address disappears from AD0-AD7 lines and 8085 sends
signal
low to enable the addressed memory location. The memory device then places the contents of
the addressed memory location on the data bus (AD0-AD7)
During T3 state, the microprocessor loads the data from the data bus in its instruction register
and raises
to high which disables the memory device
In T4 state, the microprocessor decodes the opcode and based on the instruction it decides
whether to T0 state T5 or to enter state T1of the next machine cycle (M2). All the one byte
instructions which operate on 8-bit data like MOV A, B, ADDB, DCRC, RAL etc..are executed
T4 state. One byte instructions which operate on 16-bit data are executed in T5 and T6 states.
For example: INXH, SPHL, 5DCXH etc.

16

Figure 6 Timing diagram for Opcode fetch Machine cycle

Memory Read cycle:

Memory read machine cycle is a machine cycle during which memory is read. For
example, the instruction LDA 8900H which is a 3-byte instruction has three memory read cycles
immediately after the opcode fetch cycle. The first two cycles are to get the memory address, in
two 8-bit groups (the low-order part of the address and then the high-order address). The third
read cycle is needed to read the data located at the address previously retrieved. This data is
then loaded into accumulator.
The timing diagram for memory read cycle [For Ex: LDA 2020H] is shown in Fig 7. As shown in
the memory read timing diagram, after the opcode fetch cycle, the first two read cycles have the
address going out over the address bus first for the low-order of the address (2001H) and then
for the high-order of the address(2002H). In the third read cycle, the address of the instruction
just read from memory (2020H) is sent back over the address bus in T1 and then data from that
memory location is returned over the data bus in T2-T3. IO/ goes low at the beginning of the
opcode fetch cycle and remains low during the next three cycles.
, on the other hand goes
low each time data on the data bus is to be read into the microprocessor.

17

Figure 7. Timing diagram for Memory Read machine cycle

Memory Write cycle:
This memory write cycle is used when the microprocessor needs to send data out from
accumulator or specific register and then write into the memory. As an example let us consider
the instruction MOV M, A (50H). This instruction requires two machine cycles-an opcode fetch
machine cycle followed by one write cycle. Because, after fetching the opcode, the instruction
has to write the data in the accumulator out to memory at the address location in the H-L register.
This operation requires 7-T states for opcode fetch and three T states for the memory write.

18

Figure 8 .Timing diagram for Memory Write machine cycle

The timing diagram of the instruction MOV A, M is shown in Fig .8. The opcode fetch cycle
shows the address [2000H] going out over the address bus and the opcode for the MOV M,A
(50H) returning over the data bus. During the write cycle (M2), the address that was stored in the
H-L pair goes out from the microprocessor during T1 and data to be written from the accumulator
goes out during T2-T3. The remaining signals like ALE, IO/ ,
and
have their usual
meaning as shown in the timing diagram.
I/O Read cycle:
This I/O read cycle occurs when the microprocessor executes IN instruction and during
the I/O read cycle, data is read in from an I/O device. In the case of IN PORT, there are three
machine cycles. The opcode fetch cycle, a memory read cycle and an I/O read cycle. The three
machine cycles combinedly taken 10-states.
The Fig 9. shows the timing diagram of the instruction IN 80H, Here 80H is the port address of
the device being read.
The opcode fetch cycle shows the address of the instruction (2000H) going out over t he address
bus and the opcode (DBH) for the IN instruction returning on the data bus. The memory read
cycle (M2) displays the address of the second byte of the instruction (8001H) going out over the
address bus and the port address (80H) returning on the data bus. During the I/O read cycle, the
port address of the device being read is sent over the address bus and the lower 8-bits carry the
same 8-bit port address and the data from the input device is returned on the data bus during T2T3.

19

Figure 9. Timing diagram for I/O Read machine cycle

I/O write cycle:
During this I/O write cycle DATA is written into I/O device specified by the port address
from the accumulator. The out port instruction has three machine cycles. The first one is opcode
fetch cycle, second one is memory read to get the port address and the third cycle is an I/O write
cycle. The OUT command writes the data stored in the accumulator over the data bus to the
device whose port address was sent out over the address bus. The three machine cycle that
forms the outport command has a total of ten T-states. The Fig 10 Shows the timing diagram for
OUT 04H instruction. 04H is the address of the output device
The opcode fetch cycle sends the address of the instruction (2000H) over the address bus while
the opcode (D3H) for the OUT instruction is returns on the data bus. The second machine cycle
shows the address of the second byte of the instruction (2001H) going out over the address bus
with the port address (84H) returning over the data bus.
From the timing diagram it is clear that, In the third machine cycle the port address (84H) is sent
out over both the upper and lower parts of the address bus, similar to I/O read cycle whenever
the microprocessor addresses an I/O device, the port address of the device being read is sent
out over both the lower and higher order parts of the address bus.
It is also to be noted that the data in the accumulator is being written to the output device and
goes out over the data bus during T2 -T3 states after the port address has been sent over the two
parts of the address bus during T1 of the I/O write cycle

20

Figure 10 Timing diagram for I/O Write machine cycle

Interrupt Acknowledge
This Interrupt acknowledge machine cycle is a special machine cycle that is used in place
of opcode fetch cycle in the RST (restart) instruction. It is same as an opcode fetch except that it
0sends out an
signal instead of an
signal and the status lines IO/ , S0 and S1 are 111
instead 011. Another difference is, the interrupt acknowledge is six-T states whereas opcode
fetch is only four T-states

Instruction cycle, Machine cycle, fetch and execute cycles

Instruction cycle
An instruction is a command given to the microprocessor to perform a specific operation
on the given data. Sequence of instructions written for a processor to perform a particular task is
called a program. Program & data are stored in the memory. The microprocessor fetches one
instruction from the memory at a time & executes it. It executes all the instructions of the program
one by one to produce the final result. The necessary steps that a microprocessor carries out to
fetch an instruction & necessary data from the memory & to execute it constitute an instruction
cycle.
In other words, an instruction cycle is defined as the time required completing the execution of an
instruction.
An instruction cycle consists of a fetch cycle and an execute cycle. The time required to fetch an
opcode (fetch cycle) is a fixed slot of time while the time required to execute an instruction
(execute cycle) is variable which depends on the type of instruction to be executed.

21

Instruction cycle(IC) = Fetch cycle(FC) + Execute cycle(EC)

This is shown diagrammatically in the Fig.3.11

Figure 11 Instruction cycle

Machine cycle:
Machine cycle is defined as the time required for completing the operation of accessing
either memory or I/O device. In the 8085, the machine cycle may consist of three to six T states.
The T-state is defined as one sub-division of the operation performed in one clock period. These
sub-divisions are internal states synchronized with the system clock.In every machine cycle the
first operation is op-code fetch and the remaining will be read or write from memory or IO
devices.
Fetch operation:
The first byte of an instruction is its op-code. An instruction may be more than one byte
long. The other bytes are data or operand address. The program counter (PC) keeps the
memory address of the next instruction to be executed. In the beginning of a fetch cycle the
content of the program counter, which is the address of the memory location where op-code is
available, is sent to the memory. The memory places the op-code on the data bus so as to
transfer it to the microprocessor. The entire operation of fetching an op-code takes three clock
cycles.
Execute operation:
The op-code fetched from the memory goes to the instruction register (IR). From the
instruction register it goes to the decoder circuitry which decodes the instruction. After the
instruction is decoded, execution begins. If the operand is in general purpose registers execution
is immediately performed.
The time taken for decoding and execution is one clock cycle. If an instruction contains data or
operand and address which are still in the memory, the microprocessor has to perform some
read operations to get the desired data. After receiving the data it performs execute operation. A
read cycle is similar to a fetch cycle. In case of a read cycle the quantity received from the
memory are data or operand address instead of an op-code. In some instructions write operation
is performed. In write cycle data are sent from the microprocessor to the memory or an output
device. Thus we see that in some cases an execute cycle may involve one or more read or write
cycles or both.

Instruction set of 8085

An Instruction is a command given to the microprocessor to perform a given task
on specified data. Each instruction has two parts one is the task to be performed called the
operation code (op-code) and the second is the data to be operated on, known as operand. The
operand or data can be specified in various ways.

22

Instruction and data formats:

The format of a typical instruction is composed of two parts: an operation code or op-code
and an operand. Every instruction needs an op-code to specify what the operation of the
instruction is and then an operand that gives the appropriate data needed for that particular
operation code.
According to the word or byte size the 8085 instructions are classified into three types.
They are
(a) One byte (single) instructions.
(b)Two byte instructions.
(c) Three byte instructions.
Onebyte instructions: An instruction with only opcode and do not require any dat or address is
called a one byte instruction.
Ex: 1. MOV C, A
2. ADD B
3. CMA

Hex code = 4FH (one byte)

Hex code = 80H (one byte)
Hex code = 2FH (one byte)

Twobyte instructions: At wo byte instruction is one which contains an 8-bit op-code and 8-bit
operand (Data).
Ex: 1. MVI A, 09
2. ADD B, 07
3. SUB A, 05

Hex code = 3E, 09 (two bytes)

Hex code = 80, 07 (two bytes)
Hex code = 97, 05 (two bytes)

Threebyte instructions: A three byte instruction contains an opcode plus a 16 bit address.
Ex: 1.LXI H, 8509
2 .LDA 8509
3. JMP 9567
4. STA 3525

Hex code = 21, 09, 85 (Three bytes)

Hex code = 3A, 09, 85 (Three bytes)
Hex code = C3, 67, 95 (Three bytes)
Hex code = 32, 35, 25 (Three bytes)

DATA FORMATS: The 8085 is an 8-bit microprocessor which process only binary numbers. But
it is very difficult to understand these binary numbers by a common user. So, we have to code
these binary numbers into different data formats. The commonly known data formats are ASCII,
BCD, signed integers and unsigned integers. The ASCII code is a 7-bit alpha-numeric code that
represents decimal numbers, English alphabets and certain special characters. The ASCII
stands for American Standard code for Information Interchange
The term BCD stands for binary coded decimal, used for decimal numbers from 0-9.An 8bit register can store two BCD numbers. A signed integer is either a positive or a negative
number. In 8085 microprocessor the most significant bit D7 is used for the sign. Here 0 denotes
positive sign and 1 denotes the negative sign. An integer without a sign can be represented by all
the 8-bits in a microprocessor register. So, the largest number that can be processed at one time
is FFH. The numbers larger than 8-bits like 16, 24, 32 bits can be processed by dividing them in
groups of 8-bits.

CLASSIFICATION OF INSTRUCTIONS
An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. The 8085 microprocessor instruction set has 74 operation codes
that result in 246 instructions. This instruction set includes all the 8080A instructions plus two
additional instructions namely SIM and RIM.

23

The instruction set of 8085 microprocessor is classified into five groups. They are:
1. Data transfer (copy) group.
2. Arithmetic group
3. Logic group
4. Branch control group
5. Machine control and I/O group.
Data transfer (copy) instructions
The data transfer instructions are used to transfer data from one register to another
register, from memory to register or register to memory but not from one memory location to
another memory location. Actually this data transfer instruction copies the data from source to
destination and the contents of the source are not altered. So, the data transfer instruction
performs basically copy operation.
Examples of data transfer instructions are MOV, MVI (Move Immediate), LXI (Load Immediate HL Pair), LDA (Load Accumulator), STA (Store Accumulator), LHLD (Load H-L pair direct), SHLD
(Store H-L pair direct), XCHG (Exchange the contents of H-L pair with D-E pair) etc
Ex: MVI A, 55H ; Move the data 55H into Accumulator
MOV B, C ; Copies the contents of C register into B register
IN 00H
; Read the Input port(00H is the port address)
OUT 01H ; write data to an output port(01H is the port address)
LXIH 8570H ; Load H-L pair by address 8570H.
In the 8085 microprocessor, data transfer instructions do not affect any flags.
Arithmetic Instructions
The arithmetic operations like addition, subtraction, increment and decrement are
performed by the 8085 microprocessor using the following arithmetic instructions.
ADD, ADI (Add Immediate), SUB (Subtract), SUI (Subtract Immediate), INR (Increment), DCR
(Decrement) etc
The arithmetic operations Add and subtract are performed in relation to the
contents of the accumulator. But, the increment or the decrement operations can be performed in
any register.
Ex:ADD B, C
ADI 08
SUB A, B
SUI 05
INR B
DCR C

; Add the contents of B register to the B register contents

; Add the data 08 to the accumulator.
; Subtract the contents of B register from accumulator.
;Subtract immediate the 8-bit data from accumulator
; Increment the B register contents by one bit
; Decrement the C register contents by one bit.

Arithmetic instructions modify all the flags according to the data conditions of the result. The INR
and DCR instructions affect all flags except the carry flag.
Logical Group of Instructions:
Since the microprocessor is a programmable logic chip, it can be perform all the logic
functions of the hard-wired logic through its instruction set. The 8085 processor can perform the
logic instructions like, AND, OR, NOT (Complement) and X-OR (Exclusive OR) etc The
mnemonics of these instructions are given below.

ANA :
ANI :

Logically AND the contents of a register

Logically AND immediate the 8-bit data.

24

ORA :
OR :
XRA :
XRI :
CMA :

Logically OR the contents of a register.

Logically OR immediate the 8-bit data.
Exclusive-OR the contents of a register.
Immediate Exclusive-OR the 8-bit data
Complement the accumulator

All the logic operations are performed in relation to the contents of the accumulator. The CMA
instruction does not affect any flags. The executions of the logical instruction do not affect the
contents of the operand register.
Branch Instructions
These instructions are very important because they allow the microprocessor to change
the sequence of a program either conditionally or unconditionally. The conditional branch
instructions transfer the program to the specified label when certain condition is satisfied. The
unconditional branch instructions transfer the program to the specified location unconditionally.
We know that the microprocessor is a sequential machine. So, it executes machine codes from
one memory location to the next. Branch instructions instruct the microprocessor to go to a
different memory location and the processor continues executing machine codes from the new
location. The address of the new locations either specified explicitly or provided by the
microprocessor or some times by additional hardware. The Branch instructions are classified into
three categories. They are
(a). Jump instructions
(b). Call and return instructions
(c). Restart instructions.
Jump instructions specify memory locations explicitly and they are 3-byte instructions. These
Jump instructions are of two types. They are , Unconditional Jump and Conditional Jump.
Unconditional Jump:
This is similar to Unconditional Go to statement in BASIC. When this instruction is
executed the 16-bit address available immediately in the instruction is loaded into the program
counter , so that the next sequence of instruction execution starts from this location. This
Unconditional Jump instruction enables the programmer to create continuous loops.
JMP (16 bit address). So, this is a 3-byte instruction where the first byte is opcode and the second, third bytes specify memory address.
For example, the instruction JMP 8500H, instructs the microprocessor to go to the memory
location8500H unconditionally. Sometimes, the jump location is specified using a label also.
Conditional Jump:
This instruction allows the microprocessor to make decision depending on certain
conditions indicated by flags. The 8085 processor Jump instruction is associated with four flags.
Namely Carry flag (CY), Zero flag (Z), Sign flag (S) and Parity flag (P). The following instructions
shown in Table 3.3 transfer the program sequence to the memory location specified under the
given conditions.

25

S. No

Instruction

Description

JC (16 bit Addr)

Jump on carry (if CY=1)

JNC (16 bit Addr)

Jump on no carry (if CY=0)

JZ (16 bit Addr)

Jump on Zero (if Z=1)

JNZ (16 bit Addr)

Jump on no Zero (if Z=0)

JP (16 bit Addr)

Jump on plus (if D7=0; S=0)

JM (16 bit Addr)

Jump on minus (if D7=1; S=1)

JPE (16 bit Addr)

Jump on Even Parity (if P=1)

JPO (16 bit Addr)

Jump on Odd Parity (if P=0)

Table 3 various conditional jump instructions

To understand the instructions, let us consider the instruction JC (16 bit address). The meaning
of this instruction is, the microprocessor is instructed to jump the specified 16 bit memory location
if there exists a carry after the arithmetic operation else it will execute the next instruction in the
sequence.
CALL and RETURN Instructions
The microprocessor uses the two instructions CALL and RETURN to implement
subroutines. Here CALL instruction calls a subroutine program which is not a part of the main
program and the RET instruction at the end of the subroutine program to return the control to the
main program.
Ex: CALL (16 bit memory address)
RET
RESET (RST) Instruction
The 8085 processor provides eight RST instructions to transfer the program control to a specific
location on page 00H. These instructions are 1-byte instructions. The various RST instructions
and their call locations are given in the following Table 3.4
S. No

Mnemonics

Hex code

RST 0

C7

Call location
In Hex
0000

RST1

CF

0008

RST2

D7

0010

RST3

DF

0018

RST4

E7

0020

RST5

EF

0028

RST6

F7

0030

RST7

FF

0038

Table 4 Various RST instructions and their call locations

26

Machine control and I/O Instructions

There are six basic machine control instructions. They are
EI (Enable Interrupt)
DI (Disable Interrupt)
NOP (No Operation)
SIM (Set Interrupt Mask)
RIM (Read Interrupt Mask)
HLT (Halt)
EI (Enable Interrupt): This is a one byte instruction used to enable the interrupt. This instruction
is used to enable the interrupts when the microprocessor is reset or the interrupt enable flag is
reset after interrupt acknowledge. This instruction takes one machine cycle with four states. The
op-code is FBH.
DI (Disable Interrupt): This is a one byte instruction which resets the interrupt enable flag to
disable all the interrupts except TRAP. It takes one machine cycle with four states. The op-code
is F3H.
NOP (No Operation): when this instruction is executed, the microprocessor performs nothing.
Microprocessor spends four states doing nothing. It is a one byte instruction whose op-code is
00H.This instruction is normally used to generate very small time delays of the order of few micro
seconds. This NOP instruction is also very useful when we are required to insert a few
instructions in the main program additionally .
SIM (Set Interrupt Mask): This instruction masks the interrupt as desired. This is a dual purpose
instruction. The first purpose is to set or reset the mask of the maskable interrupt. The second
purpose is to send the data out through the SOD pin at pin number 4 of the microprocessor.
RIM (Read Interrupt Mask): This instruction copies the status of the interrupts into the
accumulator. It is also used to read the serial data through the SID pin

HLT (Halt): After execution of this instruction the microprocessor goes into the halt state. The
processor can be restarted by a valid interrupt or by applying a RESET signal. The
microprocessor takes 5T states to implement the halt instruction.
I/O instructions:
There are two important instructions to input the data into the microprocessors accumulator
through the input port and output the data from the accumulator to the output port. They are

IN (port address)
OUT (port address)

This port address is an 8-bit address. In both these instructions the default register is
Accumulator.
Ex: (i) IN 01H. This instruction will copy the contents into the Accumulator through the port
whose address is 01H. It takes three machine cycles and takes 10 states. The op-code is DBH.
(ii)OUT 02H. This instruction sends the contents of Accumulator to the outport whose
address is 02H. It is a two byte instruction which requires 10 states. The op-code for this
instruction is D3H.

27

DETAILED INSTRUCTION SET

DATA TRANSFER INSTRUCTIONS

28

29

ARITHMATIC INSTRUCTIONS

30

31

32

33

34

35

36

37

38

39

SOD Serial output Data .Bit D7 of accumulator is latched in to the SOD output line made
available to serial peripheral if bit D6 =1 .
SOE Serial output enable.If this bit =1 ,it enables the serial output.
XXX Dont care condition
R7.5 Reset RST7.5.If this bit = 1 ,RST7.5 flip-flop is reset .This is an additional control to reset
RST7.5
MSE Mask set Enable.If this bit is high ,it enables the function of bits D2,D1 and D0.This is a
master control over all the interrupt masking bits.
M7.5 D2=0 ,RST 7.5 is enabled
D2=1 RST7.5 is masked or disabled
M6.5 D1=0 RST6.5 is enabled
D1=1 RST 6.5 masked or disabled.
M5.5 D0=0 RST5.5 is enabled
D0=1 RST 5.5 is disabled or masked.

ADDRESSING MODES
Majority of the instructions of 8085 microprocessor requires an operand (either data or
address) on which the intended operation can be performed. Some instructions may require only
one operand and some other instructions require two operands for its instruction execution. The
speed of execution mainly depends on the position of the operand in the instruction. The scheme
involved in identifying the position of operands in an instruction is known as addressing mode.
There are five addressing modes 8085 processor.They are
(i). Immediate addressing mode
(ii). Direct addressing mode
(iii). Register addressing mode.
(iv). Register indirect addressing mode.
(v). Implicit addressing mode.
(i). Immediate Addressing mode: The mode of addressing in which the operand is a part of the
instruction itself is known as Immediate Addressing mode. If the immediate data is 8-bit, the
instruction will be of two bytes. If the immediate data is 16 bit, the instruction is of 3 bytes.
Ex: (1). ADI DATA ; Add immediate the data to the contents of the accumulator.
(2).LXIH 8500H : Load immediate the H-L pair with the operand 8500H
(3). MVI 08H
; Move the data 08 H immediately to the accumulator
(4). SUI 05H
; Subtract immediately the data 05H from the accumulator
(ii) Direct Addressing mode: The mode of addressing in which the 16-bit address of the
operand is directly available in the instruction itself is called Direct Addressing mode. i.e., the
address of the operand (data) is available in the instruction itself. This is a 3-byte instruction.
Ex: (1). LDA 9525H ; Load the contents of memory location into Accumulator.
(2). STA 8000H ; Store the contents of the Accumulator in the location 8000H
(3). IN 01H ; Read the data from port whose address is 01H.
(iii). Register addressing modes: The mode, in which the operand is in one of the general
purpose registers, is known as the register addressing mode.
Ex: (1). MOV A, B;
Move the contents of B register to A register.
(2). SUB D;
Subtract the contents of D register from Accumulator.
(3). ADD B, C; Add the contents of C register to the contents of B register.

40

(iv). Register indirect addressing modes: The 16-bit address location of the operand stored in
a register pair (H-L) is given in the instruction. The address of the operand is given in an indirect
way with the help of a register pair. Hence it is called Register indirect addressing mode
Ex: (1). LXIH 9570H ; Load immediate the H-L pair with the address of the location 9570H
MOV A, M
; Move the contents of the memory location pointed by the H-L pair to
accumulator
(v). Implicit Addressing mode: The mode of instruction which do not specify the operand in the
instruction but it is implicated, is known as implicit addressing mode. i.e., the operand is
automatically considered to be in the Accumulator.
Ex: (1).CMA; complement the contents of Accumulator
(2).CMC; Complement carry
(3). RLC; Rotate Accumulator left by one bit
(4). RRC; Rotate Accumulator right by one bit
(5). STC; Set carry.

ASSEMBLY LANGUAGE PROGRAMMING EXAMPLES:

Addition Programs
Example 1: Addition of two 8-bit numbers whose sum is 8-bits.
Explanation: This assembly language program adds two 8-bit numbers stored in two memory
locations .The sum of the two numbers is 8-bits only.The necessary algorithm and flow charts are
given below.
ALGORITHM:
Step1. : Initialize H-L pair with memory address XX00 (say: 9000).
Step2. : Clear accumulator.
Step3. : Add contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. XX01).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
Step6. : Store the contents of accumulator in 9002.
Step7. : Halt
PROGRAM:
Address
of the
memory
location
8000

Hex
cod
e

Label

Mnemonics
OpOperand
code

Comments

LXI

H, 9000

8003
8004
8005

21,0
0,90
3E
00
86

MVI

A, 00

Initialise memory pointer to point

the first data location 9000.
Clear accumulator

ADD

A, M

8006

23

INX

8007

86

ADD

A, M

8008
8009
800A
800B

32
02
90
76

STA

9002

HLT

The first number is added to

accumulator [A] [A] + M
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator
The contents of accumulator are
stored in memory location 9002.
Stop the execution
41

Ex: Input: Ex: (i) 9000 29 H

9001 16 H
Result: Ex: (i) 9002 3F H

Ex :(ii) 9000 49 H
9001 32 H
Ex :( ii) 9002 7B

Flow Chart
Start
Initialise H-L Pair
with XX00

Clear Accumulator
(00) A

Add contents of M to
Accumulator

# Increment memory pointer(XX01)

# Add contents of M to A

Copy the contents of Reg. A

to memory location XX02

Stop

Fig 3.18

Example 2: Addition of two 8-bit numbers whose sum is 16 bits.

Explanation: The first 8-bit number is stored in one memory location (say 8500) and the second
8-bit number is stored in the next location (8501).Add these two numbers and check for carry.
Store the LSB of the sum in one memory location (8502) and the MSB (carry) in the other
location(8503).
ALGORITHM:
Step1. : Initialize H-L pair with memory address X (say: 8500).
Step2. : Clear accumulator.
Step3. : Add contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. 8501).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.

42

Step6. : Check for Carry

Step 7 : Store the sum in 8502.
Step8 : Store the Carry in 8503 location
Step 9 : Halt

Flow Chart

Start

Initialise H-L Pair with XX00

Clear Accumulator
(00) A

Add contents of M
to Accumulator

# Increment memory
pointer(XX01) &
# Add contents of M to A

Store the sum in the location

xx02

Is
Carry
exists ?

Yes

No

Store carry in the

XX03 location

Store Zero in the

XX03 location

Stop

Fig 3.19

43

PROGRAM:

Address
Hex
of
the code
memory
location
8000
21,00
,85
8003
3E
8004
00
8005
86

Lab
el

Mnemonics
OpOperand
code

Comments

LXI

H, 8500 H

MVI

A,00

Initialise memory pointer to point

the first data location 9000.
Clear accumulator

ADD

A, M

8006
8007
8008

0E
00
23

MVI

C,00

INX

8009

86

ADD

A, M

800A

32

JNC

FWD

800B
800C
800D
800E

0E
80
0C
32

INR
STA

C
8502 H

800F
8010
8011
8012
8013
8014
8015

02
85
79
32
03
85
76

MOV
STA

A,C
8503 H

Ex: Input:

Ex :

FW
D

HLT
8500 97 H
8501 98H

The first number is added to

accumulator [A] [A]+M
Initial value of Carry is 0
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator
Is Carry exists ? No,go to the label
FWD

Make carry =1
The sum is stored in memory
location 8502.

Store the carry at 8503 location

Stop the execution

RESULT:

8502 32 H
8503 -- 01 H

Example 3: Decimal addition of two 8-bit numbers whose sum is 16 bits.

Explanation: Decimal addition of two 8-bit numbers is same as that of two 8-bit numbers
program. Except that the use of DAA instruction. The first 8-bit number is stored in one memory
location (say 8500) and the second 8-bit number is stored in the next location(8501).Add these
two numbers and use the DAA instruction to get the result in decimal. Also check for carry. Store
the LSB of the sum in one memory location(8502) and the MSB (carry) in the other
location(8503).
ALGORITHM:
Step1. : Initialize H-L pair with memory address XXXX (say: 8500).
Step2. : Clear Carry register C.
Step3. : Move contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. 8501).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
44

Step6. : Apply the instruction DAA(Decimal adjust after addition)

Step7: Check for Carry
Step8: Store the sum in XX02.
Step9: Store the Carry in XX03 location
Step10: Halt

Flow Chart
Start

Initialise H-L Pair

with XX00

Clear Carry register

(00) C

Add contents of M to
Accumulator

# Increment memory
pointer(XX01) &
# Add contents of M to A

Apply DAA instruction to

convert Hex data to decimal
form

Store the sum in the

location XX02

Is
Carry
Exists?

Yes

Stores carry in the

XX03 location

No
Store Zero in the
XX03 location

Stop

Fig .20

45

PROGRAM
Address of
the
memory
location
8000

Hex
code

Label Mnemonics
OpOperand
code
LXI

8003
8004
8005

21,
00,85
0E
00
7E

8006

Comments

MVI

H, 8500 Initialise memory pointer to point

H
the first data location 9000.
C, 00
Clear accumulator

MOV

A, M

23

INX

8007

86

ADD

A, M

8008
8009

27
D2

DAA
JNC

FWD

Is Carry exists? No, go to the label

FWD

800C
800D
800E
800F
8010
8011

0D
80
0C
32
02
85
79
32

INR
STA

C
8502 H

Make carry =1
The contents of accumulator are
stored in memory location 8502.

MOV
STA

A, C
8503 H

Carry is moved to accumulator

A Carry is stored in the location
8503

8012
8013
8014

03
85
76

Ex: Input:

Ex :

FWD

HLT
8500 67 D
8501 85 D

The first number is added to

accumulator [A] [A]+M
Increment the memory pointer to
next location of the Data.
The 2nd number is added to
contents of accumulator

Stop the execution

RESULT:

8502 52 D
8503 01 (Carry)

Example 4: Addition of two 16-bit numbers whose sum is 16 bits or more

Explanation: First 16-bit number is stored in two consecutive locations (Ex 8500 &8501)
because in each location we can store only one 8-bit number. Store the second 16-bit number in
the next two consecutive locations (For Ex: 8502 &8503).Add the LSB of the first number to the
LSB of the second number and the MSB of the first number to the MSB of the second number
using the DAD instruction. Store the sum in the next two locations and the carry (if any) in the
third location
ALGORITHM:
Step1: First 16 bit number is in locations 8500 & 8501 respectively
Step2: Second 16-bit number is in locations 8502 & 8503
Step3: Add the two 16-bit numbers using DAD Instruction.
Step4: Sum is stored in locations 8504 & 8505.
Step5: Carry (if any) is stored in the location 8506.
Step6: Halt

46

Flow Chart

Start

Initialise H-L Pair

with 8500

Load the first 16-bit

number in to H-L Pair

Exchange this
number in to D-E
pair

Load the second 16-bit number

in to H-L pair

Add the LSB of Ist number to

the LSB of the second number
& MSB of the second number to
MSB of the second number
using DAD instruction

Store the LSBs of the sum in

8504 & 8505 locations

Is
Carry
Set?

Yes

No

Store1 in the 8506

location

Store 0 in the location 8506

Stop

Fig 21

47

PROGRAM:
ADDRESS

HEX
CODE

8000
8001
8002
8003

2A,00,85
00
85
EB

8004
8005
8006
8007
8008
8009
800A
800B
800C
800D
800E
800F
8010
8011

2A
02
85
0E
00
19
D2
0E
80
OC
22
04
85
79

8012
8013
8014
8015

32
06
85
76

Ex: INPUT:

LABEL

MNEMONIC

OPCO
DE
LHLD

COMMENTS

OPERAND
8500 H

First 16-bit number in H-L pair

XCHG

FWD

Exchange first number to D-E

Pair

LHLD

8502 H

MVI

00

MSB of the sum is initially 00

DAD
JNC

D
FWD

Add two 16 bit numbers

Is Carry? If yes go to the next line
.Else go to the 800E LOCATION

INR
SHLD

C
8504 H

Increment carry
Store the LSB of the Sum in 8504
& MSB in 8505 locations

MOV

A,C

STA

8506 H

MSBs of the sum is in

Accumulator
Store the MSB (Carry) of the
result in 8506 location

HLT

8500- 12 H LSB of the Ist Number

8501- 13 H MSB of the Ist Number
8502 -13 H LSB of the IInd Number
8503 -12H MSB of the IInd number

Stop execution
RESULT : 8504 - 25H LSB of the Sum
8505 25H MSB of the Sum
8506 -- 00 Carry .

Subtraction Programs:
Example 5: Subtraction of two 8-bit numbers without borrows.
Explanation: Its a simple program similar to addition of two 8- bit numbers, except that we use the
instruction SUB instead of ADD. The first 8-bit number is stored in XX00 memory location and the second
8-bit number is stored in the XX01 location .Use the SUB instruction and store the result in the XX02
location.

ALGORITHM:
Step1. : Initialise H-L pair with the address of minuend.
Step2. : Move the minuend into accumulator
Step3. : Increment H-L pair
Step4. : Subtract the subtrahend in memory location M from the minuend.
Step5. : Store the result in XX02.
Step6. : Stop the execution

48

Flow Chart
Start

Initialise H-L Pair with

XX00

Move the contents of M

to Accumulator

Increment memory
pointer(XX01)

Subtract the subtrahend in

memory location M from
the minuend in A

Store the result in the

location XX02

Stop

Figure 22
PROGRAM:
ADDRESS

HEX
CODE

8000

LABEL

COMMENTS

21

MNEMONIC
OPCOD OPERAN
E
D
LXI
H, 8500

8001
8002
8003
8004
8005
8006
8007

00
85
7E
23
96
23
77

MOV
INX
SUB
INX
MOV

8008

76

HLT

[A] [M]
[M+1] [M]
A [A] [M]
Next memory location
Store the result in the location
8502
Stop the execution

A,M
H
M
H
M,A

Initialise H-L pair and get the

First number in to 8500
location

49

INPUT: Ex :

8500- 59H
8501- 30H

Result: 8502 29H

Example 6: Subtraction of two 8-bit Decimal numbers.

Explanation: In this program we cant use the DAA instruction after SUB or SBB instruction because it is
decimal adjust after addition only. So, for decimal subtraction the number which is to be subtracted is
converted to 10s complement and then DAA is applied.

ALGORITHM:
Step1. : Initialise H-L pair with the address of second number (XX01).
Step2. : Find its tens complement
Step3. : Decrement the H-L pair for the first number (XX00)
Step4. : Add the first number to the 10s complement of second number.
Step5. : Store the result in XX02.
Step6. : Stop the execution

Flow Chart
Start

Initialise H-L Pair with XX01

and get the second number

Find its 10s

complement
Add first number to the 10s
complement of the second number

Apply the DAA instruction to get

decimal result

Store the result in the

location XX02

Stop

Figure 23

50

PROGRAM:
ADDRESS
8000

HEX
CODE
21

8001
8002
8003
8004
8005

00
85
3E
99
96

MVI

A,99

[A] 99

SUB

8006

3C

INR

8007
8008

2B
86

DCX
ADD

H
M

9s complement of second
number
10s complement of second
number
Address of the first number
Add first number to 10s
complement of second number

8009
800A

27
32

DAA
STA

8502

800B
800C
800D

02
85
76

HLT

Ex: Input: 8500 -76 D

LAB
EL

MNEMONIC
COMMENTS
OPCODE OPERAND
LXI
H,8500
Initialise H-L pair and get
theSecond number in to 8501
location

Store the result in the location

8502

Stop the execution

Result: 8502 - 41 D

8501- 35 D

Example 6: Subtraction of two 16 bit numbers.

Explanation: It is very similar to the addition of two 16-bit numers.Here we use SUB &SBB
instructions to get the result .The first 16-bit number is stored in two consecutive locations and
the second 16-bit number is stored in the next two consecutive locations.The lsbs are subtracted
using SUB instruction and the MSBs aare subtracted using SBB instruction.The result is stored in
different locations.
ALGORITHM:
Step1. : Store the first number in the locations 8500 & 8501.
Step2. : Store the second number in the locations 8502 &8503.
Step4. : Subtract the second number from the first number with borrow.
Step5. : Store the result in locations 8504 & 8505.
Step6. : Store the borrow in location 8506
Step 7: Stop the execution

51

Flow Chart
Start

Initialize H-L Pair

with XX00

Load the first 16-bit number in

to H-L Pair A

Exchange this
number in to D-E
pair

Load the second 16-bit number

in to H-L pair

Subtract LSB of 2 nd number

from the LSB of the Ist number
& MSB of the 2 nd number from
MSB of the first number

Store the result in XX04 &

XX05 locations

Is
borrow
Set ?

Yes

No
Store 0 in the location XX06

Store 1 in the
XX06 location

No

Stop

Fig 24

52

PROGRAM:
ADDRESS

HEX
CODE

8000
8003
8004
8005
8006
8007

2A,
00,85
EB
2A
02
85
7B

8008

LABE
L

MNEMONIC
OPCOD
OPERAN
E
D
LHLD
8500 H

COMMENTS

XCHG
LHLD

8502 H

Exchange first number to D-E Pair

Get the second 16-bit number in H-L
pair

MOV

A, E

95

SUB

8009
800A
800A

6F
9C

MOV
MOV
SBB

L, A
A, D
H

800B
800C

67
22

MOV
SHLD

H, A
8504

800D
80OE
80OF

04
85
76

HLT

First 16-bit number in H-L pair

Get the lower byte of the First number

in to Accumulator
Subtract the lower byte of the second
number
Store the result in L- register
Get higher byte of the first number
Subtract higher byte of second number
with borrow
Store the result in memory locations
with LSB in 8504 & MSB in 8505

Stop execution

53

Ex: INPUT :

8500- FF H LSB of the Ist Number

8501 - FF H MSB of the Ist Number
8502 -EE H LSB of the IInd Number
8503 EE H MSB of the IInd number

RESULT: 8504 - 11H LSB

8505 11 H MSB

Multiplication Programs
Example 7: Multiplication of two 8-bit numbers. Product is 16-bits.
Explanation: The multiplication of two binary numbers is done by successive addition. When
multiplicand is multiplied by 1 the product is equal to the multiplicand, but when it is multiplied by
zero, the product is zero. So, each bit of the multiplier is taken one by one and checked whether
it is 1 or 0 .If the bit of the multiplier is 1 the multiplicand is added to the product and the product
is shifted to left by one bit. If the bit of the multiplier is 0 , the product is simply shifted left by one
bit. This process is done for all the 8-bits of the multiplier.
ALGORITHM:
Step 1 : Initialise H-L pair with the address of multiplicand.(say 8500)
Step 2 : Exchange the H-L pair by D-E pair. so that multiplicand is in D-E pair.
Step 3 : Load the multiplier in Accumulator.
Step 4 : Shift the multiplier left by one bit.
Step 5 : If there is carry add multiplicand to product.
Step 6 : Decrement the count.
Step 7 : If count 0; Go to step 4
Step 8 : Store the product i.e. result in memory location.
Step 9 : Stop the execution

Flow Chart
Start

Load the multiplier in to Accumulator &

multiplicand in D-E pair

Initial value of product=00.

Count=08

Shift product left by one bit &Shift

multiplier left by one bit

Is carry
exists from
multiplier ?

No

Yes
Product = Product + Multiplicand

54

Count = count -1

No

Is count
=0?

Yes
Store result

Stop

Figure 25

PROGRAM:

ADDRESS

8000
8003
8004
8005
8006
8007
8008
8009
800A
800B
800C
800D
800E
800F
8010
8011

HEX
COD
E

LABE
L

2A,0
0,85
EB
3A
02
85
21
00
00
0E
08
29
LOO
P
17
D2
12
80
19

MNEMONIC

COMMENTS

OPCOD
E

OPERAND

LHLD

H, 8500

Load the multiplicand in to H-L pair

XCHG
LDA

8502

Exchange the multiplicand in to D-E pair

Multiplier in Accumulator

LXI

H.0000

Initial value in H-L pair is 00

MVI

C,08

Count =08

DAD

Shift the partial product left by one bit.

RAL
JNC

FWD

Rotate multiplier left by one bit

Is Multiplier bit =1? No go to label FWD

DAD

Product =Product +Multiplicand

55

8012
8013
8014
8015
8016

0D
C2
0C
80
22

8017
8018
8019

03
85
76

FWD

DCR
JNZ

C
LOOP

COUNT=COUNT-1

SHLD

8503

Store the result in the locations 8503 &

8504

HLT

Stop the execution

INPUT :

Result:

Address
8500
8501
8502

Data
8AH LSB of Multiplicand
00 H MSB of Multiplicand
52 H - Multiplier

8503
8504

34 H LSB of Product
2C H MSB of Product

Division Programs
Example 7:

Division of a 16- bit number by a 8-bit number.

Explanation: The division of a 16/8-bit number by a 8-bit number follows the successive
subtraction method. The divisor is subtracted from the MSBs of the dividend .If a borrow occurs,
the bit of the quotient is set to 1 else 0.For correct subtraction process the dividend is shifted left
by one bit before each subtraction. The dividend and quotient are in a pair of register H-L.The
vacancy arised due to shifting is occupied by the quotient .In the present example the dividend is
a 16-bit number and the divisor is a 8-bit number. The dividend is in locations 8500
&8501.Similarly the divisor is in the location 8502.The quotient is stored at 8503 and the
remainder is stored at 8504 locations.
ALGORTHM:
STEP1. : Initialise H-L pair with address of dividend.
STEP2. : Get the divisor from 8502 to register A & then to Reg.B
STEP3. : Make count C=08
STEP4. : Shift dividend and divisor left by one bit
STEP 5: Subtract divisor from dividend.
STEP6. : If carry = 1 : goto step 8 else step7.
STEP7. : Increment quotient register.
STEP8. : Decrement count in C
STEP9. : If count not equal to zero go to step 4
STEP10: Store the quotient in 8503
STEP11: Store the remainder in 8504
STEP12: Stop execution.

56

57

Flowchart

START

Initialise H-L pair with address of

dividend

Copy the divisor in to Reg. A

Move the divisor in to Reg. B

Move count =08 in to C register

# Shift dividend left by one bit

# Shift Quotient left by one

bit+

Is MSBs of
Dividend >
Divisor ?

No

Yes
Quotient = Quotient +1

8 MSBs of dividend =
8 MSBs of dividend -divisor

Count = Count-1

No

Is
Count
=0?

Yes

store th quotient in 8503

&remainder in 8504

Stop

Fig.26

58

PROGRAM:
ADD
RESS
8000
8001
8002
8003
8004
8005
8006

HEX LABEL
CODE

8007
8008
8009

0E
08
29

800A

MNEMONIC
OPCOD OPERAN
E
D
LHLD
H, 8500

COMMENTS

LDA

8502 H

Load
the
divisor
from
location 8502 to accumulator

MOV

B,A

MVI

C,08

Move Divisor to Reg.B from

A
Count =08

DAD

7C

MOV

A,H

800B

90

SUB

800C
800D
800E
800F

DA
11
80
67

JC

FWD

MOV

H,A

8010
8011
8012
8013
8014
8015
8016
8017
8018

2C
0D
C2
09
80
22
03
85
76

INR
DCR
JNZ

L
C
BACK

SHLD

8503H

Ex:

21
00
85
3A
02
85
47

BACK

FWD

Input & Result

HLT

Initialize the H-L pair for

dividend

Shift dividend and quotient

left by one bit
MSB of dividend in to
accumulator
Subtract divisor from MSB
bits of divisor
Is MSB part of dividend >
divisor ? No,goto label FWD
MSB of the dividend in
Reg.H
Increment quotient
Decrement count
If count is not zero jump
to8009 location
Store quotient in 8503 and
remainder in 8504 locations
Stop execution

Address
8500
8501
8502
8503
8504

Data
64 LSB of Dividend
00 MSB of Dividend
07 Divisor
0E Quotient
02 Remainder

59

Largest & Smallest numbers in an Array

Example 8:

To find the largest number in a data array

Explanation: To find the largest number in a data array of N numbers (say)first the count is
placed in memory location (8500H) and the data are stored in consecutive
locations.(8501.onwards).The first number is copied to Accumulator and it is compared with
the second number in the memory location. The larger of the two is stored in Accumulator. Now
the third number in the memory location is again compared with the accumulator. And the largest
number is kept in the accumulator. Using the count, this process is completed , until all the
numbers are compared .Finally the accumulator stores the smallest number and this number is
stored in the memory location.85XX.
ALGORTHM:
Step1: Store the count in the Memory location pointed by H-L register.
Step2: Move the I st number of the data array in to accumulator
Step3: Compare this with the second number in Memory location.
Step4: The larger in the two is placed in Accumulator
Step5: The number in Accumulator is compared with the next number in memory .
Step 6: The larger number is stored in Accumulator.
Step 7; The process is repeated until the count is zero.
Step 8: Final result is stored in memory location.
Step 9: Stop the execution

60

Flow Chart

START

Initialise H-L pair

Get the count in Register C

Get first number in Accumulator

Yes

No

Is
Number in
Accumulator>
Next number ?

Get Larger number in

Accumulator

No
Decrement Count

No

Is count = 0
?
Yes
store the result in the
location 85XX

STOP
Fig 27

61

PROGRAM
ADD
RESS
8000

HEX LABEL
CODE

MNEMONIC
OPCOD OPERAN
E
D
LXI
H, 8500

COMMENTS

MOV
INX
MOV

C,M
H
A,M

DCR
INX
CMP

C
H
M

Count in the C register

First number in H-L pair
Move first number in to
Accumulator
Decrement the count
Get the next number
Compare the next number
with previous number
Is next number >previous
maximum?No,go
to
the
loop2

8003
8004
8005

21,00,8
5
7E
23
4E

8006
8007
8008

0D
91
BE

8009

D2

JNC

LOOP2

800A
800B
800C

0D
80
7E

MOV

A,M

800D
800E

0D
C2

DCR
JNZ

C
LOOP1

800F
8011
8012
8013

07
80
78
32

STA

85XX

8014
8015
8016

XX
85
76

HLT

Ex : Input :

LOOP1

LOOP2

8500- N(Say N=7 )

8501-05
8502-0A
8503-08
8504-14
8505 -7F
8506-25
8507-2D

INITIALISE H-L PAIR

If,yes move
the large
number in to Accumulator
Decrement the count
If count not equal to
zero,repeat

Store the largest number in

the location 85XX

Stop the execution

Result : 8508 - 7F

62

Example 9 :

To find the smallest number in a data array.

Explanation: To find the smallest number in a data array of N numbers (say)first the count is
placed in memory location (8500H) and the data are stored in consecutive
locations.(8501.onwards).The first number is copied to Accumulator and it is compared with
the second number in the memory location.The smaller of the two is stored in Accumulator.Now
the third number in the memory location is again compared with the accumulator.and the
smallest number is kept in the accumulator.Using the count,this process is completed until all
the numbers are compared .Finally the accumulator stores the smallest number and this number
is stored in the memory location.85XX.
ALGORTHM :
Step1: Store the count in the Memory location pointed by H-L register.
Step2: Move the I st number of the data array in to accumulator
Step3: Compare this with the second number in Memory location.
Step4: The smaller in the two is placed in Accumulator
Step5: The number in Accumulator is compared with the next number in memory .
Step 6: The smaller number is stored in Accumulator.
Step 7; The process is repeated until the count is zero.
Step 8: Final result is stored in memory location.
Step 9: Stop the execution

63

Flow Chart
START

Initialise H-L pair

Get the count in Register C

Get first number in to

Accumulator

Yes

Is
Number in
Accumulator<
Next number ?

No
Get smaller number in
Accumulator

Decrement Count

Is count =
0 ?
No
Yes
store the result at 85xx

STOP
Fig.28

64

PROGRAM
ADD
RESS
8000
8001
8002
8003
8004
8005

HEX LABEL
CODE

8006
8007
8008

0D
91
BE

8009

MNEMONIC
OPCOD OPERAN
E
D
LXI
H, 8500

COMMENTS

MOV
INX
MOV

C,M
H
A,M

DCR
INX
CMP

C
H
M

D2

JC

LOOP2

Count in the C register

First number in H-L pair
Move first number in to
Accumulator
Decrement the count
Get the next number
Compare the next number
with previous number
Is next number <previous
smallest ?If yes go to the
loop2

800A
800B
800C

0D
80
7E

MOV

A,M

800D
800E

0D
C2

DCR
JNZ

C
LOOP1

800F
8011
8012
8013

07
80
78
32

STA

85XX

8014
8015
8016

XX
85
76

HLT

21
00
85
7E
23
4E

Ex: Input :

LOOP1

LOOP2

8500 - N((Say N=7)

8501-09
8502-0A
8503-08
8504-14
8505 -7F
8506-04
8507-2D

Initialise the H-L pair.

No,move
the smaller
number in to Accumulator
Decrement the count
If count not equal to
zero,repeat

Store the smallest number in

the location 85XX

Stop the execution

Result : 8508 04

Stack and Subroutines

Stack is a set of memory locations in the Read/Write memory which is used for temporary
storage of binary information during the execution of a program. It is implemented in the Last-infirst-out (LIFO) manner. i.e., the data written first can be accessed last, One can put the data on
the top of the stack by a special operation known as PUSH. Data can be read or taken out from
the top of the stack by another special instruction known as POP.

65

Stack is implemented in two ways. In the first case, a set of registers is arranged in a
shift register organization. One can PUSH or POP data from the top register. The whole block of
data moves up or down as a result of push and pop operations respectively. In the second case,
a block of RAM area is allocated to the stack. A special purpose register known as stack pointer
(SP) points to the top of the stack. Whenever the stack is empty, it points to the bottom address.
If a PUSH operation is performed, the data are stored at the location pointed to by SP and it is
decremented by one. Similarly if the POP operation is performed, the data are taken out of the
location pointed at by SP and SP is incremented by one. In this case the data do not move but
SP is incremented or decremented as a result of push or pop operations respectively.
3.14.1 Application of Stack: Stack provides a powerful data structure which has applications in
many situations. The main advantage of the stack is that,
We can store data (PUSH) in it with out destroying previously stored data. This is not true in the
case of other registers and memory locations.
stack operations are also very fast
The stack may also be used for storing local variables of subroutine and for the transfer of
parameter addresses to a subroutine. This facilitates the implementation of re-entrant
subroutines which is a very important software property.
The disadvantage is, as the stack has no fixed address, it is difficult to debug and document a
program that uses stack.
3.14.2 Stack operation: Operations on stack are performed using the two instructions namely
PUSH and POP. The contents of the stack are moved to certain memory locations after PUSH
instruction. Similarly, the contents of the memory are transferred back to registers by POP
instruction.
For example let us consider a Stack whose stack top is 4506 H. This is stored in the 16bit Stack pointer register as shown in Fig.3.29

Figure.29 The PUSH operation of the Stack

Let us consider two registers (register pair) B & C whose contents are 25 & 62.
Reg. B
Reg. C

25

62

66

After PUSH operation the status of the Stack is as shown in Fig 3.30

Figure .30 After PUSH operation the status of the stack

Let us now consider POP operation: The Figs 3.31 & 3.32 explains before and after the POP
operation in detail

67

Figure 3.31 The POP operation of the Stack

Figure 32 After POP operation the status of the stack

Before the operation the data 15 and 1C are in the locations 4502 & 4503 and after the pop
operation the data is copied to B-C pair and now the SP register points to 4504 location.This is
shown in Fig.3.32

Programming Example FOR PUSH & POP

Write a program to initialize the stack pointer (SP) and store the contents of the register pair H-L
on stack by using PUSH instruction. Use the contents of the register pair for delay counter and at
the end of the delay retrieve the contents of H-L using POP.
Memory
Location
8000

Label

Mnemonics

Operand

Comments

LXI

SP, 4506 H

Initialize
Stack pointer

8003

LXI

H,2565 H

8006
8007
.
.
.
.
8.00A

PUSH

DELAY

CALL

.
.
.

.
.
.

POP

Push
the
contents.

68

Subroutine: It is a set of instructions written separately from the main program to execute a
function that occurs repeatedly in the main program.
For example, let us assume that a delay is needed three times in a program. Writing delay
programs for three times in a main program is nothing but repetition. So, we can write a
subroutine program called delay and can be called any number of times we need
Similarly, in 8085 microprocessor we do not find the instructions for multiplication and
division. For this purpose we write separate programs. So, in any main program if these
operations are needed more than once, the entire program will become lengthy and complex. So,
we write subroutine programs MUL & DIV separately from main program and use the instruction
CALL MUL (or) CALL DIV in the main program. This can be done any number of times. At the
end of every subroutine program there must be an instruction called RET. This will take the
control back to main program.
The 8085 microprocessor has two instructions to implement the subroutines. They are CALL
and RET. The CALL instruction is used in the main program to call a subroutine and RET
instruction is used at the end of the subroutine to return to the main program. When a subroutine
is called, the contents of the program counter, which is the address of the instruction following
the CALL instruction is stored on the stack and the program execution is transferred to the
subroutine address. When the RET instruction is executed at the end of the subroutine, the
memory address stored on the stack is retrieved and the sequence of execution is resumed in
the main program.
Diagrammatic representation
Let us assume that the execution of the main program started at 8000 H. It continues until a
CALL subroutine instruction at 8020 H is encountered. Then the program execution transfers to
8070 H. At the end of the subroutine 807B H. The RET instruction is present. After executing this
RET, it comes back to main program at 8021 H as shown in the following Fig. 3.34

Fig.33 Diagrammatic representation of subroutine program execution

69

The same is explained using the assembly language program example.

Program Example:
Memory
Address

Mnemonics

Operand

Comments

8000
|
|
|
8020
8021
8022
8023
|
|
|
802F

LXI

SP, 8400 H

Initialize the Stack pointer at 8400 H

CALL

8070 H

Call a subroutine program stored at

the location 8070 H. (It is a three by
Instruction)
The address of the next instruction
following CALL instruction.

Next instruction
|
|
|
HLT

End of the main program

.

Subroutine Program:
Memory
Address
8070
|
|
|
|
807B

Mnemonics

807C

Next Subroutine

Instructions

RET

807F

RET

Operand

Comments
Beginning of the Subroutine.

End of the program

Instructions of next subroutine if
any

End of the subroutine.

Delay programs:

In many situations it may be desired to provide some delay between the execution of two
instructions by a microprocessor. The delay can be produced by either hardware chip like 8253
or by writing a software program using registers of the processor. Here we will discuss the
software delay program. This delay program is not a part of the main program. Hence it is called
delay sub-routine program. For small delays we can use only one register. But for longer delays
one has to use two or three registers. The technique involved here is, a register is loaded with a
number and then decremented by using the instruction DCR until it becomes zero. The time of
execution of the microprocessor is equal to the delay time produced.
For example, we have constructed a display system where the LEDs receive the input from a
microprocessor. Since the microprocessor is a very fast device it sends the signal at very high

70

speeds there by our eye cannot recognize the display pattern. So, if you provide some delay
between two input signals, the display can be visualized clearly. Similarly to observe the rotations
of a stepper motor, a delay is needed between every two excitation signals applied to the motor.
Delay Subroutine with one register:
Program
Address Label

Machine
code

Mnemonics

Operand

Comments

MVI

A, FF

Get FF in register A

DCR

Decrement register A.

9003

JNZ

LOOP

9006

RET

Has the content of

register B becomes
zero? No, jump to
LOOP. Yes, proceed
ahead.
Return to main program

9000
9002

LOOP

Calculation of Delay time for the above program:

In the above program register A is loaded by FFH B(255 decimal) and it is decremented in a loop until it
becomes zero. The delay produced by this program is as follows

We should know the number of times each instruction of the above program is being
executed. The number of states required for the execution of each instruction is as follows:

Instructions
MVI A, FFH
(loop) DCR A
JNZ loop
RET

States
7
4
7/10
10

Total T States=3584

71

The time required for one T-state in INTEL 8085 microprocessor is nearly 330n.sec

Delay time is= 3584 x 333n.sec

= 3.584 x 0.333 x 10-3 seconds
= 1.18272 x 10-3 seconds
= 1. 193472 milliseconds
Delay Subroutine with two registers
Program:

Address Label

Machine Mnemonic Operand Comments

Code

8400

MVI

B, 10H

Get desired number in register B

8402

LOOP1

MVI

C, 56H

Get desired number in register

8404

LOOP2

DCR

Decrement C.

8405

JNZ

LOOP2

Is [C] zero? No, go to LOOP2. Yes,

proceed further

8408

DCR

Decrement register B

8409

JNZ

LOOP1

840C

RET

Is [B] zero? No, go to LOOP1. Yes,

proceed further
Return to main program.

Delay Subroutine using register pair

Program:

Addres
s

Label

8000
LOOP

Machin
e
Code

Mnemonic Operand

Comments

LXI

D, FFFF

Get FFFF in register pair D-E

DCX

Decrement count

MOV

A, D

Move the contents of register D to

accumulator

ORA

Check if D and E are zero.

JNZ

LOOP

If D-E is not zero, jump to LOOP

RET

Return to main program

Delay Subroutine using three registers

Program:

72

Addres
s

Label

Machin
e
Code

Mnemonic

Operand

Comments

8400

MVI

A, 98H

Get control word

8402

OUT

03

Initialize port foe LED Display

8404

MVI

B, 50H

8406

MVI

C, FFH

8408

MVI

D, FFH

840A

DCR

840B

JNZ

LOOP3

840E

DCR

840F

JNZ

LOOP2

8412

DCR

8413

JNZ

LOOP1

8416

MVI

A, 01

8418

OUT

01

8419

HLT

Delay Subroutine
registers

with

three

Output for LED

Stop.

From the above discussion it is clear that with increase of T-states required for a delay
subroutine ,the delay time also increases.

-----------------x------------------

73

74

75