Features of 8086 microprocessor Architecture

It needs 5-MHz for 8086, 8-MHz for 8086-2 and 10-MHz for 8086-1
It is possible to perform bit, byte word and block operation in 8086. It performs the
arithmetic and logic operations on bit, byte and decimal numbers including multiply
and divide.
The Intel 8086 microprocessor architecture is designed to two modes namely the
minimum mode and the maximum mode. When only one 8086 CPU is to be used in
a microcomputer system the 8086 is used in the minimum mode. In this mode the
CPU issues the control signals required by memory and I/O device. In multiprocessor
system if operates in maximum mode, in this mode the control signals are
generated with the help of external bus controller (8288).
The INTEL 8086 microprocessor architecture supports Multi-programming.
In 8086 microprocessor architecture it pre-fetches up to six instruction bytes from
memory and queues them in order to increase the speed of execution.
8086 microprocessor architecture provides the powerful instruction set.
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8086 Microprocessor architecture

The 8086 Microprocessor architecture consists of two sections

Bus Interface Unit (BIU)
Execution unit(EU)
Execution Unit

Execution unit in the microprocessor architecture does the following action

It informs B.I.U(bus interface unit) from where to fetch instruction of data and where
to store the data.
It decodes the op-codes which is fetched from queue register and then execute that
instruction

The important blocks are:

a). ID(Instruction decoder), Control Unit, ALU:

ID decodes the op-code which is fetched from Queue Register. Then the control unit
will generate proper control signals to execute that instruction. The ALU is 16-bit,
i.e. it can perform arithmetic and logic operation on 16-bit as well as 8-bit data.
b). Data Group (Arithmetic Register):

It has 8-general purpose register, denoted by AH, AL, BL, CH, CL, DH & DL. The
width of each register is 8 bit. They are used for 8-bit data. For 16-bit data we have
to use AX, BX, CX, and DX. Here AX- register is known as Accumulator. BX Register
also used to sore the 16-bit effective address. CX register is also used as implied
counter for some instruction. DX register also used.
To store I/O address for some instructions, and
To store some part of result after performing multiplication and division.
c) Pointer and index register:

In this microprocessor architecture Pointer and index register are used to store 16bit offset address. They are SP (Stack Pointer), BP (Base Pointer), SI (Source Index
Register), DI (Destination Index Register).
d) Flag Register in 8086 microprocessor architecture:

It is a 16-bit register, but in 8086 microprocessor architecture there are only 9-flags.
So, only 9-bits are used. All 9 flags Divided into two groups.
Conditional Flags: They are used to indicate some condition produced after
executing an instruction. For this purpose 6-flags are used.
Control flags: they are used to control some operation of microprocessor. For that
purpose 3 flags are used.
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BIU (Bus Interface unit)

It is 8086 microprocessor architecture interface to the outside world. It provides the

16-bit bidirectional data bus and 20 bit address bus. This unit is responsible for
performing all external bus operations.
It gives address of memory or I/O.
It fetches opcode from memory.
It read data from memory or I/O port.
It writes data into memory or I/O port.
It supports instruction queuing.
The important blocks in the BIU are:
Instruction pointer

It is a 16-bit register. It is used to store 16-bit effective address or logical address)

for CS register. BIU generates 20-bit physical address (PA) by using base address
and effective address.
For E.g. - content of CS is 4000H and content of IP is 1250H. Now the physical
address is given as.
8086 microprocessor architecture, calculating base address

Segment register

We have a 4-segment register known as CS- register (Code Segment register), DSregister (data Segment Register), SS Register (Stack Segment Register), and ES
Register (Extra Segment Register).
In 8086 microprocessor architecture the width of each register is 16- bit, it is used to
store upper 16- bit starting address of memory segment. This address is known as
Base address.
Queue register (Instruction Register)

It is a 6-byte register. It is used to store 6-bytes which are fetched from CS memory.
The 6-bytes are stored in this register in FIFO form. The BIU fetches this when EU is
executing the current instruction. When EU is ready for next instruction, it simply
reads from queue register instead of from memory. Therefore speed is increased.
This technique is known as pipeline. This is the advantage of the queue register.
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Memory Segmentation in 8086 microprocessor architecture and its Advantages

8086 microprocessor architecture, memory segmentation in 8086

Physical address of 8086 is 20 bit wide. So it can access 1 MB memory (2^20*8=1

MB or 16*64 KB). This 1 MB memory is divided into 16 Segment memories. The
capacity of each memory segment is 64 KB. But 8086 can access at a time only
memory segment. They are CS memory, DS memory, SS memory and ES memory.
Instruction fetch operations are performed in DS memory. String operations are
performed in ES memory.
For the selection of each segment memory, 8086 has 4- segment registers. They
are known as CS Register, DS Register, SS Register, and SS Register. The content of
each segment register is known as the Base Register. BIU generates 20-bit physical
Address by using Base Address and Effective Address.

Advantages of Memory segmentation

In 8086 microprocessor architecture It permits its programmer to access 1MB

memory even though address associated with the Instruction is 16 bit.
Instruction, data, sack of a program can be more than 64KB memory in 8086
microprocessor architecture
8086 microprocessor architecture permits separate memory area for instruction,
data and stack. So one program can work on different sets of data.

This method is very useful during the multitasking in 8086 microprocessor

architecture
Disadvantage: Even though memory capacity is 16*64KB, microprocessor can
access at a time only 4*64 KB of memory.

Flag Register in 8086 microprocessor architecture

8086 microprocessor architecture, flag registers in 8086

Conditional flags in 8086 microprocessor architecture:

Carry flag: this flag is set whenever there is an overflow from MSB after performing
arithmetic operation, otherwise it is reset. For 8-bit operation overflow is from B7 bit
for 16-bit operation overflow is from B15 bit.
Parity Flag: This flag is set if lower order 8-bit of the result consists of even number
of 1s, otherwise it is reset.
Auxiliary Carry flag: This flag is set if there is overflow from lower 4-bits after
performing arithmetic operation, otherwise it is reset.
Zero Flag: this flag is set if the result is zero after performing ALU operation,
otherwise it is reset.
Sign flag: It is set if MSB of the result is equal to 1 after performing ALU operation,
otherwise it is reset. (for 8-bit data it is set when B7=1, for 16-bit data it is set when
B15=1),
Overflow Flag: this flag is set, if the result cannot be stored in destination location,
otherwise it is reset. This flag is checked during signed arithmetic. This flag can be
checked by using an instruction INTO.
It will set when
Overflow from B6 to B7, AND no overflow from B7(for 8-bit operation)
Overflow from B14 to B15 AND no overflow from B15(for 16-bit operation)
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2. Control flag

A) Trap Flag: When this flag is set, 8086 enters into single stepping mode. In this
mode system will execute one instruction and wait for further direction from the
programmer. It is used to debug the program. If it is reset, control continues
sequentially
B) Interrupt Enable Flag: When it is set, 8086 recognizes interrupt INTR. If it is
reset it will not recognize interrupt INTR i.e. INTR is maskable interrupt.
C) Directional Flag: When it is set, content of SI or DI or both automatically
decremented (by 1 or 2) after executing the string instruction. If it is reset, content
of SI or DI or both are automatically incremented (by 1 or 2) after executing the
string instruction.
So, this article is dedicated to the 8086 Microprocessor architecture, in the next
article we will discuss about the addressing modes of 8086 and instructions set of
8086 microprocessor. if you have any query regarding 8086 Microprocessor
architecture, then you can comment below, I will surely respond to your comment
with appropriate answer.:)

FLAGS register
From Wikipedia, the free encyclopedia

This article discusses the flag register specific to the x86 architecture. For a general discussion about
flag registers, see status register.
The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the
processor. This register is16 bits wide. Its successors, the EFLAGS and RFLAGS registers,
are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller
predecessors.
Contents
[hide]

1 Flags

2 Use

3 Determination of processor type

4 See also

5 References

Flags[edit]
Intel x86 FLAGS register[1]

Bit #

Abbreviation

Description

Category

FLAGS

CF

Carry flag

Status

Reserved

PF

Parity flag

Reserved

AF

Adjust flag

Reserved

ZF

Zero flag

Status

SF

Sign flag

Status

TF

Trap flag (single step)

Control

IF

Interrupt enable flag

Control

10

DF

Direction flag

Control

Status

Status

11

OF

Overflow flag

Status

12-13

IOPL

I/O privilege level (286+ only), always 1 on 8086 and 186

System

14

NT

Nested task flag (286+ only), always 1 on 8086 and 186

System

15

Reserved, always 1 on 8086 and 186, always 0 on later models

EFLAGS

16

RF

Resume flag (386+ only)

System

17

VM

Virtual 8086 mode flag (386+ only)

System

18

AC

Alignment check (486SX+ only)

System

19

VIF

Virtual interrupt flag (Pentium+)

System

20

VIP

Virtual interrupt pending (Pentium+)

System

21

ID

Able to use CPUID instruction (Pentium+)

System

22

Reserved

23

Reserved

24

Reserved

25

Reserved

26

Reserved

27

Reserved

28

Reserved

29

Reserved

30

Reserved

31

Reserved

RFLAGS

32-63

Reserved

Use[edit]
The POPF, POPFD, and POPFQ instructions read from the stack the first 16, 32, and 64 bits of the flags
register, respectively. POPFD was introduced with the i386 architecture and POPFQ with
the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not
PUSHFD/POPFD.[2]
The following assembly code changes the direction flag (DF):
pushf ; Pushes the current flags onto the stack
pop ax ; Pop the flags from the stack into ax register
push ax ; Push them back onto the stack for storage
xor ax, 400h ; toggle the DF flag only, keep the rest of the flags
push ax ; Push again to add the new value to the stack
popf ; Pop the newly pushed into the FLAGS register
; ... Code here ...
popf ; Pop the old FLAGS back into place
In practical software, the cld and std instructions are used to clear and set the direction flag,
respectively. Some instructions inassembly language use the FLAGS register. The conditional jump

instructions use certain flags to compute. For example, jz uses the zero flag, jc uses the carry
flag, jo uses the overflow flag...

Determination of processor type[edit]

Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is
installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be
changed then the CPU is a 486 or higher. These methods of processor detection were made obsolete by
the CPUID instruction, which was first included in the Intel Pentium.

Purpose of using flag registers.

FLAGS : 8086 has 16 flag registers among which 9 are active. The
purpose of the FLAGS register is to indicate the status of the processor.
It does this by setting the individual bits called flags. There are two
kinds of FLAGS;
Status FLAGS and Control FLAGS. Status FLAGS reflect the result of an
operation executed by the processor. The control FLAGS enable or
disable certain operations of the processor.

1.

Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you
add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0.
2.
Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and
to 0 when there is odd number of one bits.
3.

Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits).

4.

Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0.

5.
Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to0. (This flag
takes the value of the most significant bit.)
6.

Trap Flag (TF) - Used for on-chip debugging.

7.
Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external
devices.
8.
Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is
set to 0 - the processing is done forward, when this flag is set to 1the processing is done backward.
9.
Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add
bytes 100 + 50 (result is not in range -128...127).

Intel 8086 microprocessor architecture

Memory
Program, data and stack memories occupy the same memory space. The total addressable memory
size is 1MB KB. As the most of the processor instructions use 16-bit pointers the processor can

effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special
segment registers to specify where the code, stack and data 64 KB segments are positioned within 1
MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
32-bit addresses are stored in "segment:offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment:offset pair is calculated as:
address = (<segment> * 16) + <offset>
Program memory - program can be located anywhere in memory. Jump and call instructions can be
used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere
within 1 MB of memory. All conditional jump instructions can be used to jump within approximately
+127 - -127 bytes from current instruction.
Data memory - the 8086 processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing
instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES
or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two memory accesses
to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries
requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations:
0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in
format segment:offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h
address.

Interrupts
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of the
POPF instruction. When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing
routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow

Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.
Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode (type
7).
Software interrupt processing is the same as for the hardware interrupts.

I/O ports

65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.

Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four
different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of
processor memory these 4 segments are located the 8086 microprocessor uses four segment
registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by instruction
pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated
during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer
(BP) registers is located in the stack segment. SS register can be changed directly using POP
instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment. DS register can be changed directly using POP
and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program
data. By default, the processor assumes that the DI register references the ES segment in string
manipulation instructions. ES register can be changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by prefixing instructions
with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The
general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and
used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains
the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as a
16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the highorder byte. BX register usually contains a data pointer used for based, based indexed or register
indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a
16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH
contains the high-order byte. Count register can be used as a counter in string manipulation and
shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a
16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH
contains the high-order byte. Data register can be used as a port number in I/O operations. In integer
32-bit multiply and divide instruction the DX register contains high-order word of the initial or
resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used
for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is
even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last
result calculation.

Instruction Set

Instruction set of Intel 8086 processor consists of the following instructions:

Data moving instructions.
Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.
Logic - AND, OR, exclusive OR, shift/rotate and test.
String manipulation - load, store, move, compare and scan for byte/word.
Control transfer - conditional, unconditional, call subroutine and return from subroutine.
Input/Output instructions.
Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is located. This
addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the
resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI),
the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of
a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location
where data resides.