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2. PHOTOVOLTAIC SYSTEMS
2.1 BLOCK DIAGRAM OF PV SYSTEM
b
c
solar radiation.
Region containing a drift field for charge separation, and
Charge collecting front and back electrodes.
The photo-voltaic effect can be described easily for p-n junction in a semiconductor. In an intrinsic semi-conductor such as silicon, each one of the four valence
electrons of the material atom is tide in a chemical bond, and there are no free
electrons at absolute zero. If a piece of such a material is doped on one side by a five
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The most normal configuration for a solar cell to make a p-n junction semi
conductor is sunlight. This p-n junction is usually obtained by putting a p- type base
material into a diffusion furnace containing a gaseous n-type dopant such as
phosphorus and allowing the n-dopant to diffuse into the surface about 0.2m. The
junction is thus formed slightly below the planer surface of the cell and the light
impinges perpendicular to the junction. The positive and negative charges created by
the absorption of photons are thus encouraged to drift to the front and back of the
solar cell. The back is completely covered by a metallic contact to remove the charges
to the electric load. The collection of charges from the front of the cell is aided by a
fine grid of narrow metallic fingers. The surface coverage of the conducting collectors
is typically about 5% in order to allow as much light as possible to reach active
junction area. An antireflective coating is applied on the top of the cell. The p-n
junction provides an electrical field that sweeps the electrons in one direction and the
positive holes in the other. If the junction is in thermodynamic equilibrium, then the
Fermi energy must be uniform throughout. Since the Fermi level is near the top of the
gap of an n-doped material and near the bottom of the p-doped side, an electric field
must exist at the junction providing the charge separation function of the cell.
Important characteristics of the Fermi level is that, in thermodynamic equilibrium, it
is always continuous across the contact between the two materials.
2.1.1(D) Conversion efficiency and power output
A solar cell usually uses a p-n junction its physical configuration is shown
schematically in fig.2.3.
I i =I o exp
Ve
1
KT
(2.1)
Where
IoSaturation current also called the dark current and is applied when a large
negative voltage is applied across the diode.
V Voltage across junction.
e Electronic charge
k Boltzmanns constant
T Absolute temperature
When light impinges on the junction, electron hole pairs are created at a
constant rate providing an electrical flow across the junction. The net current is thus
the difference between the normal diode current and light generated current IL. The
internal series resistance Rs is mostly due to the high sheet resistance of the diffused
layer which is in series with the junction. The light generated current acts as a
constant current source supplying the current to either the junction or a useful load
depending on the junction characteristic and the value of the external load resistance.
The net current I is given by
Ve
(2.2)
1
KT
The internal voltage drop in a cell can usually be minimized, and for ideal cell Rs may
I =I L I i =I L I o exp
be assumed equal to zero i.e. Rs=0. With these the corresponding I-V plot is given in
figure. Open circuit voltage Voc for the ideal cell is then given by
I
KT
V oc =
ln L +1 (2.3)
e
IO
Since IL>>Io, the 1 in the equation can be neglected. Then open circuit voltage
I
KT
V oc =
ln L ( 2.4)
e
IO
In practice the open circuit voltage of the cell decreases with increasing temperature.
The maximum power that can be derived from the device is given by
Pmax=Vmp.Imp
(2.5)
[ ]
[ ]
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Thus
V mp I mp
(2.6)
Psun
=
I L EG
eP sun
( )(
V mp I mp
I l V OC
eV OC
EG
)( )
FF
(2.8)
A typical value of the fill factor for a good silicon cell is about 0.8.The voltage factor
(eVoc/Eg) is determined by the basic properties of the materials in the cell and typically
about 0.5 for a silicon cell.
2.1.2
Blocking diode
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A Blocking Diode which lets the array generated power flow only toward the
battery or grid. Without a blocking diode the battery would discharge back through
the solar array during times of no insulation.
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Single-crystal silicon
Single-crystal silicon cells are the most common in the PV industry. The main
technique for producing single-crystal silicon is the Czochralski (CZ) method. Highpurity polycrystalline is melted in a quartz crucible. A single-crystal silicon seed is
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dipped into this molten mass of polycrystalline. As the seed is pulled slowly from the
melt, a single-crystal ingot is formed. The ingots are then sawed into thin wafers
about 200-400 micrometers thick (1 micrometer = 1/1,000,000 meter). The thin
wafers are then polished, doped, coated, interconnected and assembled into modules
and arrays [6].
Polycrystalline silicon
Consisting of small grains of single-crystal silicon, polycrystalline PV cells are less
energy efficient than single-crystalline silicon PV cells. The grain boundaries in
polycrystalline silicon hinder the flow of electrons and reduce the power output of the
cell. A common approach to produce polycrystalline silicon PV cells is to slice thin
wafers from blocks of cast polycrystalline silicon. Another more advanced approach is
the ribbon growth method in which silicon is grown directly as thin ribbons or
sheets with the approach thickness for making PV cells [6].
complex material and toxic in nature so the manufacturing process face some problem
[6].
2.4 CHARACTERISTICS OF PV CELL
(2.9)
(2.10)
[ (
I =I p h I O . exp
) ][
V + I RS
V +I RS
1
(2.11)
VT
Rp
Where, Iph is the Insolation current, I is the Cell current, Io is the Reverse saturation
current, V is the Cell voltage, Rs is the Series resistance, Rp is the Parallel resistance,
VT is the Thermal voltage (KT/Q ), K is the Boltzmann constant, T is the Temperature
in Kelvin, q is the Charge of an electron.
2.4.1 EFFICIENCY OF PV CELL
The efficiency of a PV cell is defined as the ratio of peak power to input solar power.
V mp . I mp
KW
I
. A( m2 )
2
m
( )
(2.12)
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where, Vmp is the voltage at peak power, Imp is the current at peak power, I is the
solar intensity per square metre, A is the area on which solar radiation fall.
The efficiency will be maximum if we track the maximum power from the PV
system at different environmental condition such as solar irradiance and temperature
by using different methods for maximum power point tracking.
2.5 MODELLING OF PV ARRAY:
The building block of PV arrays is the solar cell, which is basically a p-n junction that
directly converts light energy into electricity: it has a equivalent circuit as shown
below in Figure 2.8.
I =n p I ph n p I rs
[( )]
q
V
KTA
exp
1 ( 2.13)
ns
where I is the PV array output current; V is the PV array output voltage; ns is the
number of cells in series and np is the number of cells in parallel; q is the charge of an
electron; k is the Boltzmanns constant; A is the p-n junction ideality factor; T is the
cell temperature (K); Irs is the cell reverse saturation current. The factor A in equation
(2.13) determines the cell deviation from the ideal p-n junction characteristics; it
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ranges between 1-5 but for our case A=2.46 [3]. The cell reverse saturation current
Irs varies with temperature according to the following equation:
I rs =I rr
q EG 1 1
T 3
exp
(2.14)
Tr
KA T r T
( ) ( [
])
Where Tr is the cell reference temperature, Irr is the cell reverse saturation
temperature at Tr and EG is the band gap of the semiconductor used in the cell.
The temperature dependence of the energy gap of the semi conductor is given by [25]:
2
T
(
)
EG =EG 0
T +
(2.15)
The photo current Iph depends on the solar radiation and cell temperature as follows:
I ph= [ I scr + K i ( T T r ) ]
s
(2.16)
100
where Iscr is the cell short-circuit current at reference temperature and radiation, Ki
is the short circuit current temperature coefficient, and S is the solar radiation in
mW/cm2. The PV power can be calculated using equation (2.17) as follows:
q
V
KTA
P=IV =n p I ph V [
1]
ns
(2.17)
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Fig 2.10: I-V characteristic of a solar array for a fixed temperature but varying irradiance
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Fig 2.11: P-V characteristic of a solar array for a fixed temperature but varying irradiance
Fig 2.12: I-V Characteristic of a PV array under a fixed irradiance but varying temperatures
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Fig 2.13: P-V Characteristic of a PV array under a fixed irradiance but varying temperatures
From the I-V and P-V curves, we observe that the short circuit current
increases with increase in irradiance at a fixed temperature. Moreover, from the I-V
and P-V curves at a fixed irradiance, it is observed that the open circuit voltage
decreases with increase in temperature.
3. CONVERTERS
3.1 DC-DC CONVERTERS
DC-DC converters can be used as switching mode regulators to convert an
unregulated dc voltage to a regulated dc output voltage. The regulation is normally
achieved by PWM at a fixed frequency and the switching device is generally BJT,
MOSFET or IGBT. The minimum oscillator frequency should be about 100 times
longer than the transistor switching time to maximize efficiency. This limitation is due
to the switching loss in the transistor. The transistor switching loss increases with the
switching frequency and thereby, the efficiency decreases. The core loss of the
inductors limits the high frequency operation. Control voltage Vc is obtained by
comparing the output voltage with its desired value. Then the output voltage can be
compared with its desired value to obtain the control voltage Vcr. The PWM control
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signal for the dc converter is generated by comparing Vcr with a saw tooth voltage Vr.
There are four topologies for the switching regulators: buck converter, boost
converter, buck-boost converter, and Cuk converter. However my project work deals
with the boost regulator and further discussions will be concentrated towards this one.
3.1.1 BOOST CONVERTER AND ITS OPERATION
The figure (3.1) below shows a step up or PWM boost converter. It consists of a dc
input voltage source Vg; boost inductor L, controlled switch S, diode D, filter
capacitor C, and the load resistance R. When the switch S is in the on state, the
current in the boost inductor increases linearly and the diode D is off at that time.
When the switch S is turned off, the energy stored in the inductor is released through
the diode to the output RC circuit.
(b) ON STATE:
In the ON state, the circuit diagram is as shown below in Figure (3.3):
Vo=Vg/(1-D)
Conversion ratio, M=Vo/Vg=1/(1-D)
(3.1)
(3.2)
The boost converter operates in CCM (continuous conducting mode) for L> Lb where
Lb =
( 1D ) 2 DR
(3.3)
2f
The current supplied to the output RC circuit is discontinuous. Thus a large filter
capacitor is used to limit the output voltage ripple. The filter capacitor must provide
the output dc current to the load when the diode D is off.
The minimum value of the filter capacitance that results in the voltage ripple Vr is
given by:
Cmin =
DVO
(3.4)
V O RF
3.2 INVERTERS
The inverter provides ac Load voltage from a dc Voltage source. The semiconductor switches can be BJTs, thyristors, Mosfets, IGBTs etc. The choice of
power switch will depend on rating requirements and ease with which the
device can be turned on and off. A single-phase inverter will contain two or
four power switches arranged in half-bridge or full-bridge topologies. Halfbridges have the maximum ac voltage limited to half the value of the full dc
Source voltage and may need a centre tapped source. Full-bridges have the full dc
Source voltage as the maximum ac Voltage Where the dc Source voltage is low, e.g.
12V or 24V, the voltage drop across the conducting power switches is
significant and should be taken into account both in calculation and in selection
of the switch. The ac load voltage of the inverter is essentially a square wave,
but pulse- width-modulation methods can be used to reduce the harmonics and
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produce a quasi-sine wave. If higher ac Voltages than the dc source voltage are
required, then the inverter will require a step-up transformer. The output frequency
of the inverter is controlled by the rate at which the switches are turned on
and off, in other words by the pulse repetition frequency of the base, or gate,
driver circuit. Thyristors would only be used in very high power inverters,
since on the source side there is no voltage zero, and a forced commutation
circuit would be required to turn the thyristor off. Some typical single-phase
inverters are considered in the following sections. The switching device shown is a
BJT, but could be any switch, the choice being determined by availability of
required rating and ease of turn-on and turn-off. Care must be taken not to
have two switches 'on' together, shorting out the dc source. There must be
either a dead-time between switches or an inhibit circuit to ensure this does
not happen.
The main objective of static power converters is to produce an ac output waveform
from a dc power supply. These are the types of waveforms required in adjustable
speed drives (ASDs), uninterruptible power supplies (UPS), static var compensators,
active lters, exible ac transmission systems (FACTS), and voltage compensators,
which are only a few applications. For sinusoidal ac outputs, the magnitude,
frequency, and phase should be controllable. According to the type of ac output
waveform, these topologies can be considered as voltage source inverters (VSIs),
where the independently controlled ac output is a voltage waveform. These structures
are the most widely used because they naturally behave as voltage sources as required
by many industrial applications, such as adjustable speed drives (ASDs), which are
the most popular application of inverters; see Fig. Similarly, these topologies can be
found as current source inverters (CSIs), where the independently controlled ac output
is a current waveform. These structures are still widely used in medium-voltage
industrial applications, where high-quality voltage waveforms are required.
3.3 SINGLE-PHASE VOLTAGE SOURCE INVERTER
Single-phase voltage source inverters (VSIs) can be found as half-bridge and
full-bridge topologies. Although the power range they cover is the low one, they are
widely used in power supplies, single-phase UPSs, and currently to form elaborate
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high-power static power topologies, the main features of both approaches are
reviewed and presented in the following
3.3.1 Half-Bridge VSI
Fig3.6 shows the power topology of a half-bridge VSI, where two large
capacitors are required to provide a neutral point N, such that each capacitor
maintains a constant voltage vi/2. Because the current harmonics injected by the
operation of the inverter are low-order harmonics, a set of large capacitors (C+ andC-)
is required. It is clear that both switches S+ and S- cannot be on simultaneously
because a short circuit across the dc link voltage source vi would be produced. There
are two dened (states 1 and 2) and one undened (state 3) switch state as shown in
Table 3.1. In order to avoid the short circuit across the dc bus and the undened ac
output voltage condition, the modulating tech- nique should always ensure that at any
instant either the top or the bottom switch of the inverter leg is on.
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order to generate the given waveforms is done by the modulating technique that
should ensure the use of only the valid states.
TABLE 3.4 Valid switch states for a three-phase CSI
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