Abstract: Ultra-low power Phase Locked Loops

(PLL) is desired in various wireless applications

where power consumption and reliability are
important performance metrics. This paper
proposes a low power PLL employing charge
recycling technique for ZigBee application.
Design challenges in this technique are
addressed which include adaptive body biasing.
The PLL is implemented in 180nm CMOS. The
power dissipation at 1.2 V power supply is
1.3mW (including buffers).
I.

INTRODUCTION

Power consumption is very important in low

cost, low data rate and short range
communications such as ZigBee, Bluetooth and
wireless sensor networks, where battery lifetime
is critical. Due to the small output power of the
power amplifiers, the power consumption of
such system is easily dominated by a PLL based
frequency synthesizer which generates a
frequency in GHz range. To reduce the power
consumption, low voltage design has been
widely adopted. Although power consumption
can be reduced with low voltage circuits, a DCDC converter is required if the overall system
works at a higher power supply. For low power
and low cost systems, power and overhead of
the DC-DC converter can be significant. Hence,
reducing the current consumption at the nominal
supply voltage is desirable for integration with
the overall system that uses a single supply
voltage without the need for DC-DC converters.
An effective way to reduce the current
consumption at nominal power supply is to
employ charge recycling technique as shown in
Fig. 1. By stacking two low voltage circuits, the
top circuit works as the DC-DC converter for the
bottom circuit. Power consumption can be
reduced as there is no wastage of power in the
DC-DC converter and as the charge used by the
top circuit is recycled in the bottom circuit.

Fig.1. Basic structure of a charge recycling

system
Charge recycling technique suffers from a
charge imbalance problem. When the current
consumption of top and bottom circuits are the
same, a mid-voltage (VMID) stays at a desired
voltage. However they are different in practice
due to different inputs and mismatch. If the
current at the top circuit is larger than that of the
bottom circuit, the mid-voltage will be increased
since all the current from the top circuit is not
consumed in the bottom circuit and thereby
remained current charges the node at the midvoltage [].
In this paper a low power PLL using charge
recycling technique, in 180nm CMOS is
proposed. This paper is organized as follows.
Section II presents the charge recycling PLL.
Section III deals with the individual blocks in
detail. Simulation results are shown in Section
IV. Section V concludes and summarizes this
paper.
II.

CHARGE RECYCLING PLL

Fig.2. Bloc k Diagram of PLL

The block diagram of the proposed synthesizer

is shown in Fig. 2. A 4.8GHz VCO is followed
by a divide-by-2 to generate quadrature signals
at 2.4GHz. To minimize the power consumption,
VCO and divide-by-2 are designed for low
voltage charge recycling operation. In order to
reduce the switching noise from the top circuit, a
decoupling capacitor is added at the intermediate
node [].
A high speed phase frequency detector (PFD)
which reduces the power consumption and jitter
is designed. The PFD high speed is achieved by
detection of both rising and falling edges of
input signals []. Charge pump circuits using a
current bypass technique, which suppresses
charge sharing and reduces the sub-threshold
currents is used [].
In order to avoid variation of VMID, several
techniques are employed in designing the VCO
and the divide-by-2, which are the two most
power hungry circuits of the synthesizer. First a
self biased scheme is used in the divide-by-2 so
that the variation in the VMID is minimized. As
shown in Fig. , the output of the VCO is directly
connected to the input of divide-by-2 and hence
the DC bias of the NMOS dynamic loads is
VMID. If the current of the top VCO is larger than
the bottom divide-by-2, VMID will increase which
in turn will reduce the current demand of the
VCO. As the current demand is reduced, VMID
will decrease, hence minimizing its variation.
Such negative feedback enables robust operation
to PVT variation. Second, an adaptive bodybiasing technique is also employed to improve
its robustness at low supply voltage [].

The programmable divider uses extended true

single phase clock (E-TSPC) logic for high
speed and TSPC logic for low speed and low
power consumption. The modulus control signal
is sampled by the output of the dual modulus
prescaler so that the effective delay of the
control signal is kept constant regardless of the
divider modulus [].
III.

PLL ARCHITECTURE

A. PFD: Phase frequency detector shown

in Fig. 3 is the very first block of the
PLL. It is very important block for PLL.
PFD having two inputs clock
reference (CLKREF) and clock from
programmable divider (CLKDIV).Two
outputs UP signal and DN signal.
Input to the PFD is from the reference
clock and second input is from the
feedback
signal
coming
from
programmable divider. The outputs are
connected to the charge pump to
generate the related control signal for
VCO [].

Fig. 3 High Speed PFD

B. Charge Pump and Low Pass Filter:
The charge-pump circuit using current
bypass technique is shown in Fig. 4.
Two current bypasses are attached to the
original circuit. The UP-current bypass
consists of MN4, MN5, MP6, MP1
transistors. The DN-current bypass
consists of MP4, MP5, MN6, and MN1
transistors.

VDS of MN2 is nearly zero. Therefore, the

sub-threshold currents of the proposed
circuit are reduced to be similar to those of
the charge-pump circuit with a unity-gain
amplifier.
When UP becomes 1 and switch transistor
MP2 in the main UP-current path turns on,
node pc starts with a voltage close to Vctrl.
When DN becomes 1 and switch transistor
MN2 in the main DN-current path turns on,
node nc starts with a voltage close to Vctrl.
Therefore, very little charge-sharing can
occur []. A third order low pass filter is used
followed by the charge pump.
C. VCO and Divide-by-2:

Fig. 4 Charge Pump using current bypass

technique
The transistors in the same row have the
same transistor sizes as in Eq. (1).
(W/L)MP1 = (W/L) MP4,
(W/L)MP2 = (W/L) MP5 = (W/L) MP6,

(1)

(W/L)MN2 = (W/L) MN5 = (W/L) MN6 and

(W/L)MN1 = (W/L) MN4.
When UP = DN = 0, both the current
bypasses turn ON and the drain voltages of
the transistors in both the current bypasses
are close to Vctrl since MN5, MP6, MP5,
and MN6 transistors operate in linear region
with small turn-on resistance. So the
voltages of nodes pc and nc stay close to
Vctrl. VGS of MN2 is close to Vctrl and

Fig. 5 Circuit of Charge Recycling QVCO

The schematic of the proposed QVCO is
shown in Fig. 5. The target of the design is
to operate at 2.4 GHz, but for low power
consumption, a VCO generating 4.8GHz

frequency is followed by a divide-by-2

block. For the generation of the quadrature
signals, the divide-by -2 is implemented in
current mode logic (CML). The VCO is
based on complementary LC-tank oscillator,
which consists of two inductors (L), two Ptype metal oxide semiconductor FET
(PMOS) to generate the signal. At the
differential outputs of the VCO, V+ and V-,
the output frequency of VCO is used for
upper band operation. A varactor CVAR is
connected between V+ and V- and tuned by
DC voltage. Adaptive body biasing
technique is employed for robustness at low
supply voltage.
The divide-by-2 is the CML static frequency
divider. In order to minimize the number of
the stacked transistors between two supply
rails, the divide-by-2 is built without current
source. The quadrature signals generation
with the divide-by-2 has the better phase and
amplitude match.

flop to reduce propagation delay and current

consumption.

Fig. 6 Block Diagram of Programmable

Divider

Fig.7 Implementation of 2/3 cell

D. Programmable divider:
The chosen RF application targets the 2.4
GHz ISM band. This requires the VCO and
divider to operate nominally at 4.8 GHz (to
generate I and Q components at 2.4 GHz).
The block diagram of the programmable
divider is shown in Fig. 6.
The synthesizer input frequency comes from
a 5 MHz crystal oscillator. The required
division factor (N) is nominally 480-496, so
the design requires eight divide-by-2/3 cells.
The design uses only True single phase
clocking (TSPC) flops rather than Sourcecoupled logic (SCL) flops. The internal
topological details of the 2/3 cell are shown
in fig. 7 and 8. The combinational logic,
except for an inverter, is absorbed inside the

Fig. 8 Implementation of TSPC flop

IV.

SIMULATION RESULTS

The Phase Locked Loop has been

implemented in 180nm CMOS. The tuning
characteristics of the PLL are shown in Fig.
9.