8997

Application Notes

16x2 LCD Dot Matrix

Module

The DMX can be interfaced with most microprocessors.

Interface with 68XX Series

Initialisation Routine
restat:

LDS
LDAB
LDX
JSR
LDAA
STAA
INX
DECB
BNE
BYTE
BYTE
BYTE
BYTE
BYTE

Figure 5
R/W

R/W

A0
A14
A15
VMA
2
DB0
DB7

A0

re1:

Indat:

E
DB0
DB7

Instruction Leaflet

#$7F
#$5
#indat
busy
O,X
DMX1

RS stock no. 312-319

re1
$38
$38
$06
$0C
$01

*********DMX BUSY?******

LCD
Module

busy:
busy1:

Interface with 80XX Series

PSHA
LDAA
BMI
PULA
RTS

MOV
MOV

Figure 6
RD

ACALL
MOVX
MOV
ACALL
MOVX
MOV

80XX
WX

DB7

R/W
74LS373

ACALL
MOVX
MOV

RS

1D 1Q
EN
5Q
6Q
8D 7Q
8Q

DMX1
busy 1

Initialisation Routine
Init:

ALE
DB0

8997

Issued November 1991

DB0
DB7
ACALL
MOVX
MOV
ACALL
MOVX
RET

LCD
Module

DPTR,#DMX1
A.#038H
Function set:-Two
Line (Sent Twice)
busy
@DPTR,A
A,#038H
;Function Set
busy
@DPTR,A
A,#06H
;Entry Mode:Cursor moves Right
busy
@DPTR.A
A,#0CH
:Display Control:Display on, Cursor
off - No Blink of
Cursor Position.
busy
@DPTR,A
A,#02H
; Home Cursor
busy
@DPTR,A

*********CHECK DMX BUSY FLAG*********

busy:

flagin:

PUSH
PUSH
PUSH
MOV
MOVX
JB

ACC
DPH
DPL
DPTR,#DMX1
A,@DPTR
ACC.07H.flagin

;Read Busy
Flag until b7=0

The information provided in RS instruction leaflet is believed to be accurate and reliable; however, RS Components assumes no
responsibility for inaccuracies or omissions, or for the use of this information, and all use of such information shall be entirely at the
users own risk. No responsibility is assumed by RS Components for any infringements of patents or other rights of third parties which
may result from its use. Specifications shown in RS Components instruction leaflets are subject to change without notice.

RS Components, PO Box 99, Corby, Northants, NN17 9RS

An Electrocomponents Company

Telephone: 01536 201234

RS Components 1996

HD 44780 Compatible Interface

Robust Construction

Back-light

Bezel

Easy to Install

The DMX sets new standards for dot matrix displays. Of compact and robust construction, it can be
bolted in place or panel mounted using bezel (supplied complete with clips and window). The
interface is compatible with the Hitachi LCDII/IIA standard and connection is via a 16 way ribbon
cable connector (this is in the popular 14 pin format but with extra pins for the back-light). The unit
can be optionally back-lit with a simple 5V supply.

Item
Input High Voltage
Input Low Voltage

Symbol

Min.

VIH

Max.

Unit

2.2

Vdd

0.6

VIL

-0.3

Output High Voltage

VOH

2.4

Output Low Voltage

VOL

Power Supply Voltage

Vdd

Power Supply Current

Idd

Contrast Control

Vee

Typ.

V
V

0.4

5.5

0.5

mA

Vdd

Backlight Supply Voltage

5.5

Backlight Supply Current

50

90

mA

4.5

-1.0

8997

8997
Display ON/OFF Control
D. Display is turned ON when D=1 and OFF when D=0. When the display is turned off due to
D=0, the display data remains in the DD RAM and it can be displayed immediately by setting
D=1.

Figure 1.
d e f
3.2
(0.12)
24.4 (0.96)

24.1 (0.95)

39.(1.53)

71.5 (2.81)

5.55 (0.22)

51.3 (2.02)

+5V
RS
E
D1
D2
D6
D7
LMP+

Rear
View

0V
Vee
R/W
D0
D2
D4
D8
LMP-

C.

B. The character residing at the cursor position blinks when B=1/ The blink is done by switching
between all the black dots and display characters at 0.4 second intervals. The cursor and the
blink can be set concurrently.

5.7
(0.22)

61.4 (2.42)

The cursor is displayed when C=1 and not displayed when C=0. Even if the cursor
disappears, the function of I/D etc. does not change during display data write. The cursor is
displayed using 5 dots in the 8th line when the 5x7 character font is selected.

Panel cut-out 72 x 40 (2.83 x 1.57).

Maximum panel thickness 3 mm.

Function Set
The DMX can be operated in a four or eight bit data entry mode.

76.5 (3.01)
72.5 (2.85)

24 (0.94)

44 (1.73)

40.5 (1.59)

DL=1.
DL=0.
N.

a. 2.00 (0.08)
b. 6.50 (0.25)
c. 1.00 (0.04)
d. 9.80 (0.38)
e. 1.50 (0.06)
f. 9.50 (0.37)

ab

51 (2.00)

Set CG RAM Address

Sets the CG RAM address in a binary number of ACG in the address counter. All data read/write
operations access the CG RAM afterwards.
Set DD RAM Address
Sets the DD RAM address in a binary number of ADD in the address counter. All data read/write
operations access the DD RAM afterwards.

Pin function
1.
2.
3.

0V.
+5V
Vee.

4.
5.
6.
7-14.
15.
16.

RS
R/W
E.
D0-D7.
LampLamp+

LCD contrast control input

(see Diagram)
Register Select input.
Read/Write input.
Enable signal.
8 Bit bi-directional p data bus.
} Back light supply, max. 90mA.

Item

Read Busy Flag and Address

This instruction will read the busy flag and either the DD AOR CG address (determined by the
previous Address Set).

+5V

}Power supply.

10-20kW

Vee

BF=1.
The DMX is busy executing the previous instruction. The next instruction will not be
accepted until BF=0. The address contents (AC) are those of CG RAM and DD RAM previously
shown.

0V

Standard Value

Symbol

Unit

Min.

Typ.

Max

tcycE

See READ and WRITE diagram

1000

nS

Enable Pulse Width, High Level

PWEH

See READ and WRITE diagram

450

nS

Enable Rise and Decay Time

tEr, tEf

See READ and WRITE diagram

25

nS

tAs

See READ and WRITE diagram

140

nS
nS

Enable Cycle Time

Address Setup Time, RS, R/W - E

Data Delay Time

tDDR

See WRITE diagram

320

Data Setup Time

tDSW

See READ diagram

195

nS

Data Hold Time

tH

See READ diagram

10

nS

Data Hold Time

tDHR

See WRITE diagram

20

nS

See READ and WRITE diagram

10

nS

Address Hold Time

tAH

Data is read or written in eight bit.

Data is read or written in four bits on DB7 - DB4. Upper nibble first, lower second.
Sets either 1-line (N-0) or 2-line (N=1) operation. Use N=1 for DMX.

Write Data to CG or DD RAM

Writes binary data to the CG or the DD RAM. Whether the CG or the DD RAM is to be written
into is determined by the previous Address Set. After write, the address is automatically
incremented or decremented by one according tot he entry mode. Display shift also follows the
entry mode.
Read Data from CG or DD RAM
Will read data from the CG or DD ram (determined by the previous Address Set). Ensure that the
required RAM address is set before executing this instruction. After the read instruction, the
address will automatically be incremented or decremented according to the entry mode. Display
shift, however, is not performed regardless of entry mode types.

8997

8997
Instructions

Figure 2. Font Table

lower
4 bit
0

Higher
4 bit

xxxx0000

0000

0010

0011

0100

0101

0110

0111

1010

1011

1100

1101

1110

1111

Code

CG
RAM
(1)

Instruction

RS

Clear Display

R/W DB
7
0

DB
6

DB
5

DB
4

DB
3

DB
2

DB
1

DB
0

(2)
1

Description

Execute
Time
(Max.)

Clears all display and returns

the cursor to the home position
(Address 0).

1.64mS

xxxx0001

Cursor at Home

01

(3)
2

xxxx0010

xxxx0011

xxxx0100

Entry Mode Set

1/D

(4)

Display On/Off Control

(5)

(6)
5

xxxx0101

*Characters with lower case

descenders eg , etc.
will only be partially displayed by the DMX

(7)
6

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

xxxx1011

xxxx1100

(8)

xxxx1111

Function Set

DL

S/C R/L
N

ACG

Sets ON/OFF of all display (D) cursor

ON/OFF (C), and blink of cursor
position character.

40S

Moves the cursor and shifts the display

without changing DD RAM contents.

40S

Sets interface data length (DL)

number of display lines (L) and
character font (F).

40S

Sets the CG RAM address. CG RAM

data is sent and received after this
setting.

40S

Sets the DD RA, address/ DD RAM is

sent and received after this setting

40S

BF

AC

(2)

Busy
Read

Reads Busy flag (BF) indicating internal

operation is being performed and reads
address counter contents

40S

CG RAM/DD RAM Data

Write

WRITE DATA

Writes data into DD RAM or CG RAM

40S

CG RAM/DD RAM Data

Read

READ DATA

Reads data from DD RAM or CG RAM.

40s

Clear Display Writes the space code (20 hex) to all DD RAM addresses. The cursor returns to Address 0 and the
display, if it has been shifted, will return to its original position. Because all the DD RAM contents
have 20 written to them, this instruction should not be used if general data is kept in Invisible DD
memory.

VIH1
VIL1
tAS

Figure 4. Read Operation

VIH1
VIL1
tAM
VIH1

VIH1

VOH1
VOL1

VIL1
tEr

tDHR

Valid data

VIL1

VOH1
VOL1

tcyc

(Write Data from MPU to Module)

DB0 - DB7

VIH1

VIH1
VIL1

Entry Mode Select

I/D: Increments (I/D=1) or decrements (I/D=0) the DD Ram address by one upon writing into or
reading from the DD RAM a character. The same applies when writing to and reading from the CG
RAM. The advantage of this instruction is that you do not need to set the DD RAM or CG RAM
address between each data entry if the data is sent in the correct order.
S: When S=0 the display stays still and the cursor moves to the left or right (CG RAM address up
or down) depending on I/D status.
When S=1 the cursor stays put but the display moves to the left or right according to I/D
status.
Writing or reading from CG RAM is not affected by S status.

tE

tDSW
VOH1
VOL1

VIL 1

tAM

PWEM
f

tE

tDDr

R/W

VIH1
VIL1
tAM

VIL 1

tAM
VIH1
VIL1

VIH1
VIL1
tAS

RS

VIH1

VIL1
tEr

Flag/Address

Instruction Explanations

PWEM

DB0 - DB7

1D

ADD

Figure 3. Write Operation

(8)

R/W

(7)

RS

40S

(6)

xxxx1110

Sets the cursor move direction and

specifies or not to shift the display.
These operations are performed
during data write and read.

DD RAM Address Set

(5)

1.64mS

(1)

(4)

xxxx1101

Cursor/Display Shift

CG RAM Address Set

(3)

Returns the cursor to the

home position (Address 0).
Also returns the display being
shifted to the original position. DD

Cursor or Display Shift

The instruction will shift either the cursor or the display to the right or the left without writing to or
reading from the display. It has to be executed for as many times as shifts are required.
S/C=1
The display shifts.
R/C = 1 Shift to the right.
S/C=0
The cursor shifts
R/L = 0 Shift to the left.

tH

Valid data

VOH1
VOL1

tcyc

(Reading Data from Module to MPU)

8997

8997
Instructions

Figure 2. Font Table

lower
4 bit
0

Higher
4 bit

xxxx0000

0000

0010

0011

0100

0101

0110

0111

1010

1011

1100

1101

1110

1111

Code

CG
RAM
(1)

Instruction

RS

Clear Display

R/W DB
7
0

DB
6

DB
5

DB
4

DB
3

DB
2

DB
1

DB
0

(2)
1

Description

Execute
Time
(Max.)

Clears all display and returns

the cursor to the home position
(Address 0).

1.64mS

xxxx0001

Cursor at Home

01

(3)
2

xxxx0010

xxxx0011

xxxx0100

Entry Mode Set

1/D

(4)

Display On/Off Control

(5)

(6)
5

xxxx0101

*Characters with lower case

descenders eg , etc.
will only be partially displayed by the DMX

(7)
6

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

xxxx1011

xxxx1100

(8)

xxxx1111

Function Set

DL

S/C R/L
N

ACG

Sets ON/OFF of all display (D) cursor

ON/OFF (C), and blink of cursor
position character.

40S

Moves the cursor and shifts the display

without changing DD RAM contents.

40S

Sets interface data length (DL)

number of display lines (L) and
character font (F).

40S

Sets the CG RAM address. CG RAM

data is sent and received after this
setting.

40S

Sets the DD RA, address/ DD RAM is

sent and received after this setting

40S

BF

AC

(2)

Busy
Read

Reads Busy flag (BF) indicating internal

operation is being performed and reads
address counter contents

40S

CG RAM/DD RAM Data

Write

WRITE DATA

Writes data into DD RAM or CG RAM

40S

CG RAM/DD RAM Data

Read

READ DATA

Reads data from DD RAM or CG RAM.

40s

Clear Display Writes the space code (20 hex) to all DD RAM addresses. The cursor returns to Address 0 and the
display, if it has been shifted, will return to its original position. Because all the DD RAM contents
have 20 written to them, this instruction should not be used if general data is kept in Invisible DD
memory.

VIH1
VIL1
tAS

Figure 4. Read Operation

VIH1
VIL1
tAM
VIH1

VIH1

VOH1
VOL1

VIL1
tEr

tDHR

Valid data

VIL1

VOH1
VOL1

tcyc

(Write Data from MPU to Module)

DB0 - DB7

VIH1

VIH1
VIL1

Entry Mode Select

I/D: Increments (I/D=1) or decrements (I/D=0) the DD Ram address by one upon writing into or
reading from the DD RAM a character. The same applies when writing to and reading from the CG
RAM. The advantage of this instruction is that you do not need to set the DD RAM or CG RAM
address between each data entry if the data is sent in the correct order.
S: When S=0 the display stays still and the cursor moves to the left or right (CG RAM address up
or down) depending on I/D status.
When S=1 the cursor stays put but the display moves to the left or right according to I/D
status.
Writing or reading from CG RAM is not affected by S status.

tE

tDSW
VOH1
VOL1

VIL 1

tAM

PWEM
f

tE

tDDr

R/W

VIH1
VIL1
tAM

VIL 1

tAM
VIH1
VIL1

VIH1
VIL1
tAS

RS

VIH1

VIL1
tEr

Flag/Address

Instruction Explanations

PWEM

DB0 - DB7

1D

ADD

Figure 3. Write Operation

(8)

R/W

(7)

RS

40S

(6)

xxxx1110

Sets the cursor move direction and

specifies or not to shift the display.
These operations are performed
during data write and read.

DD RAM Address Set

(5)

1.64mS

(1)

(4)

xxxx1101

Cursor/Display Shift

CG RAM Address Set

(3)

Returns the cursor to the

home position (Address 0).
Also returns the display being
shifted to the original position. DD

Cursor or Display Shift

The instruction will shift either the cursor or the display to the right or the left without writing to or
reading from the display. It has to be executed for as many times as shifts are required.
S/C=1
The display shifts.
R/C = 1 Shift to the right.
S/C=0
The cursor shifts
R/L = 0 Shift to the left.

tH

Valid data

VOH1
VOL1

tcyc

(Reading Data from Module to MPU)

8997

8997
Display ON/OFF Control
D. Display is turned ON when D=1 and OFF when D=0. When the display is turned off due to
D=0, the display data remains in the DD RAM and it can be displayed immediately by setting
D=1.

Figure 1.
d e f
3.2
(0.12)
24.4 (0.96)

24.1 (0.95)

39.(1.53)

71.5 (2.81)

5.55 (0.22)

51.3 (2.02)

+5V
RS
E
D1
D2
D6
D7
LMP+

Rear
View

0V
Vee
R/W
D0
D2
D4
D8
LMP-

C.

B. The character residing at the cursor position blinks when B=1/ The blink is done by switching
between all the black dots and display characters at 0.4 second intervals. The cursor and the
blink can be set concurrently.

5.7
(0.22)

61.4 (2.42)

The cursor is displayed when C=1 and not displayed when C=0. Even if the cursor
disappears, the function of I/D etc. does not change during display data write. The cursor is
displayed using 5 dots in the 8th line when the 5x7 character font is selected.

Panel cut-out 72 x 40 (2.83 x 1.57).

Maximum panel thickness 3 mm.

Function Set
The DMX can be operated in a four or eight bit data entry mode.

76.5 (3.01)
72.5 (2.85)

24 (0.94)

44 (1.73)

40.5 (1.59)

DL=1.
DL=0.
N.

a. 2.00 (0.08)
b. 6.50 (0.25)
c. 1.00 (0.04)
d. 9.80 (0.38)
e. 1.50 (0.06)
f. 9.50 (0.37)

ab

51 (2.00)

Set CG RAM Address

Sets the CG RAM address in a binary number of ACG in the address counter. All data read/write
operations access the CG RAM afterwards.
Set DD RAM Address
Sets the DD RAM address in a binary number of ADD in the address counter. All data read/write
operations access the DD RAM afterwards.

Pin function
1.
2.
3.

0V.
+5V
Vee.

4.
5.
6.
7-14.
15.
16.

RS
R/W
E.
D0-D7.
LampLamp+

LCD contrast control input

(see Diagram)
Register Select input.
Read/Write input.
Enable signal.
8 Bit bi-directional p data bus.
} Back light supply, max. 90mA.

Item

Read Busy Flag and Address

This instruction will read the busy flag and either the DD AOR CG address (determined by the
previous Address Set).

+5V

}Power supply.

10-20kW

Vee

BF=1.
The DMX is busy executing the previous instruction. The next instruction will not be
accepted until BF=0. The address contents (AC) are those of CG RAM and DD RAM previously
shown.

0V

Standard Value

Symbol

Unit

Min.

Typ.

Max

tcycE

See READ and WRITE diagram

1000

nS

Enable Pulse Width, High Level

PWEH

See READ and WRITE diagram

450

nS

Enable Rise and Decay Time

tEr, tEf

See READ and WRITE diagram

25

nS

tAs

See READ and WRITE diagram

140

nS
nS

Enable Cycle Time

Address Setup Time, RS, R/W - E

Data Delay Time

tDDR

See WRITE diagram

320

Data Setup Time

tDSW

See READ diagram

195

nS

Data Hold Time

tH

See READ diagram

10

nS

Data Hold Time

tDHR

See WRITE diagram

20

nS

See READ and WRITE diagram

10

nS

Address Hold Time

tAH

Data is read or written in eight bit.

Data is read or written in four bits on DB7 - DB4. Upper nibble first, lower second.
Sets either 1-line (N-0) or 2-line (N=1) operation. Use N=1 for DMX.

Write Data to CG or DD RAM

Writes binary data to the CG or the DD RAM. Whether the CG or the DD RAM is to be written
into is determined by the previous Address Set. After write, the address is automatically
incremented or decremented by one according tot he entry mode. Display shift also follows the
entry mode.
Read Data from CG or DD RAM
Will read data from the CG or DD ram (determined by the previous Address Set). Ensure that the
required RAM address is set before executing this instruction. After the read instruction, the
address will automatically be incremented or decremented according to the entry mode. Display
shift, however, is not performed regardless of entry mode types.

8997
Application Notes

16x2 LCD Dot Matrix

Module

The DMX can be interfaced with most microprocessors.

Interface with 68XX Series

Initialisation Routine
restat:

LDS
LDAB
LDX
JSR
LDAA
STAA
INX
DECB
BNE
BYTE
BYTE
BYTE
BYTE
BYTE

Figure 5
R/W

R/W

A0
A14
A15
VMA
2
DB0
DB7

A0

re1:

Indat:

E
DB0
DB7

Instruction Leaflet

#$7F
#$5
#indat
busy
O,X
DMX1

RS stock no. 312-319

re1
$38
$38
$06
$0C
$01

*********DMX BUSY?******

LCD
Module

busy:
busy1:

Interface with 80XX Series

PSHA
LDAA
BMI
PULA
RTS

MOV
MOV

Figure 6
RD

ACALL
MOVX
MOV
ACALL
MOVX
MOV

80XX
WX

DB7

R/W
74LS373

ACALL
MOVX
MOV

RS

1D 1Q
EN
5Q
6Q
8D 7Q
8Q

DMX1
busy 1

Initialisation Routine
Init:

ALE
DB0

8997

Issued November 1991

DB0
DB7
ACALL
MOVX
MOV
ACALL
MOVX
RET

LCD
Module

DPTR,#DMX1
A.#038H
Function set:-Two
Line (Sent Twice)
busy
@DPTR,A
A,#038H
;Function Set
busy
@DPTR,A
A,#06H
;Entry Mode:Cursor moves Right
busy
@DPTR.A
A,#0CH
:Display Control:Display on, Cursor
off - No Blink of
Cursor Position.
busy
@DPTR,A
A,#02H
; Home Cursor
busy
@DPTR,A

*********CHECK DMX BUSY FLAG*********

busy:

flagin:

PUSH
PUSH
PUSH
MOV
MOVX
JB

ACC
DPH
DPL
DPTR,#DMX1
A,@DPTR
ACC.07H.flagin

;Read Busy
Flag until b7=0

The information provided in RS instruction leaflet is believed to be accurate and reliable; however, RS Components assumes no
responsibility for inaccuracies or omissions, or for the use of this information, and all use of such information shall be entirely at the
users own risk. No responsibility is assumed by RS Components for any infringements of patents or other rights of third parties which
may result from its use. Specifications shown in RS Components instruction leaflets are subject to change without notice.

RS Components, PO Box 99, Corby, Northants, NN17 9RS

An Electrocomponents Company

Telephone: 01536 201234

RS Components 1996

HD 44780 Compatible Interface

Robust Construction

Back-light

Bezel

Easy to Install

The DMX sets new standards for dot matrix displays. Of compact and robust construction, it can be
bolted in place or panel mounted using bezel (supplied complete with clips and window). The
interface is compatible with the Hitachi LCDII/IIA standard and connection is via a 16 way ribbon
cable connector (this is in the popular 14 pin format but with extra pins for the back-light). The unit
can be optionally back-lit with a simple 5V supply.

Item
Input High Voltage
Input Low Voltage

Symbol

Min.

VIH

Max.

Unit

2.2

Vdd

0.6

VIL

-0.3

Output High Voltage

VOH

2.4

Output Low Voltage

VOL

Power Supply Voltage

Vdd

Power Supply Current

Idd

Contrast Control

Vee

Typ.

V
V

0.4

5.5

0.5

mA

Vdd

Backlight Supply Voltage

5.5

Backlight Supply Current

50

90

mA

4.5

-1.0