Homework Assignment

Summer 2014

Homework #6
READING:
1. Hennessey / Patterson: 5.1 5.7
PROBLEM SET:
1. Cache Architectures
In this question you will explore the direct mapped cache, the set-associative cache and the fullyassociative cache. Below is a list of memory references given as byte addresses in hexadecimal.
A word is 4 bytes. A block contains 8 words. The addresses are 16 bits.
The main memory is 1024 kBytes.
004, 008, 00C, 010, 014, 044, 048, 105, 04C, 050, 018, 01C, 210, 020, 024, 018, 01C, 106, 018, 01C
a) Main Memory:
1. How many blocks are in main memory?
2. How many address bits are needed at minimum to address each byte of main memory?
b) Assume you have a direct mapped cache with 8 eight-word blocks and a total size of 64 words
which is initially empty. The cache uses the Dirty Bit.
1. What write strategy was chosen for this cache.
2. Show how a 16bit byte address would be split into tag, index, etc. for this cache.
3. What would be the size of this cache. Compute both, the size of the cache (number of bits stored in
cache) and the total number of bits needed to implement this cache (incl. tags, etc).
4. Label each reference in the list above as a hit or miss for this cache.
Hint: Use a table to see what is going on in cache. You may use a spreadsheet program.
5. Show the final content of this cache.
c) Assume you have a 2-way set-associative cache with 8-word blocks and a total size of 64 words
which are initially empty. Assume LRU (least recently used) replacement.
1. Show how a 16bit byte address would be split into tag, index, etc. for this cache.
2. What would be the size of this cache. Compute both, the size of the cache (number of bits stored in
cache) and the total number of bits needed to implement this cache (incl. tags, etc).
3. Label each reference in the list above as a hit or miss for this cache.
4. Show the final content of this cache.

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Homework Assignment

Summer 2014

d) Assume you have a fully associative cache with 8 words blocks and a total size of 64 words which
are initially empty. Assume LRU replacement.
1. Show how a 16bit byte address would be split into tag, index, etc. for this cache.
2. What would be the size of this cache. Compute both, the size of the cache (number of bits stored in
cache) and the total number of bits needed to implement this cache (incl. tags, etc).
3. Label each reference in the list above as a hit or miss for this cache.
4. Show the final content of this cache.
e) Compare the cache miss rate for all three cache implementations.
2. Cache Performance
The table below lists three different cache configurations for a processor with a single level of
cache and their associated miss rates. Assume that the base CPI for the processor is 2.0 and that
the cache miss penalty, in number of CPU clock cycles, is computed by the following formula:
(5 + block size in words) * 10
The processor executes a program in which 38% of the instructions contain data references.
Determine which cache configuration causes the processor to spend the most cycles on clock
misses. Determine the actual CPI for all cache configurations.

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Homework Assignment

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3. Cache Hierarchy
In the question below: 1 KB is 1024 byte, 1 word is 4 byte, 1 byte is 8 bit, etc.
A Processor runs at 2.5 Ghz and has a base CPI=1.8. It executes a program in which 28% of
instructions contain data references. Below is the data of the memory system.

a) Which cache scheme (direct mapped, set associative, fully associative) would you use for level 1
and level 2. Please state a reason. Remember what is most important at each level.
b) Assume that the level 1 cache is direct mapped. Show how a 32bit long byte address would be split
into tag, index, etc. for this cache and determine the number of blocks that this cache can store.
c) Assume that the level 2 cache is 4way set-associative. Show how a 32bit long byte address would
be split into tag, index, etc. for this cache and determine the number of blocks that this cache can store
and the number of sets that this cache has.
d) If the processor would have only the level 1 cache and NOT a level 2 cache, what would be its
total CPI?
e) What is the total CPI of this processor if it employs level 1 AND level 2 caches?
f) How much faster is the processor with 2 cache levels versus 1 cache level?

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Dr. Craig Lorie