Beruflich Dokumente
Kultur Dokumente
Description
45 m at VIN=5.5 V
55 m at VIN=3.3 V
90 m at VIN=1.8 V
185 m at VIN=1.2 V
Slew Rate Control with tR:
FPF1203/FPF1203l/FPF1204:
FPF12045: 2 s
100 s
Applications
Ordering Information
Switch
Output
(Typical)
Discharge
at 3.3VIN
Part Number
Top
Mark
FPF1203UCX
QL
55 m
FPF1203LUCX
QP
55 m
NA
Active LOW
100 s
FPF1204UCX
QM
55 m
65
Active HIGH
100 s
FPF1204BUCX
(Backside Laminate)
QM
55 m
65
Active HIGH
100 s
FPF12045UCX
NC
55 m
65
Active HIGH
2 s
NA
ON Pin
Activity
tR
Active HIGH
100 s
Package
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January 2013
Application Diagram
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2
VOUT
A1
A2
VIN
VIN
A2
A1
VOUT
GND
B1
B2
ON
ON
B2
B1
GND
Pin Definitions
Pin #
Name
Description
A1
VOUT
A2
VIN
B1
GND
B2
ON
B2
ON
Switch Output
Supply Input: Input to the power switch
Ground
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3
Pin Configurations
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
6.0
VIN
ISW
2.2
PD
1.0
+150
TSTG
JA
ESD
-65
1S2P with One Thermal Via
(1)
110
(2)
95
C/W
kV
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB COLD PLATE Method.
Symbol
Parameter
Min.
Max.
Unit
VIN
Input Voltage
1.2
5.5
TA
-40
+85
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4
Unless otherwise noted, VIN=1.2 V to 5.5 V and TA=-40 to +85C. Typical values are at VIN=3.3 V and TA=25C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
5.5
Basic Operation
VIN
Supply Voltage
1.2
IQ(OFF)
Off Supply
Current
0.1
1.0
FPF1203L
1.0
2.0
ISD
Shutdown
Current
0.1
1.0
FPF1203L
1.2
3.0
IQ
Quiescent
Current
0.1
1.5
45
55(3)
55
65(3)
90
100(3)
RON
FPF1203L
On Resistance
185
(3)
VIN=3.3 V, VON=OFF,
IFORCE=20 mA, TA=25C,
FPF1204 / FPF12045
VIH
VIN=1.2 V to 5.5 V
VIL
RON_PD
ION
220
A
A
A
(3)
105
65
75
1.15
VIN=1.2 V to 5.5 V
0.65
VIN=1.2 V to 1.8 V
0.60
VIN=1.2 V to 5.5 V
On Input Leakage
VON=VIN or GND
8.3
M
1
Dynamic Characteristics
tDON
Turn-On Delay(4)
70
tR
100
tON
Turn-On Time(6)
tDON
(4)
Turn-On Delay
170
2
tR
tON
Turn-On Time(6)
tDOFF
tF
(4,5)
Turn-Off Delay
(4,5)
tOFF
Turn-Off Time(5,7)
tDOFF
Turn-Off Delay(4,5)
tF
(4,5)
(5,7)
tOFF
Turn-Off Time
tDOFF
Turn-Off Delay(4,5)
tF
(4,5)
(5,7)
tOFF
Turn-Off Time
tDOFF
Turn-Off Delay(4,5)
tF
tOFF
(4,5)
(5,7)
Turn-Off Time
0.5
2.0
2.5
6
115
121
4.0
2.9
7.3
6
115
121
Continued on the following page
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5
Electrical Characteristics
Unless otherwise noted, VIN=1.2 V to 5.5 V and TA=-40 to +85C. Typical values are at VIN=3.3 V and TA=25C.
Symbol
tDOFF
tF
Parameter
Turn-Off Delay
(4,5)
(5,7)
tOFF
Turn-Off Time
tDOFF
Turn-Off Delay(4,5)
tF
tOFF
Condition
Min.
(4,5)
(4,5)
(5,7)
Turn-Off Time
Typ.
Max.
Unit
4.0
2.5
6.5
6
11
17
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF are defined in Figure 23.
5. Output discharge enabled during off-state.
6. tON=tR + tDON.
7. tOFF=tF + tDOFF.
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6
Electrical Characteristics
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7
100
100s
10
1ms
1
10ms
RDS(ON) Limit
0.1
100ms
1s
10s
DC
Single Pulse
RJA = 110oC/W
TA = 25oC
0.01
0.1
1
VDS, DRAIN-SOURCE VOLTAGE (V)
10
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8
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9
Output Capacitor
A 0.1 F capacitor, COUT, should be placed between the
VOUT and GND pins. This capacitor prevents parasitic
board inductance from forcing VOUT below GND when
the switch is on. CIN greater than COUT is highly
recommended. COUT greater than CIN can cause VOUT to
exceed VIN when the system supply is removed. This
could result in current flow through the body diode from
VOUT to VIN.
90%
VOUT
90%
10%
10%
tR
tF
3.3V
50%
50%
VON
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor
must be placed between the VIN and GND pins. A 1 F
ceramic capacitor, CIN, placed close to the pins is
usually sufficient. Higher-value CIN can be used to
reduce the voltage drop in higher-current applications.
10%
VOUT
tDON
tDOFF
Board Layout
For best performance, traces should be as short as
possible. To be most effective, input and output
capacitors should be placed close to the device to
minimize the effect of parasitic trace inductance on
normal and short-circuit operation. Using wide traces or
large copper planes for all pins (VIN, VOUT, ON, and
GND) minimizes the parasitic electrical effects and the
case-ambient thermal impedance. However, the VOUT
pin should not connect directly to the battery source due
to the discharge mechanism of the load switch.
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10
0.03 C
2X
F
E
A
0.40
0.20
Cu Pad
A1
0.40
BALL A1
INDEX AREA
0.30
Solder Mask
0.03 C
2X
TOP VIEW
0.2920.018
0.539
0.461
0.05 C
0.2080.021
SEATING PLANE
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
0.005
C A B
0.2600.020
4X
0.40
B
A
0.40
(Y)0.018
F
1 2
(X)0.018
BOTTOM VIEW
Product Dimensions
D
760 m 30 m
760 m 30 m
0.180 mm 0.018 m
0.180 mm 0.018 m
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
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11
Physical Dimensions
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12