PROGRAM- BSc IT

SEMESTER- SECOND
SUBJECT CODE & NAME- BT0068, Computer Organization and Architecture
CREDIT- 4 BK ID- B0952 MAX. MARKS- 60
Q1.
1. Subtract (76425-28321) using 10s complement. Show the steps.

Answer.
Follow these steps:
Step 1:
Take the "10s complement" of the number we are subtracting.
10s complement of 28321 is 71679
Step 2:
Add it to the number we are subtracting from
Adding 71679 to 76425 we get,
148104
Step 3:
Discard the extra "1" on the left
Hence we get the final result is: 48104
Therefore the difference is 48104 after discarding the end carry.

2. Subtract (28531-345620) using 10s complement. Show the steps.

Answer.
Follow these steps:
Step 1:
Take the "10s complement" of the number we are subtracting.
10s complement of 345920 is 654080

Step 2:
Add it to the number we are subtracting from
Adding 6 5 4 0 8 0to 0 2 8 5 3 1 we get,
682611
Step 3:
Difference is negative and is equal to the 10scomplement of the answer.
Therefore,
Difference is - 317389

Q2. What do you mean by bus in computer system? Explain the bus structure. 4+6
Answer:A collection of wires through which data is transmitted from one part of a computer to
another. You can think of a bus as a highway on which data travels within a computer. When used in
reference to personal computers, the term bus usually refers to internal bus. This is a bus that
connects all the internal computer components to the CPU and main memory. There's also an
expansion bus that enables expansion boardsto access the CPU and memory.

All buses consist of two parts -- an address busand a data bus. The data bus transfers actual data
whereas the address bus transfers information about where the data should go.
The size of a bus, known as its width, is important because it determines how much data can be
transmitted at one time. For example, a 16-bit bus can transmit 16 bits of data, whereas a 32-bitbus
can transmit 32 bits of data.
Every bus has a clock speed measured in MHz. A fast bus allows data to be transferred faster, which
makes applications run faster. On PCs, the old ISA bus is being replaced by faster buses such as
PCI.
Nearly all PCs made today include a local bus for data that requires especially fast transfer speeds,
such as video data. The local bus is a high-speed pathway that connects directly to the processor.
Several different types of buses are used on Apple Macintosh computers. Older Macs use a bus
called NuBus, but newer ones use PCI.
Bus Structure
A bus consists of 1 or more wires. There's usually a bus that connects the
CPU to memory and to disk and I/O devices. Real computers usually have several busses, even though the
simple computer we have modeled only has one bus where we consider the data bus, the address bus, and
the control bus as part of one larger bus.
The size of the bus is the number of wires in the bus. We can refer toindividual wires or a group of
adjacent wires with subscripts. A bus can be drawn as a line with a dash across it to indicate there's more
than one wire.
The dash in it is then labeled with the number of wires and the designation of those wires.

For example, consider a bus as shown in figure 3.9. It consists of a slant dash on the horizontal line that
represents it is a bus that carries more wires.
Also the slant dash is labeled 32 which indicates that the number of wires in that bus is 32 and the dash is
also labeled A31-0 which indicates individual
32 wires from A0 to A31. We can then refer to, say A10-0 or A15-9 to refer to some subset of the wires.
A bus allows any number of devices to hook up to the bus. Devices connected to the bus must share the
bus. Only one device can write to it at a time. One alternative to using a bus is to connect each pair of

devices directly. Unfortunately, for N devices, this requires about N2 connections,which may be too many.
Most devices have a fixed number of connections which doesn't permit dedicated connections to other
devices. A bus doesn't have this problem.
Data, Address, and Control Busses
There are usually 3 kinds of buses. There's a 32-bit data bus, which is used to write or read 32 bits of data
to or from memory. There's a 32-bit address bus for the CPU to specify which address to read or write
from or to memory.
Finally, there's a control bus which may consist of a single wire or multiple wires to allow the CPU and
memory to communicate
For example a control signal is required to indicate when and whether a read or write is to be performed.
To support two 32-bit busses, both the
CPU and memory require 64 pins or connections 32 for data and 32 for address. Earlier there was shortage
of pins and hence it was necessary to multiplex the address and data bus. Multiplexing uses the same bus
as both address and data bus.

Q3. Explain the instruction format with diagram and examples6+4

Answer.
Each instruction is represented by a sequence of bits. The instruction isdivided into fields, corresponding
to the constituent elements of theinstruction. This layout of the instruction is called Instruction Format.
Instruction Format is defined as the layout of bits in an instruction in termsof its constituent parts. An
Instruction Format must include opcode implicitly or explicitly and one or more operand(s). For, most
instruction sets haveusually more than one instruction format.
Instruction Length
Most important design issue is the length of an instruction. It is affected byand affects Memory size,
Memory organization, Bus structure, CPUcomplexity, CPU speed. There is a trade off between powerful
instruction repertoire and saving space. Apart from this tradeoff there are other considerations. Either the
instructionlength should be equal to the memory transfer length or one should be amultiple of the other. A
related consideration is the memory transfer rate.
Allocation of Bits
The factors that determine the use of addressing bits are:

Number of addressing modes: Sometimes addressing mode is implicit in the instruction or may
be certain op codes call for indexing. Inother cases the addressing mode must be explicit and one

or more bitsare needed.

Number of operands: Typically todays machines provide two operands.Each operand may

require its own mode indicator or the use of indicatoris limited to one of the address fields.
Register versus memory: A machine must have registers so that thedata can be brought into the
CPU for processing. One operand addressis implicit. The more the registers are used to specify the

operands lessthe number of bits needed.

Number of register sets: Almost all machines have a set of generalpurpose registers, with
typically 8 or 16 registers in it. These registerscan be used to store data or addresses for

displacement addressing etc.

Address range: For addresses that refer to the memory locations, therange of addresses is related

to the number of address bits. Because ofthis limitation direct addressing is rarely used.
Address granularity: It is concerned with addresses that refer to thememory other than registers.
In a system with 16 or 32 bit words, anaddress can refer to a word or a byte at the designers
choice. Byte addressing is convenient for character manipulation but requires fixedsize memory,
and hence more address bits.

Variable-Length Instruction
The designer might provide a variety of instruction formats of differentlengths. Addressing can be more
flexible, with various combinations ofregisters and memory references plus addressing modes.
The price that needs to be paid is an increase in the complexity of the CPU.
1. Due to varying number of operands,
2. Due to varying lengths of opcode in some CPUs.

Q4. Explain the non-negative integers and negative integers representation. 5+5
Answer.
Non-negative Integers
The easiest numbers to represent are the non-negative integers. To seehow this can be done, recall how we
represent a number in the decimalsystem. A number such as 2034 is interpreted as:2*103 + 0*102 + 3*101
+ 4*100But there is nothing special with the base 10, so we can just as well usebase 2. In base 2, each
digit value is either 0 or 1, which we can represent,for instance, by false and true, respectively.

In fact, we have already hinted at this possibility, since we usually write 0and 1 instead of false and
true.All the normal algorithms for decimal arithmetic have versions for binaryarithmetic, except that they
are usually simpler.
Negative Integers
Things are easy as long as we stick to non-negative integers. They becomemore complicated when we
want to represent negative integers as well.In binary arithmetic, we simply reserve one bit to determine the
sign. In thecircuitry for addition, we would have one circuit for adding two numbers, andanother for
subtracting two numbers. The combination of signs of the twoinputs would determine which circuit to use
on the absolute values, as wellas the sign of the output.While this method works, it turns out that there is
one that is much easier todeal with by electronic circuits. This method is called the two's complement
method. It turns out that with this method, we do not need aspecial circuit for subtracting two numbers.In
order to explain this method, we first show how it would work in decimal arithmetic with infinite
precision. Then we show how it works with binaryarithmetic, and finally how it works with finite
precision.

Q5. Explain the mapping functions between the main memory and CPU. 10
Answer.
Mapping functions
The correspondence between the main memory and CPU are specified by amapping function. There are
three standard mapping functions namely
1. Direct mapping
2. Associative mapping
3. Block set associative mapping
In order to discuss these methods consider a cache consisting of 128 blocksof 16 words each. Assume that
main memory is addressable by a 16 bitaddress. For mapping purpose main memory is viewed as
composed of 4Kblocks.
1. Direct mapping technique
This is the simplest mapping technique. In this case, block K of the mainmemory maps onto block K
modulo 128 of the cache. Since more than one

main memory block is mapped onto a given cache block position, contentionmay arise for that position
even when the cache is not full. This is overcomeby allowing the new block to overwrite the currently
resident block.

Figure: Direct mapping cache

A main memory address can be divided into three fields, TAG, BLOCK andWORD as shown in figure.
The TAG bit is required to identify a mainmemory block when it is resident in the cache. When a new
block enters the cache the 7-bit cache block field determines the cache position in which thisblock must be
stored. The tag field of that block is compared with tag field ofthe address. If they match, then the desired
word is present in that block ofcache. If there is no match, then the block containing the required
wordmust be first read from the main memory and then loaded into the cache.

Q6. Write a short note on DMA controller. Draw the diagram of it. 7+3
Answer:
DMA Controller

DMA has been a built-in feature of PC architecture since the introduction of the original IBM PC. PCbased DMA was used for floppy disk I/O in the original PC and for hard disk I/O in later versions. PCbased DMA technology, along with high-speed bus technology, is driven by data storage, communications
and graphics needs all of which require the highest rates of data transfer between system memory and
I/O devices. Data acquisition applications have the same needs and therefore can take advantage of the
technology developed for larger markets. This section introduces DMA controller terminology and
explains the basic operation of a PC - based DMA controller along with common modes of operation. Key
terminology is italicized. A DMA controller is a device, usually peripheral to a computer's CPU, that is,
programmed to perform a sequence of data transfers on behalf of the CPU. A DMA controller can directly
access memory and is used to transfer data from one memory location to another, or from an I/O device to
memory and vice versa. A DMA controller manages several DMA channels, each of which can be
programmed to perform a sequence of these DMA transfers. Devices, usually I/O peripherals, that acquire
data that must be read (or devices that must output data and be written to) signal the DMA controller to
perform a DMA transfer by asserting a hardware DMA request signal. A DMA request signal for each
channel is routed to the DMA controller. This signal is monitored and responded to in much the same way
as a processor handles interrupts. When the DMA controller sees a DMA request, the DMA controller
responds by performing one or many data transfers from that I/O device into system memory or vice
versa. Channels must be enabled by the processor for the DMA controller to respond to DMA requests.
The number of transfers performed, transfer modes used and memory locations accessed depend on how
the DMA channel is programmed. A DMA controller typically shares the system memory and I/O bus with
the CPU and has both bus master and slave capability. Figure 12.6 shows the DMA controller architecture
and how the DMA controller interacts with the CPU. In bus master mode, the DMA controller acquires the
system bus address, data and control lines) from the CPU to perform the DMA transfers. Because the CPU
releases the system bus for the duration of the transfer, the process is sometimes referred to as cycle
stealing. However, this term is no longer appropriate in the context of the new high-performance
architectures that are appearing in personal computers. These architectures use cache memory for the

CPU, which enables the DMA controller to operate in parallel with the CPU to some extent.

In bus slave mode, the DMA controller is accessed by the CPU, which programs the DMA
controller's internal registers to set up DMA transfers. The internal registers consist of source
and destination address registersand transfer count registers for each DMA channel, as well as
control andstatus registers for initiating, monitoring and sustaining the operation of the DMA
controller.