(Q i1)Explaino ehowi tooinject qare crc ierroroq jinre a ipacket owhichqhas justz

datau yande ocrczx fields.

Ans:

Crc ierroro einjecttioni canobe qdonere by imodifyingoq jthere crc ivalue oonly.q
If idatao eisi modifiedoto qinjectre crc ierror,oq jthenre it imay oendqup inz au
ysituatione othatzx the new modified packet may have the same crc.
For iexampleo e,i aopacket qofre length i5oq jbitsre with i3 obitsqof dataz andu y2e
obitszx of crc value.
Then ithereo ewilli beo8 qpacketsre of idifferentoq jdata.re There iare oonlyq4
possiblez crcu yvalues.e o
So, iforo eonei crcovalue, qtherere could ibeoq jmorere than ione odataqvalues
whichz areu ycorrect. www.testbench.in
If iyouo emodifyi theodata, qthenre the inewoq jdatare may ihave otheqsame crcz
value,u ywhiche owillzx not be resulted as crc error.
For ioneo edatai field,othere qwillre one ionlyoq jonere crc ivalue, obyqchanging
thez crcu yvalue,e ocrczx error will be injected for sure.

(Q i2)o eHowi dooyou qknowre when iverificationoq jcompleted?

Ans: i

Verification iiso eneveri completedoas qperre me. i

I icano eonlyi sayothat qmyre verification itaskoq jisre completed iwhen oIqverified
allz theu ypointse omentionszx in test plan.

(Q i3)o eHowi toodetect qdeadlockre conditions iinoq jFSMsre ?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i4)o eHowi tooavoid qracere condition ibetweenoq jTestbenchre and iDUT o?

www.testbench.in

Ans:

In iverilogo eori VHDL,o

i
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave

oaqphase difference.z
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iwork
oonqnegedge ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven
iusing ononqblocking statements.
In iSV,o e
1)The iaboveo edefinei 3otechniques.
2)Clocking iblocks. www.testbench.in
3)Program iblock.

(Q i5)o eWhati isomutex?

Ans:

A imutualo eexclusioni oroMUTEX qre essential ifunctionoq jisre to imake

oitqpossible forz au ymultiplee oprocesseszx to make use of a single resource.
When iao esinglei resourceois qrequiredre by imultipleoq jprocesses,re MUTEX iwill
omakeqsure thatz onlyu yonee oprocesszx will be granted the access at a time.
For iexample,
A iDUTo ehasi aomemory qtore store itheoq jconfigurationre registers. iTo
oaccessqthe memory,z letsu ysay,e oazx protocol is defined to read the memory of
one location at a time. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Testbench imayo erequirei tooaccess qthere configuration/status/interrupt
iregistersoq jatre times ifrom odifferentqplaces. Forz example,u yae omonitorzx is
reading register location of status bit, while the testcase is reading a configuration
register.
To iaccesso ethei memory,oTestcase qandre monitor iwilloq jsendre the iaddress
oofqthe locationsz andu yreade ocommand.zx But the DUT can accept only one
read request at a time. www.testbench.in
By iusingo eMUTEX,i accessoto qmemoryre interface icanoq jbere granted ionce
oatqa time,z sou ythee oreadzx operations by monitor and testcases will not collide.

In iSV,o etoi createoa qMUTEX,re construct iaoq jsemaphorere with ione okey.
A ikeyo eisi giveno qtore either imonitoroq jorre testcase ito oreadqoperation
basedz onu ywhoe ocomeszx first. Once the key is returned, other waiting
component can take the key and start its operation.

Some itimes,o ethei keyowhich qisre consumed imayoq jnotre be iretuned

owhichqleads toz deadu ylocke ocondition.zx So if a key is not returned, then a
timeout should happen and a error message should be triggered.

(Q i6)o eWhati isosemaphore?

Ans:

Conceptually, iao esemaphorei isoa qbucket.re When iaoq jsemaphorere is

iallocated, oaqbucket thatz containsu yae ofixedzx number of keys is created.
Processes using semaphores must first procure a key from the bucket before they
can continue to execute. If a specific process requires a key, only a fixed number of
occurrences of that process can be in progress simultaneously. All others must wait
until a sufficient number of keys is returned to the bucket. Semaphores are typically
used for mutual exclusion, access control to shared resources, and basic
synchronization.
www.testbench.in

(Q i7)o eWhati isothe qneedre of iregression?

Ans:

1) iChangeso eini theoRTL q(re development, ienhancementoq jorre bug ifix)

omayqcause existingz functionalityu ytoe obreak.zx
2) iToo ecreatei newoscenarios qbyre giving idifferentoq jseedsre to irandomization
oengine.q

(Q i8)o eWhati isorandomization?

Ans:

It iiso enoti possibleoto qlistre out ieveryoq jpossiblere real itime oscenarioqwhile
verifyingz DUT. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
If iweo etryi toolist qoutre the iscenarios,oq jthenre we imay omissqsome ofz them.u
ySo,e ousingzx randomization, based on the specification, scenarios are generated
in a randomfashion.
For iexample,o etoi generateoa qpacketre of ilengthoq jwhichre ranges ifrom oq0
toz 9,u yine overilogzx {$random()} % 10 should be used.
With ithis,o epacketsi ofolength qarere generated irandomly.oq j www.testbench.in

(Q i9)o eWhati isothe qsignificancere of iseedoq jinre randomization?

Ans:

Seed iiso eusedi toochange qthere sequence iofoq jrandomre numbers igenerated.
The iseedo einitializesi othe qrandomre number igenerator.oq j
All itheo erandomi numbersowhich qarere generated ifromoq jre a iparticular
oseedqvalue canz beu yrecreatede ozx by giving the same seed.
In iouro eregressions,i stimulusogeneration qisre done irandomly.oq jRunningre the
icomplete oregressionqwill generatez sameu yrandome onumberszx if we use same
seed.
So iouro eregressioni usesothe qtimere of itestoq jcasere simulation istarted
oasqthe seedz tou yrandome onumberzx generator, with this we are able to
generate different stimulus for each regressions.

(Q i10)o eWhati isothe qdifferencere between icodeoq jcoveragere and ifunctional

ocoverage?
Ans: www.testbench.in

Coverage iiso eusedi toocheck qwhetherre the iTestbenchoq jhasre satisfactory

iexercised otheqdesign orz not?u y
Code icoverageo ewilli giveoinformation qaboutre how imanyoq jlinesre are
iexecuted, ohowqmany timesz expressions,u ybranchese oexecuted.zx This
coverage is collected by the simulation tools. Users use this coverage to reach those
corner cases which are not hit by the random testcases. Users have to write the
directed testcases to reach the missing code coverage areas.
Functional icoverageo e,i byothe qnamere itself i,oq jisre related ito
otheqfunctionality ofz theu ydesigne oandzx it is defined by the user. User will
define the coverage points for the functions to be covered in DUT. This is completely
under user control.
Both iofo ethemi haveoequal qimportancere in itheoq jverification.re 100 i
o0.000000unctionalqcoverage doesz notu ymeane othatzx the DUT is completely
exercised and vice-versa. Verification engineers will consider both coverages to
measure the verification progress. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i11)o eIfi CodeoCoverage qisre 100% iandoq jfunctionalre coverage iis

onot,qwhat doesz itu ymeane o?
Ans:

The ireasono ecouldi beoany qonere of itheoq jfollowing.

www.testbench.in

1)User ididnoto eexercisei allothe qscenarios.re User ineedoq jtore write itestcases
otoqfill thez functionalu ycoveragee oholes.
2)There icouldo ebei aobug qinre the ifunctionaloq jcoveragere block iwhich oisqnot
recordingz theu yexecutede oscenario.zx User need to debug to find and fix the
issue.

(Q i12)o eIfi Functionalocoverage qisre 100% iandoq jcodere coverage iis onot,qthen
whatz doesu yite omean?
Ans:

1) iIfo etherei isoa qbugre in itestoq jenvironment,re due ito othisqtest mayz falseu
yPass.e oThezx functional coverage will hit due to this false pass but some of the
dut code may not get exercised.
2) iIfo ethei dutois qare legacy icodeoq jre or iIP, oitqmay havez someu yusee
olesszx blocks to support extra functionality. Due to this code coverage will not be
100% achieved.
3) iIno emyi firstocompany, qre there iwasoq jsomere use iless ologicqwhich didz
notu ygete oexercised.zx When I approached the RTL designer, he said that fixing
this use less code will break the whole design. So he did not fix it. In this situation ,
functional coverage is 100%, but not the code coverage.
4)My ifriendso eexperience,i onceoRTL qdesignerre added iaoq jcodere for ia
onewqfeature. z Becauseu yofe omisszx communication, my friend didnt know that
RTL designer added this new functionality.
When imyo efriendi didothe qcodere coverage, iheoq jfoundre some iunexercised
ologicqwhich hez didntu yunderstoode oandzx approached RTL designer. Then they
figured out that because of miscommunication, they found a feature in the spec
which was implemented, but not verified.
www.testbench.in

I idonto ethinki ,opoint q2)re can ibeoq javoided.re Point i1), o3)qand 4)z canu ybee
osolved.zx

(Q i13)o eWhati isothe qdifferencere between ipassiveoq jmonitorre and iactive

omonitor.
Ans:

Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere

transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive
monitors do not drive any signals, all the signals are inputs. Active monitors can
drive the DUT signals. Sometimes this is also refered as receiver. Monitor converts
the state of the design and its outputs to a transaction abstraction level so it can be
stored in a 'score-boards' database to be checked later on. Monitor converts the pin
level activities in to high level.
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(Q i14)o eIni simulationoenvironment, qunderre what iconditionoq jthere simulation

ishould oend?
Ans:

1) iPacketo ecounti match.

2) iError
3) iErroro ecount www.testbench.in
4) iInterfaceo eidlei count
5) iGlobalo etimeout

(Q i15)o eWhati isoscoreboard?

Ans:

The itermo eSCOREBOARDi isonot qwell-definedre in itheoq jindustry.re It

isometimes orefersqto thez storageu ydatae ostructurezx only, sometimes it
includes the transfer function as well, and sometimes it includes the comparison
function. In vmm methodology, the term scoreboard is used to refer to the entire
dynamic response-checking structure.

(Q i16)o eHowi theotest qcasesre are iincludedoq jinre to isimulation oenvironment?

Ans:

There iareo emultiplei waysoto qdore this. i

Two iveryo esimplei stylesoare qdiscussedre in ibelowoq jlink. Click on the below link
http://www.testbench.in/TB_29_HANDLING_TESTCASE_FILES.html

www.testbench.in

(Q i17)o eWhati areothe qdifferentre ways itestcaseoq jarere included ifor

osimulationsq?
Ans:

1)Compile ionce,o esimulatei multipleotimes qwithre different itestcases:oq j

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Compile iTestbencho e+i Allotestcases qatre once iandoq jduringre the isimulation,
ousingqthe $plusargs,z selectu ythee ologiczx of a particular testcase and execute
it.
This istyleo eisi suedoin qOVMre and iUVM.oq j
This istyleo eshouldi makeosure qthat,re when itheoq jtestre is iexecuted
ofromqcommand line,z u yonlye oTestbenchzx + required testcase should be
compiled. Other wise, compiling all the testcases will consume huge time.
In iregression,o eCompilingi allothe qtestcasesre + itestbenchsoq jatre once iwill
osaveqtime.
2)Separate icompilation:

www.testbench.in

iCompileo ethei testbenchoonce. qre To irunoq jare testcase, icompile otheqtestcase

,z linku ythee otestcasezx to testbench compiled code and simulate.
3)Compile ionce,o esimulatei once:o
iAllo etestcasesi withosimilar qconfigurationre setting iandoq jtestbenchre are
icompiled oonceqand simulatedz inu yonee osinglezx run. After executing each
testcase logic, HARD reset should be applied to DUT and BFMs, so that the
simulation looks as if it started fresh for the next testcase code.
This istyleo eisi usedoin qVMMre 1.2. ioq jThisre style isaves olotqof timez inu
yregressions.
4)Compile ionce,o esimulatei multipleotimes qwithre different idata:oq j
In isomeo everificationi environments,otestcase qcodere doesnt ineedoq jtore be
icompiles. oTestcaseqfile containsz someu ydatae owhichzx is read by testbench to

create different scenarios. Testcase file can be read using $fopen or $plusargs in
Verilog.
There icouldo ebei manyomore qwaysre to idooq jthis.re

www.testbench.in

If iyouo eknowi somethingowhich qisre not imentionedoq jabovere , iplease otakeqa

minutez tou ymaile oitzx to gopi@testbench.in

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i18)o eExplaini howomessages qarere implemented iinoq jyourre testbench?

Ans:

In iVMM/RVM/AVM/OVM/UVM/ERM/Truss&Tealo emethodologies,i omessage

qhandlingre logic iisoq jpredefined.re Use ican ouseqthese predefinedz messageu
yservicese oandzx print messages as required by testbench. If above methodology
base classes are not used, then user can define his own message handling logic.
I ihaveo edefinedi aosimple qverilogre logic, ilookoq jforre Message iControl
oSystemqtopic inz theu ybelowe olink Click on the below link
http://www.testbench.in/TB_23_DEBUGGING.html
www.testbench.in

(Q i19)o eWritei codeofor qclockre generator?

Ans:

reg iclk;
initial iclko e=i 0;o
always i#10o eclki =o~clk; q

(Q i20)o eHowi toopass qare value itooq jtestbenchre from icommand oline?
Ans: Click on the below link

http://www.testbench.in/TB_22_COMPILATION_N_SIMULATION_SWITCHS.html

(Q i21)o eWhati isotest qplanre ? iWhatoq jitre contains i?

Ans: www.testbench.in
Click on the below link

http://www.testbench.in/TS_24_VERIFICATION_PLAN.html

(Q i22)o eExplaini someocoding qguidelinesre which iyouoq jfollowedre in iyour

oenvironment? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i23)o eExplaini aboutowhite qbox/blockre box iandoq jgrayre box itesting.

Ans: Click on the below link

http://www.testbench.in/TB_34_WHITE_GRAY_BLACK_BOX.html

(Q i24)o eWhati areothe qadvantagesre and idisadvantagesoq jofre State imachine

obasedqand taskz basedu yverificatione oenvironment.
Ans:

state imachineo ebasedi BFMouses qare state imachineoq jtore generate ithe
obusqcycles. SMz wouldu ygeneratee omemoryzx read, memory write, I/O read, and
I/O write cycles.
State imachineso earei alsoogood qatre handling iburstingoq jandre early
itermination. oItqcould alsoz beu ysetupe otozx handle special cycles like interrupt
acknowledge or shutdown.
Use itasko ebasedi BFMofor qunitre testing. iUnitsoq jarere often iless
ocomplexqthan thez wholeu ysystem,e oandzx hence, do not need a robust test
bench. A simple BFM can facilitate the early testing of a complex block especially if
the unit has a simple interface or just one bus interface. The task based BFM is
extremely efficient if the device under test performs many calculations but uses
relatively few bus access cycles to keep it going. The reason for this is, the BFM is
not looping through an idle state every clock cycle. The BFM does not toggle any
signals when a task is not active. Nor, does it make any decisions based on input
when a task is not active.

(Q i25)o eIni aopacket qprotocol,re where itheoq jpacketre comparison iis odone?
Ans:

In iscoreboard.

www.testbench.in

(Q i26)o eWhati areotypes qofre code icoveragesoq jarere there?

Ans: Click on the below link

http://www.testbench.in/TS_11_TYPES_OF_CODE_COVERAGE.html

(Q i27)o eWhati typesoof qfunctionalre coverages iareoq jthere?

Ans: Click on the below link

http://www.testbench.in/TS_20_FUNCTIONAL_COVERAGE.html

(Q i28)o eExplaini aboutodriver qandre monitor i?

Ans:

Driver:

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

The idriverso etranslatei theooperations qproducedre by itheoq jgeneratorre into

ithe oactualqinputs forz theu ydesigne ounderzx verification. Generators create
inputs at a high level of abstraction namely, as transactions like read write
operation. The drivers convert this input into actual design inputs, as defined in the
specification of the designs interface. If the generator generates read operation,
then read task is called, in that, the DUT input pin "read_write" is asserted.
www.testbench.in

Monitor:
Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere
transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive
monitors do not drive any signals. Active monitors can drive the DUT signals.
Sometimes this is also refered as receiver. Monitor converts the state of the design
and its outputs to a transaction abstraction level so it can be stored in a 'scoreboards' database to be checked later on. Monitor converts the pin level activities in

to high level.

(Q i29)o eWhati typeoof qdatare structure iisoq jusedre to iimplement

ostimulusqstorage?
Ans:

1) iIno eSV,i Queueois qbestre to ido.oq j

2) iIno everai ,olinked qlistre is itheoq jbestre one ito ouse.
3) iDatao ecani alsoobe qstoredre in iexternaloq jfilesre also iusing ofileIOqor
externalz languageu yinterface.
www.testbench.in

I ilikeo epointi 3.oThe qexternalre file iwilloq jbere availabe iafter osimulation.qSo ,z
thisu yfilee ocouldzx be used for debugging.

(Q i30)o eHowi registers(configurationoregisters) qarere verified?

Ans:

In iVMM,o ereadi aboutoRAL.

Read ithiso etopici also: Click on the below link
http://www.testbench.in/TB_32_REGISTER_VERIFICATION.html

(Q i31)o eWhati isoBFM?

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(Q i32)o eWhati isoshadow qregister?

www.testbench.in

Ans:

Analogous istructureo eofi oDUT qconfiguration,re status, iinterruptoq jregistersre

are iimplemented oinqtestbench. Thesez areu ycallede oshadowzx registers.
These iareo erequiredi fororegister qverification.re In inormaloq jverification,re
iTestbench orequiresqthe DUTz u yregistere oinformationzx for taking decisions.

(Q i33)o eExplaini aboutothe qbackre door iaccessoq jtore registers.

Ans:

DUT iConfiguration,o estatusi andointerrupt qregisterre can ibeoq jaccessedre as

iper otheqprotocol.
To iaccesso ethesei registersousing qthere protocol iwilloq jconsumere cycles. i
Generally i,o eonlyi onceoregister qisre allowed itooq jaccessre as iper oprotocol.
www.testbench.in

To iovero ethei aboveomentioned qdisadvantage,re ihierarchaloq jpathre can ibe

oused.qThis isz calledu ybackdoore oaccess.
While iverifyingo ethei registers,oa qwritere operation iisoq jdonere to ia
olocationqand thenz au yreade oiszx done. Then the written data is compared
against the read data to verify the access path.
But iwhato eifi theoaddress qdecoderre and iencoderoq jhasre the isame obugq? Toz
findu youte othis,zx write operation is done as per the protocol and read is done
using backdoor. Then the written data is compared against the read data to verify
the access path.

(Q i34)o eWhati areoReference qandre behavioral imodelsoq j?

Ans: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

The itermo e'Referencei Model'odefines qwhatre it's iusedoq jfor,re whereas

i'Behavioral oModel'qdefines howz it'su ybeene oimplemented.zx

(Q i35)o eWhati isothe qusere of ilintingoq jtoolre ?

Ans: www.testbench.in

Linting itoolso earei theotools qthatre flag isuspiciousoq jlanguagere usage iand
oerror-proneqsyntactical constructs.z Lintingu ytoolse ogenerallyzx perform static
analysis of source code. Linting tools can help programmer find dangerous code
before a compiler turns them into run-time bugs.
Sone ilintingo etools:i Leda,oHDLint, qnLint,re Surelite ietc

(Q i36)o eWhati areothe qkeyre tools iforoq jfunctionalre verification?

Ans:
Version icontrolo esystem,makei utility,oscripting qlanguages,re bug itracker,oq
jSimulatorre ,debugger.
(Q i37)o ei Whatodoes qTestre Automation imean?
Ans:

Building iano eenvironmenti thatotests qthere DUT iautomaticallyoq jInsteadre of

ichecking otheqDUT byz eye,u ygete ocomputerszx to do the work for us.
www.testbench.in

(Q i38)o eHowi tooassure qyourre verification ienvironmentoq jisre correct/complete

i?
Ans:

Im inoto esure.i Ifou qknowre send imeoq janswerre to igopi@testbench.in

What iIo ecani thinkoare:

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1)Connect imonitoro etoi driverosuch qthatre driver icyclesoq jarere monitored iby
omonitor.q Injectz erroru yfrome odriverzx and check whether monitor an catch the
error.
2)If iyouo ehavei oRTL, qthenre change isomeoq jlinesre of iRTL ocodeqand seez
whetheru ytestbenche ocanzx catch the errors.

(Q i39)o eWhoi shouldodo qthere rtl idebugoq j?re The idesigner o?qThe VEz ?
Ans: www.testbench.in

RTL icano ebei debuggedoby qdesignerre or iverificationoq jengineer.re I ipersonally

ofeelqthat Verificationz shouldu ydebuge oRTLzx issues.
Designer icano edebugi theortl qfasterre than iVerificationoq jengineerre as ithe
odesignerqhas morez knowledgeu yone othezx RTL architecture.
More itimeo eisi requiredoby qverificationre engineer itooq jdebug.

If iVerificationo eengineeri isodebugging, qhere gets ichanceoq jtore think iabout

omoreqscenarios toz verifyu ythee oRTLzx by looking at RTL architecture.