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CMOS TECHNOLOGY
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Abstract:
The concept of CMOS was introduced by Chi-Tang Sah and Frank Wanlass inn
1963 and did not become common until the 1980s as NMOS microprocessors were dissipating
as much as 50W and alternative design techniques were needed. It is widely use din chips like
static RAM, microprocessors, microcontrollers and in other digitla logic devices and has wide
applications like data converters, sensorsa and transceivers. CMOS has also replaced bipolar
technology and has made possible levels of integration (or circuit-packing densities) and a range of
applications, neither of which would have been possible with bipolar technology.
Digital IC Techniques and Logic Circuit Families
The following figure shows the major IC technologies and logic-circuit families that are
currently in use. Members of each family are made with the same technology, have a
similar circuit structure, and exhibit the same basic features. Each logic circuit family offers
a unique set of advantages and disadvantages. In the conventional style of designing systems, one
selects an appropriate logic family (e.g., TTL, CMOS, or ECL) and attempts to implement as
much of the system as possible using circuit modules (packages) that belong to this family. In
this way, interconnection of the various packages is relatively straightforward.
The selection of a logic family is based on such considerations as logic
flexibility, speed

of operation,

availability

of complex functions, noise immunity, operating-

temperature range, power dissipation, and cost.

CMOS Technology:
The concept of CMOS was introduced by Chi-Tang Sah and Frank Wanlass inn 1963 and
did not become common until the 1980s as NMOS microprocessors were dissipating as much as
50W and alternative design techniques were needed. CMOS

technology

is,

by

large

margin, the most dominant of all the IC technologies available for digital-circuit design. CMOS
has replaced NMOS, which was employed in the early days of VLSI (in the 1970s). The most
important of which is the much lower power dissipation of CMOS circuits. CMOS has also
replaced bipolar technology and has made possible levels of integration (or circuit-packing
densities) and a range of applications, neither of which would have been possible with bipolar
technology.
N-Channel and P-Channel transistors can be fabricated on the same substrate as shown
below:

Figure 1: CMOS

Some of the reasons for replacing bipolar technology in digital applications are as follows:
1) CMOS logic circuits dissipate much less power than bipolar logic circuits and
thus one can pack more CMOS circuits on a chip than is possible with bipolar circuits.
2) The high input impedance of the MOS transistor allows the designer to use charge
storage as a means for the temporary storage of information in both logic and memory circuits.
This technique cannot be used in bipolar circuits.
3) The feature size (i.e., minimum channel length) of the MOS transistor has decreased
dramatically over the years, with some recently reported designs utilizing channel

lengths as short as 0.06 m. This permits very tight circuit packing and, correspondingly, very
high levels of integration.
Basic CMOS Inverter Circuit:
A CMOS inverter circuit is formed with the combination of PMOS and NMOS. The inverter
circuit, shown in Fig, consists of a pair of complementary MOSFETs switched by the input
voltage VI. The source of each device is connected to its body, thus eliminating the body
effect. Usually, the threshold voltages Vtn and Vtp are equal in magnitude; that is, V tn=|Vtp| =
Vt is in the range of 0.2 V to 1V. The inverter circuit can be represented by
operated in a complementary fashion, as shown in Fig. 4 (b).

sVdd
g
PMOS
dout
in
d
g sN
M
O
S

Operation of CMOS Inverter:

a pair of switches

When input Vi is grounded (logic 0), the N-Channel MOSFET is unbiased, and therefore
has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line
disconnected from ground. At the same time, the P-Channel MOSFET is forward biased, so it has a
channel enhanced within itself, connecting the output line to the +V DD supply. This pulls the output
up to +VDD (logic 1). The following circuit will illustrate this behavior.

Vi

When input Vi is at +VDD (logic 1), the P-channel MOSFET is off and the N-channel
MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly
performs logic inversion, and at the same time provides active pull-up and pull-down, according to
the output state.

Vi

CMOS Logic Gate Circuits:

The CMOS logic gate consists of following two types of networks

Pull down network (PDN)

Pull up Network (PUN)

The two networks are operated by the input variables, in a complementary fashion. The
following figure will illustrate the basic strucure of the basic structue of the CMOS loic gate ciruits.

Pull Down Network (PDN):

A pull down network is the combination of NMOS transistors. Pull down network will work
when all the inputs of the nerwork will be high (logic 1) and will produce low output ( output Y=0)
and will pull the output node down to ground and zero volatage will appear at the out put terminal
of the network. At the same time, the PUN will be off, and no direct dc path will exist between
VDD and ground.
Examples of the pull down network (PDN) are described below:

In the above examples, pull down network will conduct when both of the inputs A and
B will be high and will produce low output (Y=0).
Pull Up Network (PUN):
A pull up network is the combination of PMOS transistors. Pull up network will
work when all the inputs of the nerwork will be low (logic 0) and will produce high output ( output
Y=1) and will pull the output node up to V DD, establishing an output voltage VY = VDD. At the

same time, the PDN will be off, and no direct dc path will exist between
VDD and ground.
Examples of the pull up network (PUN) are described below:

In the above examples, the pull up nerwork will conduct when both of the inputs will be low
and will produce high output (logic 1) to the terminal VDD of the network.
CMOS Applications in Technology:
CMOS technology is widely used in

Microprocessors

Microcontrollers

Static RAM

Digital Logic Circuits

Image Sensors

Data Converters

Advantages:

Low power consumption

CMOS devices are high noise immunity and low static power consumption.
High density of logic function on a chip
Reduces the complexity of the circuit
Scaling down increases CMOS speed

Disadvantages:

Leading edge processes are not characterized and tuned for analog circuit design.
In the scaling process some second order device characteristics, such as subthreshold
operation, are usually ignored or paid less attention, and their cancellation is more

desired than their improvement.

Mismatch in CMOS devices is relatively high. This is specially hindering the reliability
of analog processing in vision chips.