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CHAPTER - 1)

Abstract:1) WHY DO WE USE VHDL CODE FOR DIGITAL CIRCUITS ???


In electronics, a hardware description language (HDL) is a specialized computer
language used to program the structure, design and operation of electronic circuits, and most
commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit
that allows for the automated analysis, simulation, and simulated testing of an electronic circuit. It
also allows for the compilation of an HDL program into a lower level specification of physical
electronic components, such as the set of masks used to create an integrated circuit.
A hardware description language looks much like a programming language such as C; it is a
textual description consisting of expressions, statements and control structures.

2)

ADVANTAGES & DISAVANTAGES:-

VHDL offers several advantages to the system level designer.Some of them are Standard
language Fully expressive language Hierarchical Configurable Tool availability Consistency
and completeness checks automatic Tight coupling to lower levels of design Supports hybrid
modeling Portable.
Disadvantages VHDL is verbose, complicated and confusing Many
different ways of saying the same thing Constructs that have similar purpose have very
different syntax (case vs.
select) Constructs that have similar syntax have very different semantics (variables vs
signals) Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs
latch vs combinational)

APPLICATIONS:VHDL is commonly used to write text models that describe a logic


circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A
simulation program is used to test the logic design using simulation models to represent the logic
circuits that interface to the design.

CHAPTER 2)-

Introduction to
Digital Concepts

In science, technology, business, and, in fact, most other fields of


endeavour, we are constantly dealing with quantities. Quantities are
measured, monitored, recorded, manipulated arithmetically,
observed, or in some other way utilized in most physical systems. It
is important when dealing with various quantities that we be able to
represent their values efficiently and accurately. There are basically
two ways of representing the numerical value of quantities: analog
and digital.

Analog Representation
In analog representation a quantity is represented by a voltage,
current, or meter movement that is proportional to the value of that
quantity. Analog quantities such as those cited above have an
important characteristic: they can vary over a continuous range of
values.

Digital Representation
In digital representation the quantities are represented not by proportional quantities but by symbols
called digits. As an example, consider the digital watch, which provides the time of day in the form of
decimal digits which represent hours and minutes (and sometimes seconds). As we know, the time of
day changes continuously, but the digital watch reading does not change continuously; rather, it
changes in steps of one per minute (or per second).

Digital Circuits consists of :Combinational & Sequential circuits


Let's define both:1) Combinational logic circuits:- Combinational
logic refers to circuits whose output is strictly
depended on the present value of the inputs. As soon as inputs
are changed, the information about the previous inputs is lost,
that is, combinational logics circuits have no memory. In many
applications, information regarding input values at a certain
instant of time is required at some future time. Although every
digital system is likely to have combinational circuits.

2) Sequential logic circuits:systems encountered in practice also include memory elements,


which require that the system be described in terms of sequential
logic. Circuits whose outputs depends not only on the present
input value but also the past input value are known as
sequential logic circuits.
A general block diagram of a sequential circuit is shown below in

Most

CHAPTER 3)
VHDL Basics:VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated
Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction
ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from
that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described
hierarchically. Timing can also be explicitly modeled in the same description.
The VHDL language can be regarded as an integrated amalgamation of the following languages:
sequential language +
concurrent language +
net-list language +
timing specifications +
waveform generation language => VHDL
Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system
with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also
be generated using the same constructs. All the above constructs may be combined to provide a comprehensive description
of the system in a single model.

IntroductionofHardwareDescriptionlanguage.(VHDL)
WhatdoesHDLstandfor?
HDLisshortforHardwareDescriptionLanguage
VHDLVeryHighSpeedIntegrated
CircuitHardwareDescriptionLanguage
WhyweuseHDL?
Bydescribingthedesigninahighlevel(=easytounderstand)language,we
cansimulateour
designbeforewemanufactureit.Thisallowsustocatchdesignerrors,i.e.,
thatthedesigndoes
notworkaswethoughtitwould.
Simulationguaranteesthatthedesignbehavesasitshould
Thedesignprocessisa6stepcycle:
Definethedesignrequirement
DescribethedesigninVHDLcode
Simulatethesourcecode
Synthesize,optimize,andfitthedesign
Simulatethedesign
Implementthedesign
VHDLusesasimulationcycletomodelthestimulusandresponsenatureof
digitalhardware
EveryVHDLdesigndescriptionconsistsofatleastoneentity/architecture
pair,oroneentity
withmultiplearchitectures.
TheentitysectionisusedtodeclareI/Oportsofthecircuit.Thearchitecture
portiondescribes
thecircuitsbehavior.
Abehavioralmodelissimilartoablackbox.
Standardizeddesignlibrariesareincludedbeforeentitydeclaration.
Includelibraryieee;beforeentitydeclaration.
ieee.std_logic_1164definesastandardfordesignerstouseindescribing
interconnectiondata
typesusedinVHDLmodeling.

ieee.std_logic_arithprovidesasetofarithmetic,conversion,comparison
functionsforsigned,
unsigned,std_ulogic,std_logic,std_logic_vector.
Ieee.std_logic_unsignedprovidesasetofunsignedarithmetic,conversion,
andcomparison
functionsforstd_logic_vector.
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Anentitydeclarationdescribestheinterfaceofthecomponent.Avoidusing
Alterasprimitive
nameswhichcanbefoundat
c:/altera/91/quartus/common/help/webhelp/master.htm#
PORTclauseindicatesinputandoutputports.
Anentitycanbethoughtofasasymbolforacomponent.
PORTdeclarationestablishestheinterfaceoftheobjecttotheoutsideworld.
ThreepartsofthePORTdeclaration
Name
Anyidentifierthatisnotareservedword.
Mode
Modes:Therearefourdefaultmodesin
VHDL
in:inputintotheentity(unidirectional)
out:outputfromtheentity(unidirectional)
inout:inputandoutputtoandfromtheentity(bidirectionalsignals)
buffer:behavesinasimilarwayasinout,butthesourceofthebuffered
signalisalways
determinedbythedrivingvalueoftheport.
Datatype
Anydeclaredorpredefineddatatype.
SamplePORTdeclarationsyntax
Architecturedeclarationsdescribetheoperationofthecomponent.
Manyarchitecturesmayexistforoneentity,butonlyonemaybeactiveata
time.
Anarchitectureissimilartoaschematicofthecomponent.
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ModelingStyles:
Therearethreemodelingstyles:
Behavioral(Sequential)
Dataflow
Structural
VHDLprovidestwodifferenttypesofexecution:sequentialandconcurrent.
Differenttypesofexecutionareusefulformodelingofrealhardware.
Supportsvariouslevelsofabstraction.
Sequentialstatementsviewhardwarefromaprogrammerapproach.
Concurrentstatementsareorderindependentandasynchronous
DataTypes
Therearescalarandarraydatatypesin
VHDL.
arraytypesexample
string
abc
bit_vector1001
charactera
bit
10
std_logic0forcing0
1forcing1
xforcingunknown
zhighimpedance
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dontcare
Lweak0
Hweak1

Uuninitialized
boolean
truefalse
real
2.351.0E+38
DataflowStyle:
SequentialStyle:
StructuralStyle:

Hardware Abstraction
VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and
one or more internal views. The internal view of the device specifies the functionality or structure, while the external view
specifies the interface of the device through which it communicates with the other models in its environment. Figure I.I
shows the hardware device and the corresponding software model.
The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models. For
example, a device modeled at a high leyel of abstraction may not have a clock as one of its inputs, since the clock may not
have been used in the description. Also the data transfer at the interface may be treated in terms of say, integer values,
instead of logical values. In VHDL, each device model is treated as a distinct representation of a unique device, called an
entity in this text. Figure 1.2 shows the VHDL view of a hardware device that has multiple device models, with each device
model representing one entity. Even though entity I through N represent N different entities from the VHDL point of view, in
reality they represent the same hardware device.

CHAPTER 4)
IntroductionofsimulatorsoftwareQuartusII
Theory:
1.Creatingaproject
2.SynthesizingacircuitfromVHDLcodeusingtheQuartosIIIntegratedSynthesistool
3.FittingasynthesizedcircuitintoanAlteraFPGA
4.Examiningthereportontheresultsoffittingandtiminganalysis
5,examiningthesynthesizedcircuitintheformofaschematicdiagramgeneratedbythe
RTLViewertool
6.MakingsimpletimingassignmentsintheQuartosIIsoftware
Creatingaproject
Eachlogiccircuit,orsubcircuit,beingdesignedwiththeQuartusIIsoftwareiscalleda
project
SelectFile>NewProjectWizardtoreachawindowthatindicatesthecapabilityofthis
wizard.PressNexttogetthewindow.
2.Settheworkingdirectorytobequartus_tutorial;ofcourse,youcanuseadirectorynameof
yourchoice.
Theprojectmusthaveaname,whichisusuallythesameasthetopleveldesignentitythat
willbeincludedintheproject.
Chooseaddersubtractorasthenameforboththeprojectandthetoplevelentity
PressNext.
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Thiswindowmakesiteasytospecifywhichexistingfiles(ifany)shouldbeincludedinthe
project.AssumingThatwedonothaveanyexistingfiles,clickNext,whichleadstothe
window.

Inthiswindow,wecanspecifythetypeofdeviceinwhichthedesignedcircuitwillbe
implemented.
ChoosetheStratixmenuitemasthetargetdevicefamily.WecanlettheQuartusII
softwareselectaspecificdevicein
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thefamily,orwecanchoosethedeviceexplicitly.Wewilltakethelatterapproach.Fromthe
listofavailable
devices,choosethedevicecalledEP1S10F484C5.PressNext,whichopensthewindow.
Inthiswindowonecanspecifyanythirdpartytoolsthatshouldbeused.Acommonlyused
termforCAD
softwareforelectroniccircuitsisEDAtools,wheretheacronymstandsforelectronicdesign
automation.This
termisusedintheQuartusIImessagesthatrefertothirdpartytools,whicharethetools
developedand
marketedbycompaniesotherthanAltera;othertutorialsshowhowsuchtoolsmaybeused.
Sincewewillrely
solelyontheQuartusIItools,wewillnotchooseanyothertools.PressNext.Now,a
summaryofthechosen
settingsappearsinthescreenshowninFigure9.PressFinish,whichreturnstothemain
QuartusIIwindow,but
withaddersubtractorspecifiedasthenewproject,inthedisplaytitlebar,asindicated.
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UsingtheQuartusIITextEditor
ThissectionshowshowtousetheQuartusIITextEditor.Youcanskipthissectionifyou
prefertousesome
othertexteditortocreatetheaddersubtractor.vhdfile,orifyouhavechosentocopythefile
fromthe
qdesigns<versionnumber>\vhdl_verilog_tutorialdirectory.
1.SelectFile>NewtogetthewindowinFigure13,chooseVHDLFile,andclickOK.This
openstheText
Editorwindow.
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2.Thefirststepistospecifyanameforthefilethatwillbecreated.SelectFile>SaveAsto
openthepopup
boxdepicted.IntheboxlabeledSaveastypechooseVHDLFile.IntheboxlabeledFilename
typeaddersubtractor.PutacheckmarkintheboxAddfiletocurrentproject.ClickSave,
whichputsthefile
intothedirectoryquartus_tutorialandleadstotheTextEditorwindow.
3.MaximizetheTextEditorwindowandentertheVHDLcodeintoit.Savethefileby
typing
File>Save,orbytypingtheshortcutCtrls.
4.CompilingtheVHDLCode
TheVHDLcodeisprocessedbyseveralQuartusIItoolsthatanalyzethecodeandgenerate
animplementation

ofitforthetargetchip.Thesetoolsarecontrolledbytheapplicationprogramcalledthe
Compiler.
1.RuntheCompilerbyselectingProcessing>StartCompilation,orbyusingthetoolbaricon
.Asthe
compilationmovesthroughvariousstages,itsprogressisreportedinthewindowontheleft
side.Successful(or
unsuccessful)compilationisindicatedinapopupbox.AcknowledgeitbyclickingOK,
whichleadstothe
QuartusIIdisplay,inwhichwehaveexpandedtheEntityhierarchyinthetopleftcornerto
showallentitiesintheaddersubtractordesign.Inthemessagewindow,atthebottom,various
messagesaredisplayed.Incaseoferrors,therewillbeappropriatemessagesgiven.
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Whenthecompilationisfinished,acompilationreportisproduced.Awindowshowingthis
report,isopenedautomatically.Thewindowcanberesized,maximized,orclosedinthe
normalway,andit
canbeopenedatanytimeeitherbyselectingProcessing>CompilationReportorbyclicking
ontheicon.The
reportincludesanumberofsectionslistedontheleftsideofitswindow.Figure19displays
theCompilerFlow
Summarysection,whichindicatesthatonlyaminisculeamountofchipresourcesareneeded
toimplementthis
tinycircuitontheselectedFPGAchip.
5UsingtheRTLViewer
TheQuartusIIsoftwareincludesatoolthatcandisplayaschematicdiagramofthedesigned
circuit.The
display
isattheRegisterTransferLevelofdetail,andthetooliscalledtheRTLViewer.

CHAPTER 6)
VHDL CODE FOR UP/DOWN COUNTERS &
RESULTS:UP-DOWN counter
Figure shows how to build an up-down counter. The flip flops outputs are connected to
steering networks. An UP control signal produces either down counting or up counting. If the UP
signal is low, Q2, Q1 and Q0 are transmitted to the clock inputs; this results in a down counter. On
the other hand, when the UP is high, Q2, Q1 and Q0 drive the clock inputs and the circuit becomes
an up counter.

Figure Up-Down Counter.

VHDL Program for 4bit Up/Down Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_VHDL is
port( Number: in std_logic_vector(0 to 3);
Clock: in std_logic;
Load: in std_logic;
Reset: in std_logic;
Direction: in std_logic;
Output: out std_logic_vector(0 to 3) );
end Counter_VHDL;
architecture Behavioral of Counter_VHDL is

signal temp: std_logic_vector(0 to 3);


begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif ( Clock'event and Clock='1') then
if Load='1' then
temp <= Number;
elsif (Load='0' and Direction='0') then
temp <= temp + 1;
elsif (Load='0' and Direction='1') then
temp <= temp - 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;

FLOW CHART OF 4 BIT UP DOWN COUNTER USING VHDL CODE

CODE LISTING:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR, up_down : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then

tmp <= "0000";


elsif (C'event and C='1') then
if (up_down='1') then

tmp <= tmp + 1;

else
tmp <= tmp - 1;

end if;
end if;
end process;
Q <= tmp;
end archi;
end process;
Q <= tmp;
end archi;

end process;
Q <= tmp;
end archi;

CHAPTER 5:
Steps to design and implement a circuit specified by
using VHDL Code.

1. Start the Quartus-II software


2. Select File> New project Wizard> Next New Window Opens
3.Select the working directory for your project, give a name etc.
>D:/XYZ
>logic gate
>logic gate >Next

"D:/ XYZ" (does not exist). Do.....


> Yes >New window opens
4.Click on Add All to add all the design files to the project directory.
> Next
New window opens
5.Select>Family>Cyclone II
>Target device
>EP2C35F672C6
>Filters>Any ; Pin out> Any; Speed gr> Any
Show Adv. Devices> Next new window appears
6. >Next

{No need of selecting EDA Tool}

New window opens.


7.Summary Window appears {Show all details of our design}
> Finish
new window opens
8. Quartus -II D:/XYZ/logic gate
9. Separately type the VHDL code in the text editor as follows
LIBRARY ieee;
USE ieee.std_logic _116y.all;
ENTITY logic gate is
PORT (X1,X2; IN STD_LOGIC
Y: OUT STD_LOGIC);
........................................................................................
..........
Note: a)File> New>VHDL File>OK>Text Editor will open
b)File >Save as>logic gate in XYZ>Save
ARCHITECTURE arch1 of logic gate is
BEGIN
y=(X1 or X1)

END arch1;
Processing > Start> Start Ana/&i/abo.
10. Compile the saved file (logic gate)
Select Start Analysis and Elaboration to check syntax, if any ;
Click Ok
11. After compilation, we need a vector waveform file to simulate out design
files.
FUNCTIONAL SIMULATION
12. To check the correctness of our logic operation of the synthesised circuit.
select assignment> setting> from dropdown> select simulation options>
simulation mode>
run simulation > click ok
13. >processing
>functional simulation Net list new window opens
Functional simulation Net list generation was successful
> click OK
14. Now we can run functional simulation
>Processing>Start simulation
Note: new window opens showing simulation waveform output.

SCOPE OF VHDL CODING:


VHDL is a hardware description language which describes the behavior through program or writing a
specific code. VHDL is a language used for testing and verification.

VHDL is an important part of VLSI. VLSI which is known as very large scale integration is a field,
which deals with the integration of large designs in a single silicon chip. VLSI Has basically two
areas, that is FRONTEND and BACKEND.
FRONTEND deals with the designing of our hardware and testing it. But this designing and testing is
done by writing a program or coding it in VHDL. We generally code the behavior of our design and
observe its functionality. There are many other constraints that we observe in FRONTEND DESIGN,
these are timing analysis, area, speed. We can also optimize our design. All these things are
accomplished through VHDL. FRONTEND design is used for Digital designing and simulation.
BACKEND deals with the fabrication section. But before fabrication. But before sending to
fabrication we optimize our design. This optimization is different from FRONTEND optimization.

This optimization is for the transistors. The design which has come from FRONTEND, its internal
schematic is observed in BACKEND. So the optimization of the analog components is also must and
important.
WHY VHDL?
In todays world every device is automated and automatic. Take for example a stepper motor, even
a stepper motor can be controlled through an IC. Also every electronic device has a microprocessor.
So the IC has become a common thing in every circuit.
IC is made by a process called FABRICATION. The average time for FABRICATION is about 3 months.
Also the cost involvement in fabrication is too high.
Suppose if a particular IC doesnt give you the desired results, then your money and time goes
waste. So the only thing that we can do is to do a through verification of our design before sending
it to FABRICATION.
The whole designing process starts from FRONTEND. This is where VHDL comes to play. Through
VHDL we can model design with higher level of abstraction. VHDL has the capability to test any
circuit and we can even select our test vectors for worst conditions to understand its performance.
Also the importance of VHDL is high due to many reasons. Firstly all semiconductor companies
spend 70% time for verification and verification is simply impossible without VHDL. Also through
VHDL we can edit our design for better performance. This saves a lot of time. For testing small
circuits we used to use bread boards, but when it comes to microprocessor it becomes impossible
to test and analyze it and also we waste a lot of time.
This semiconductor industry is a fast growing industry and with unbelievable future aspects. In
INDIA only verification is done and all designing work is done in abroad.
So the requirement and demand for good verification engineers is high.

BIBLIOGRAPHY:
. VHDL basics by Jayaram Bhaskar
. Digital Circuits by Anand Kumar
. Quartus II designed by altera
.www.google.com
.www.wikipedia.com

CONCLUSION:
Many VHDL constructs, although useful for simulation
and other stages in the design process, are not relevant
to synthesis. A sub-set of VHDL only can be used for
synthesis.
A construct may be fully supported, ignored, or
unsupported.
Ignored means that the construct will be allowed in the
VHDL file but will be ignored by the synthesis tool.
Unsupported means that the construct is not allowed

and the code will not be accepted for synthesis.