Gate-induced Barrier Field Effect Transistor (GBFET) – A New Thin Film
Transistor for Active Matrix Liquid Crystal Display Systems
M. Jagadesh Kumar1 and Ali A. Orouji2
1
Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India
2
Department of Electrical Engineering, Semnan University, Semnan, Iran
E-mail: mamidala@ieee.org aliorouji@ee.iitd.ac.in
Abstract
Using two-dimensional simulation, we report a new
Gate-induced Barrier Field Effect Transistor (GBFET)
which exhibits at least three orders of magnitude less
OFF state leakage current when compared to a
conventional poly-Si TFT. We demonstrate that the
GBFET is completely free of pseudo-subthreshold
conduction making it a very attractive device for active
matrix liquid crystal display systems.
1. Introduction
Polycrystalline thin film transistors (TFTs) are
extensively used in active matrix liquid crystal displays
(AMLCDs) [1] because polysilicon can be easily
deposited on large area substrates using low
temperature chemical vapor deposition methods.
Unlike in the case of amorphous silicon with low field-
effect mobility, poly-Si TFTs due to their larger carrier
mobility can be easily incorporated in the driving
circuitry on the same substrate used for AMLCDs
resulting in a drastic reduction in the assembly
complexity, cost and size of the display [1]. It is also
important to build polysilicon TFTs with channel
lengths less than 1 micron for high density, high
resolution AMLCDs [2,3].
In polycrystalline silicon thin film transistors, grain
boundaries and intragranular defects play a major role
in degrading the carrier transport and influencing the
poly-Si TFT characteristics. Compared to the
MOSFETs fabricated on single crystal silicon, poly-Si
TFTs exhibit poor device characteristics in terms of
threshold voltage, subthreshold swing, leakage current,
mobility and transconductance. The major drawback of
poly-Si TFTs is their large OFF state leakage current.
For applications as pixel switching elements for flat
panel liquid crystal displays, reducing the OFF state
Proceedings of the 19th International Conference on VLSI Design (VLSID’06)
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leakage current of the poly-Si TFTs is very critical. A
number of device structures have been reported in
literature to circumvent the undesirable leakage current
in poly-Si TFTs [4-8]. One of the useful techniques is
to reduce the number of grains in the channel using
excimer laser annealing [4,5]. Since the grain size
increases and the number of grain boundaries
decreases with annealing, the carrier mobility increases
improving the device switching characteristics.
However, all these novel structures are still based on
polysilicon in which the channel conduction is due to
the control of the grain boundary potential barrier in
the channel by the applied gate voltage.
For high-speed low power display applications, it is
very critical to reduce the OFF state leakage current of
the TFTs. In conventional poly-Si TFTs, the potential
barrier around the grain boundaries in the undoped
channel controls the channel conduction. However,
grain boundaries are also the reason for causing the
pseudo-subthreshold conduction resulting in a large
OFF state leakage current. An ideal TFT, therefore,
should have no grain boundaries. The absence of grain
boundaries will cause the grain-boundary potential
barriers to disappear and the TFT becomes
uncontrollable. In this paper, we demonstrate that even
if the entire polysilicon film is converted into single
crystal silicon using, for example, pulsed wave laser
annealing, we can still induce large potential barriers
in the channel using a modified gate consisting of two
p+ poly side gates and one n+poly main gate. Using
two-dimensional simulation, we show that the
proposed Gate-induced Barrier Field Effect Transistor
(GBFET) will exhibit at least three orders of
magnitude less OFF state leakage current when
compared to a conventional poly-Si TFT. We
demonstrate that the GBFET is completely free of
pseudo-subthreshold conduction making it a very
attractive device for active matrix liquid crystal display
systems.
 Table 1: Simulation parameters used in MEDICI 2. Effect of grain boundaries

Parameter Value Using excimer laser annealing, it is now possible to

+
Doping of n source/drain 10 cm-3
19 have just one or two grain boundaries in the center of
Trap density at the grain boundary 1013 cm-2 the channel [4,5]. As an example, a conventional poly-
Electron trap energy relative to the 0.51 eV Si TFT (C-TFT) with a single grain boundary in the
conduction band undoped channel is shown Fig. 1(a). The potential
Hole trap energy relative to the 0.51 eV distribution in the channel of the C-TFT, simulated by
valence band us using the two-dimensional simulator MEDICI [9], is
Capture rate for electrons and holes 10-8 cm3/sec shown in Fig. 1(b). The simulation parameters used in
Width of the grain boundary (GB) 10 nm MEDICI are given in Table 1. It clearly shows the
Polysilicon channel layer thickness 50 nm formation of a potential barrier at the grain boundary
due to carrier trapping. The C-TFT can be turned ON
Gate oxide thickness 10 nm
or OFF by controlling the height of the potential
Channel length L 0.4 µm
barrier by applying a gate voltage. Unlike in the case
p+-poly gate work function 5.25 eV of single crystal silicon MOSFETs, channel
n+-poly gate work function 4.17 eV conduction in a poly-Si TFT is not controlled by the
accumulation charge density modulation by the gate.
Gate As a result, a pseudo- subthreshold region appears in
the transfer characteristics of the poly-Si TFT resulting
n+ Poly-Si in an unacceptable OFF state leakage current [10].
Source SiO2 Drain Using MEDICI, in order to examine the pseudo-
subthreshold region, we have simulated the transfer
N+ N+ characteristics of a conventional polysilicon TFT (C-
TFT) having a single grain boundary in the center of
Grain Boundary the channel and a conventional single crystal silicon
(a)
SOI MOSFET (C-SOI) whose cross-section and
channel potential distribution are shown in Fig. 2. In
our simulations, for both the structures, we have
chosen identical dopings, silicon film thickness,
Central Barrier channel length, gate oxide thickness and gate work
functions as given in Table 1.

(b)
Drain
Source
Fig. 1 (a) Schematic cross-section of a conventional poly-Si
TFT (C-TFT) with a single grain boundary in the center of
the undoped channel and (b) The simulated potential
distribution in the channel for VGS = 0 V and VDS = 0 V.
3. Pseudo-subthreshold region
From the transfer characteristics of C-TFT
and C-SOI shown in Fig. 3, the pseudo-subthreshold
region is clearly visible in the polysilicon TFT with a
central grain boundary. However, in the case of C-SOI,
the transfer characteristic is very steep but due to the
undoped channel, its threshold voltage is negative and
the device conducts a large current even at zero gate
voltage. An ideal TFT for AMLCDs application would
have been one with a positive threshold voltage and an
undoped single crystal silicon channel for achieving
large carrier mobility and steep subthrehold slope. But
unfortunately, single crystal silicon cannot be
deposited on large area glass substrates using low
deposition temperatures. However, it has been
recently demonstrated experimentally that using
continuous wave laser annealing [11], it is possible to
convert the entire poly-Si thin film layer into single
crystal silicon even on large area substrates. After

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 Gate annealing, all the grain boundaries in the channel will
disappear as shown in Fig. 2 (a) and there will be no
n+ Poly-Si potential barriers to control the channel conduction as
Source SiO2 Drain shown in Fig. 2 (b). With no grain boundary induced
potential barriers in the channel, the TFT will conduct
N+ Undoped N+ even at zero gate bias. In this paper, using two
dimensional simulation, we demonstrate for the first
time that using gate engineering, one can induce
artificial potential barriers in the single crystal silicon
(a) channel whose height can then controlled by the gate
voltage allowing the TFT to be switched ON and OFF.

4. Gate induced barrier field effect tran-

(b)
Fig. 2 (a) Schematic cross-section of a single crystal silicon TFT
(C-SOI) with no grains in the channel and (b) Simulated channel
potential distribution for VGS = 0 V and VDS = 0 V.
Fig. 3 Transfer characteristics of a conventional poly-Si
TFT (C-TFT) with a single grain boundary in the center
channel compared with that of a single crystal silicon TFT
(C-SOI) with no grains.
sistor (GBFET)
The cross-section of the proposed gate induced
barrier field effect transistor (GBFET) is shown in Fig.
4(a). This structure can be fabricated using
conventional poly-Si TFT fabrication procedures.
However, before the source/drain implantation is
carried out, the polysilicon can be converted into
single crystal silicon using continuous wave laser
irradiation [11]. In GBFET, there are two p+
polysilicon side gates (LS) on either side of the n+
polysilicon main gate (LM). Due to the work function
difference between the p+ polysilicon and n+
polysilicon gates, as indicated by MEDICI simulations,
two side potential barriers are induced in the channel
region as shown in Fig. 4(b). In the absence of a gate
voltage, these large potential barriers, larger and wider
than the grain boundary induced potential barrier
shown in Fig. 1(b), do not permit any current to flow
from the drain to the source. If a positive gate voltage
is applied, the height of the induced potential barrier
will decrease allowing the current to flow through the
channel.
In other words, the channel conduction is controlled
by the accumulation charge density modulation by
manipulating the gate induced side barriers in the
single crystal silicon channel. However, we need to
examine whether the GBFET will exhibit (i) a positive
threshold voltage and (ii) a pseudo- subthreshold free
transfer characteristic.
In Fig. 5, the simulated transfer characteristics of
the GBFET are compared with that of the conventional
crystalline silicon SOI MOSFET (C-SOI). It is clearly
seen that the GBFET exhibits a steep subthreshold
slope without any pseudo-subthreshold region. When
compared to the transfer characteristic of the
conventional poly-Si TFT (C-TFT) shown in Fig. 3,
the OFF state leakage current of GBFET is at least few

Proceedings of the 19th International Conference on VLSI Design (VLSID’06)

1063-9667/06 $20.00 © 2006 IEEE
 Gate
p+ poly n+ poly p+ poly
Source SiO2 Drain

N+ Undoped N+

(a)

Fig. 6 Simulated potential distribution of GBFET

showing the induced side potential barriers in the
undoped channel for VGS = 0 V and VDS = 1 V.

orders of magnitude smaller. In many techniques

(b)
Fig. 4 (a) Schematic cross-section of GBFET and (b) Simulated
potential distribution showing the induced side potential barriers
in the undoped channel for VGS = 0 V and VDS = 0 V.
reported in literature, a reduction in the OFF state
leakage current also leads to a reduction in the ON
state current [4-8]. This is detrimental for the device
operation. However, in the GBFET, we observe that
the ON state current is unaffected even while the OFF
state current reduces by three orders of magnitude. The
presence of the gate induced potential barriers in the
channel also cause the threshold voltage to be positive.
The simulated potential distribution of the GBFET for
VDS = 1 V is shown in Fig. 6. Even in the presence of
increased drain voltage, the side potentials are clearly
present in the channel of the GBFET demonstrating its
improved performance at higher drain voltages.

5. GBFET with single grain boundary

Fig. 5 Comparison of the transfer characteristics of GBFET
with that of a single crystal silicon TFT (C-SOI) with no grains
in the undoped channel.
5. Simulation results
It is also important to see what would be the
transfer characteristic of the proposed GBFET if a
grain boundary is introduced in the middle of the
channel. To investigate this, we have compared in Fig.
7, the transfer characteristic of the GBFET and the
conventional polysilicon TFT both having a single
grain in the channel. It is very clear that if a grain
boundary is present in the channel of the GBFET, the
transfer characteristic will again show a diminished
subthreshold slope similar to that of the conventional
TFT indicating that the presence of grains in the
channel is detrimental to the operation of the device.

Proceedings of the 19th International Conference on VLSI Design (VLSID’06)

1063-9667/06 $20.00 © 2006 IEEE

Fig. 7 Comparison of the transfer characteristics of
GBFET and a conventional polysilicon TFT both having
a single grain boundary in the middle of the channel. The
transfer characteristic of a single crystal silicon TFT (C-
SOI) with no grains in the undoped channel is also
shown.
6. Conclusions
In conclusion, using two-dimensional simulation, we
have reported for the first time, a new gate-induced
barrier field effect transistor (GBFET) whose leakage
current is several orders of magnitude smaller than that
of the conventional polysilicon TFTs and the proposed
device is completely devoid of the pseudo-
subthreshold region. The GBFET, with its ideal
characteristics is a perfect candidate in many
applications such as active matrix liquid crystal
displays (AMLCDs), random access memories, read
only memories, linear image sensors, thermal printer
heads and photodetector amplifiers [12-15].
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