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a)
a) D -1 0
a 2-
C)
. 0
0
n
0 -1 -2 -3 -4 -5 -6
t
Drain-to-Source Voltage (V)
J
4 5
Drain-to-Source Voltage (V) Fig. 4. Output characteristics of P-SiC SBMFET for different gate currents.
A. _ 100-
0 U)
c: 50- (a)
0
0 0-
0
cJ 0 -10 -20 -30 -40 -50 -60
L-
Drain current (pA/Irm)
Distance from Source to Drain (gim)
IG= -1 AItm
cJ
U-1 a)
0 0-
(b)
L-
A.-
0
a)
uJ (b) 30 40 50
Epilayer Thickness (urn)
5 10 15 20 25 30
Distance from Source to Drain (pim) Fig. 5. Current gain versus (a) drain current and (b) epilayer thickness of P-
SiC SBMFET.
Fig. 3. (a): Injected electron profile and (b) Electric field profile in the
channel for different drain voltages. The current gain variation with drain current for the P-SiC
SBMFET is shown in Fig. 5(a). The gain variation with
shown in Fig. 3(b). Both these results confirm the phenomena epilayer thickness is shown in Fig. 5(b). It is clearly seen that
of conductivity modulation due to plasma formation in the P- the P-SiC SBMFET has a reasonable current gain. Most
SiC drift region. Although SiC is a wide bandgap material reported BMFETs on silicon have a similar range of current
(3.9 eV), this plasma formation and its modulation by the gain.
drain voltage are responsible for the extremely good output
characteristics with low ON voltage drop as shown in Fig. 4 The blocking voltage variation with epilayer thickness is
for different gate currents. shown in Fig. 6. In order to obtain the correct blocking
voltage, the Schottky gate is reverse biased at +10 V to ensure
Reverse Characteristics," IEEE Trans. on Electron Devices,
-5000 Vol.48, pp.2695-2700, Dec. 2001.
[4] T. Hatakeyama, J. Nishio, C. Ota and T. Shinohe, "Physical
V =10 V Modeling and Scaling Properties of 4H-SiC Power Devices,"
> -4000 Proceedings of the International Conf on Simulation of
Semiconductor Processes and Devices, 2005, SISPAD'05, 01-
a) 03 Sep. 2005, pp.171-174
[5] MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto CA,
> -3000 1997.
[6] ATLAS User's Manual, Silvaco, Ca, 2005.
-( -2000
0
0 M. Jagadesh Kumar (SM'1999) was born in
Mamidala, Nalgonda District, Andhra Pradesh,
India. He received the M.S. and Ph.D. degrees in
-1000l electrical engineering from the Indian Institute of
20 30 40 50 Technology, Madras, India. From 1991 to 1994, he
Epilayer Thickness (gim) performed post-doctoral research in modeling and
processing of high-speed bipolar transistors with the
Department of Electrical and Computer Engineering,
Fig. 6. Blocking voltage variation of P-SiC SBMFET versus epilayer University of Waterloo, Waterloo, ON, Canada. While with the University of
thickness. Waterloo, he also did research on amorphous silicon TFTs. From July 1994 to
December 1995, he was initially with the Department of Electronics and
Electrical Communication Engineering, Indian Institute of Technology,
that the drift region between the gates is completely pinched Kharagpur, India, and then joined the Department of Electrical Engineering,
off and the device is in OFF state. As can be seen in Fig. 6, the Indian Institute of Technology, Delhi, India, where he became an Associate
P-SiC SBMFET has a very high blocking voltage (1200 V at a Professor in July 1997 and a Full Professor in January 2005. His research
epilayer thickness of 20 ptm) and the blocking voltage interests are in Silicon Nanoelectronics, VLSI device modeling and
simulation, integrated-circuit technology, and power semiconductor devices.
increases with epilayer drift region thickness. He has published extensively in the above areas with more than 110
publications in refereed journals and conferences. His teaching has often been
IV. CONCLUSION rated as outstanding by the Faculty Appraisal Committee, IIT Delhi.
SiC is the most promising material for power devices Dr. Kumar is a Fellow of Institution of Electronics and Telecommunication
because its dielectric breakdown field is six times greater than Engineers (IETE), India and a Senior Member of IEEE. He is on the editorial
that of silicon, it can be used at high temperatures, it has a board of Journal of Nanoscience and Nanotechnology and also on the
Editorial Board of IETE Journal of Research as a subject area Honorary
high thermal conductivity, and it can be manufactured using Editor for Electronic Devices and Components. He has reviewed extensively
the same process technology that is used for silicon. Our for different journals including IEEE Trans. on Electron Devices, IEEE
simulation study using MEDICI shows that N-SiC SBMFET Trans. on Device and Materials Reliability and IEEE Electron Device Letters.
He was Chairman, Fellowship Committee, The Sixteenth International
is not a feasible device due to the fact that the Schottky metal Conference on VLSI Design, January 4-8, 2003, New Delhi, India. He was
gate cannot inject holes into the drift region which is essential Chairman of the Technical Committee for High Frequency Devices,
for the plasma formation and hence the conductivity International Workshop on the Physics of Semiconductor Devices, December
modulation of the drift region. We have, however, 13-17, 2005, New Delhi, India.
demonstrated for the first time that a P-SiC Schottky gate
BMFET (SBMFET) can be easily realized if a gate metal with
appropriate work function is chosen. Our study demonstrates
that although SiC is a wide bandgap material, the P-SiC
SBMFET exhibits very low ON voltage drop, good output
characteristics, a reasonable current gain and a high blocking
voltage. This device is expected to result in significant Harsh Bahl was born in Ghaziabad, Uttar Pradesh,
India. He received his BE degree in Electronics from
improvements in a variety of switching applications. Since Shivaji University, Kohlapur, India in 1990. He has
the proposed device is devoid of any PN junctions, the thermal been working as an Aircraft Maintenance Engineer
budget required for the fabrication of the proposed device will with the Indian Air Force since then. He received his
MBA degree in Operations Management from Indira
be less resulting in lower fabrication costs. Gandhi National Open University, New Delhi, India in
2001. He is also an Associate member of the Institute of Electronics and
V. REFERENCES Telecommunication Engineers (IETE) of India. He is presently pursuing M
Tech degree in Integrated Electronics and Circuits from the Department of
[1] S. Ryu, S. Bellone, A. Carnuso, P. Spirito, and G. Vitale "A Electrical Engineering, Indian Institute of Technology, Delhi, India.
Quasi one dimensional analysis of vertical FET devices operated His research areas include simulation of Power Semiconductor Devices
in the bipolar mode," Solid State Electronics, Vol. 26, pp.403- with a focus on BMFETs. His other interests include simulation of Silicon-
413, 1983.. Carbide devices.
[2] A. Caruso, P. Spirito, G. Vitale, G Busatto, G. Ferla and S. Musumeci,
"Performance analysis of a bipolar mode FET (BMFET) with normally
off characteristics," IEEE Trans. on Power Electronics, Vol.3, pp.810-
814, 1988.
[3] Y. Singh and M. J. Kumar, "A New 4H-SiC Lateral Merged
Double Schottky (LMDS) Rectifier with Excellent Forward and