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RC 101: RC Migration
Guide
Application Note
Cadence Design Systems, Inc
4/7/2012
This document outlines the basic synthesis flow supported by Encounter RTL Compiler (referred as RC
throughout the document) and is meant to help the new users to migrate from their existing flow to RC
effortlessly and with utmost ease. Intentionally, the language of the document is kept very simple and
scope is limited to discussing the basic synthesis features provided by RC. The scope of the discussion
does not cover the advanced synthesis features such as low power and physical synthesis. The
commands and features being discussed here are based on RC 11.1 and future releases.
COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED
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Contents
Contents ........................................................................................................................................................ 2
Overview ....................................................................................................................................................... 3
RTL Compiler Optimization Philosophy...................................................................................................... 3
RTL Compiler - Basic Design Flow ................................................................................................................. 3
Major Commands.......................................................................................................................................... 4
Elaborating the Design .............................................................................................................................. 4
Super-Threading........................................................................................................................................ 5
Synthesizing the Design ............................................................................................................................ 6
Generic Synthesis .................................................................................................................................. 7
Global Mapping ..................................................................................................................................... 8
Incremental Synthesis (IOPT) ................................................................................................................ 8
Setting Effort Levels .............................................................................................................................. 8
Generating Reports ................................................................................................................................... 9
Interfacing with Formal Equivalence tool............................................................................................ 10
Interfacing with Place & Route tool..................................................................................................... 11
Simple Synthesis Template ..................................................................................................................... 11
Migration to RC (Common Commands) .................................................................................................. 12
Some Important Commands and Attributes in RC ................................................................................. 14
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Overview
Encounter RTL Compiler (RC) is a fast, high capacity synthesis solution for demanding chip designs. The
core technologies embodied in RCs global synthesis approach produce superior logic and interconnect
structures for nanometer-scale physical design and routing. RTL Compiler complements the existing
Cadence solutions and delivers the best QoR for nanometer-scale designs.
Technology libraries for both the standard cells and the hard-macros
RTL Files implementing the designs functionality
Design Constraints in either SDC format or native RC format
Physical Data (optional) such as LEF libraries, capable and floorplan DEF
Out of the inputs mentioned above, physical data is optional. However, it is advised to provide this data
if it is readily available. The flow has been depicted in the picture below and captures different steps
that are executed as part of the synthesis flow. These steps are run sequentially and allow the designer
to observe and monitor the health of the run by looking at the intermediate results.
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Fig. 1
Major Commands
Following are the most important steps in the RC design flow. Each of these perform a specific function
and have an important role to play in determining the overall optimization strategy. These steps form
the basic building blocks of the optimization script and all other attributes and variables are just
used to guide these basic steps.
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If there are any gate-level netlists read in with the RTL files, RC automatically links the cells to their
references in the technology library during elaboration. Users need not issue any additional command
for linking. Additionaly, the elaborate command automatically elaborates the design by propagating
parameter values specified for instantiation.
At the end of elaboration, RTL Compiler displays any unresolved references (immediately after the key
words Done elaborating):
Done elaborating '<top_level_module_name>'.
Cannot resolve reference to <ref01>
Cannot resolve reference to <ref02>
Cannot resolve reference to <ref03>
...
After elaboration, RC has an internally created data structure for the whole design so users can apply
constraints and perform other operations. Attribute hdl_track_filename_row_col enables RC to keep
track of filenames, line numbers, and column numbers for all instances before optimization. RC uses this
information in subsequent error and warning messages.
Users can generate a generic netlist for a specific Verilog module and all its sub-modules, or a VHDL
entity and all its components using the following command:
elaborate des_top
Super-Threading
RTL Compilers super-threading capability allows you to reduce synthesis turn-around time by
distributing the processing work across multiple CPUs. The CPUs may be on the same machine on which
RTL Compiler was launched, or it may be on different machines across a network.
Unlike previous approaches to parallelize logic synthesis, RTL Compilers capability is unique: the
synthesis results produced through parallel processing are identical to those produced in a non-parallel
run. Therefore, only the turn-around time is affected. In addition, RTL Compiler provides support for
super-thread caching. Caching allows keeping the data and the result associated with a super-threaded
job and retrieving this result when a subsequent job is attempted. Caching can be used regardless of the
number of servers specified (even if no servers are specified).
If you enable super-threading, distributed processing occurs during RTL optimization (synthesize to_generic, global mapping and global incremental phases of the synthesize -to_mapped) command.
RC supports super-threading on LSF and the Sun Grid Engine (SGE).
The following examples illustrate how to set super-threading optimization in various scenarios:
The following example illustrates RTL Compiler L launching a single process for super-threaded
optimization on the machine on which RTL Compiler is currently running. In super-threaded
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The following example illustrates RTL Compiler launching three processes on the current
machine for super-threading. If the current machine has at least three CPUs, a significant turnaround time reduction can be achieved.
rc:/> set_attribute super_thread_servers {localhost localhost localhost} /
RTL Compiler will support super-thread servers of different platform types. The following
example illustrates RTL Compiler launching two remote server processes on the machine
called linux33 and two processes on sun42.
rc:/> set_attribute super_thread_servers {linux33 linux33 sun42 sun42} /
Following are the licensing requirements to launch the remote server processes:
Product/Option
Subsequent
license
RTL Compiler L
RTL Compiler XL
2
Table 1
Synthesizing the design to generic logic (RTL and datapath optimizations are performed in this step)
2.
These two sequential steps are represented by the synthesize command options -to_generic and
-to_mapped
COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED
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The picture above depicts in brief the tasks carried out during each of the individual steps within the
synthesize command. Now well discuss each of these individual steps in more detail.
Generic Synthesis
In this stage, RC performs technology-independent optimizations, including constant propagation,
resource sharing, logic speculation, MUX optimization, and carrysave arithmetic optimizations.
Users can run this stage separately by using the following command:
synthesize to_generic -effort <effort_level>
The medium effort is the default choice but users can use high effort for datapath intensive designs,
or designs for which it is hard to meet timing. RC optimizes sequential instances that transitively do not
fan out to primary output. This information is reported in the log file. Another way to catch these points
is to use output of formal verification. Users can see unmapped points in formal verification and check
for deleted sequential instances in the log file.
Please note that it is not advisable to use this commands while loading a verilog mapped netlist. Please
take care while using this command on a mapped netlist unless it is absolutely necessary, as it will
unmap the design.
COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED
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Global Mapping
In this phase, RC maps the generic gate level netlist to the technology library cells. This step internally is
broken down into two related activities. In the first phase of global mapping, RC performs tentative
structuring and computes the estimated arrival and required times for all the endpoints, based on the
effort level that you set. The result of this stage is the target for each cost group, a concept unique to RC
In the second phase of global mapping, RC restructures paths and computes delays based on the targets
and the effort level that you set. The goal of this phase is to meet the target timing that was inferred in
the previous optimization pass. Finally, RC refines the timing and area of all critical paths by remapping
the cells according to the new surroundings of that particular cell.
Users can run this stage separately by using the following command:
synthesize to_map -no_incremental -effort <effort_level>
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Low: The design is mapped to gates, but RC does very little RTL optimization, incremental clean
up, or redundancy identification and removal. The low setting is generally not recommended
High: RC does the timing-driven structuring on larger sections of logic and spends more time and
makes more attempts on incremental clean up. This effort level involves very aggressive
redundancy identification and removal
Following table captures the summary of the discussion on the synthesize command.
Generic
RTL
Optimization
Mapped
Mapping
Unmapping
Incremental
Optimizations
Mapping
Incremental
Optimizations
-to_generic
RTL
Optimization
Nothing
Unmapping
-to_mapped
RTL
Optimization
Mapping
Unmapping
Incremental
Optimizations
Mapping
RTL
Optimization
Mapping
Placement
Placement
Mapping
Post-placement
Placement
incremental
optimizations
Post-placement
incremental
optimizations
Mapping
Incremental
Optimizations
-to_placed
Post-placement
Incremental
Optimizations
incremental
optimizations
Table 2
Generating Reports
This section discusses how to analyze the synthesis results using the report command and the log file.
COPYRIGHT 2012, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED
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The report timing command should be used to generate reports on the timing of the current design.
The default timing report generates the detailed view of the most critical path in the current design. The
timing report provides the following information:
Use the -from and -to options to report the timing value between two points in the design. The
timing points in the report are designatedwith the <<< indicator.
The area report gives a summary of the area of each component in the current design. The report gives
the number of gates and the area size based on the specified technology library. Levels of hierarchy are
indented in the report.
In the outputs generated by report gates and report area commands, RC shows the technology library
name, operating conditions, and the wire-load mode used to generate these reports. report gates is
the command to generate a report of the gate profile being used in the design. At the end of the gate
report, RC shows the total number of instances and the area for all the sequential cells, inverters,
buffers, logic, and timing-models, if any. To get a report on the total combinational area, users need to
add the logic, inverter, and buffer area numbers.
To check if the final netlist is functionally equivalent to the initial design read into RC,
write_do_lec command is used to generate a dofile to interface with Conformal LEC
To check if the netlist conforms to low power rules defined in the Common Power Format (CPF)
file, write_do_clp command generates a dofile to interface with Conformal Low Power
Note: Using a high effort level during synthesis can creates challenges in some scenarios for
Conformal LEC depending on the design type and optimization aggressiveness. Complex
datapath designs and designs using retiming are often problematic.
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After the completion of the synthesis, users can write out files for processing by the Place & Route
tools. RC generates run files that can be used by the user to load the design seamlessly in the
Encounter Digital Implementation System (EDIS) P&R tool.
Using write_design encounter, RC will generate the following files in the working directory:
top.conf
top.g
top.rc_setup.tcl
top.v
top.enc_setup.tcl
top.mode
top.sdc
To start an EDIS session, users now only need to source the top.enc_setup.tcl file which will in turn load
the necessary files (such as the libraries, the generated netlist file, and SDC constraints) written out by
RC.
Apart from this, RC also writes out other files that can be used by other P&R tools. Following are the
commands used to dump out these files:
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elaborate <top_level_design_name>
read_sdc <sdc_file_name>
set clock [define_clock -period <periodicity> -name <clock_name> [clock_ports]]
external_delay -input <specify_input_external_delay_on_clock>
external_delay -output <specify_output_external_delay_on_clock>
synthesize -to_mapped
Task
Specifying
ibraries
RC Command
RC expects both the link and the target libraries to be specified together as part of
one list. RC automatically infers the references from the library set. Please note that
RC will use cells from both the libraries to build the circuit for design under
consideration.
Ex.
set_attribute library {mylib1.lib mylib2.lib}
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Specifying
Constraints
RC can read in the constraints in either native RC format or it can also read in the
constraints written in SDC format (most of the cases, SDC is made available as part of
the design data).
Ex.
read_sdc TOP.sdc
Following attributes define the DFT configuration within RC. Once these attributes are
set, during synthesis scan is inserted automatically. Please note that scan is added if
some or all the registers pass DFT rules. During mapping, DFT setup is done and
connection of the scan chain happens by invoking "connect_scan_chain" command.
Specifying
DFT
directives
Specifying
Low Power
Directives
Ex.
Define_dft test_clock -period 100 [find / -port clk]
define_dft test_mode -active high [find /-port rst]
define_dft test_mode -active high [find / -port test_mode]
define_dft shift_enable -active high [find / -port se]
set_attribute dft_mix_clock_edges_in_scan_chain false /des*/*
define_dft scan_chain -name chain1 -sdi si -sdo so -shift_enable se
synthesize -to_map (insert the scan structures)
connect_scan_chains (connects the scan chains in the design)
In RC, insertion of clock gating is controlled using following set of attributes. These
attributes need to be set before "synthesize" command.
Ex.
Set_attribute lp_insert_clock_gating true /
set_attr lp_clock_gating_style latch /des*/*
set_attr lp_clock_gating_test_enable scan_enable /des*/*
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Specifying
Low Power
Directives
Synthesizing
the Design
Generating
the Reports
Writing out
the Interface
Files
Once all the optimization directives (including DFT and Low Power) are applied, the
design is ready to be synthesized. In RC, this is done using the "synthesize" command
and this is used in conjunction with the "effort" level
Ex.
ESynthesize -to_mapped -eff high
Many reporting commands exist in RC to analyze the results of the execution. Primary
of these are:
check_design
report area
report timing
In RC, "write_design" command is used to dump out the design database. Verilog
netlist, SDC, DEF and other important files are written out as part of this command
Table 3
When reading in the timing libraries (only Liberty format supported), RC might mark some library
cells as unusable for use. RC can mark a library cell as avoid (dont_use) when the cell exists in the
timing library but does not exist in the physical library (LEF file). This behavior usually surprises the
user when it comes to mapping
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