Dual-gate (FinFET) and Tri-Gate MOSFETs:

Simulation and Design

A. Breed and K.P. Roenker
Department of Electrical and Computer Engineering and Computer Science
University of Cincinnati
Cincinnati, Ohio 45221-0030.
Abstract
The continued downward scaling of silicon MOSFET device dimensions below
one tenth micron has presented new and serious challenges for future integrated
circuit applications. Accordingly, new MOSFET structures, such as the dual-gate
(FinFET) [l] and the Tri-Gate transistor [2], have been proposed to replace the
conventional planar MOSFET. These devices are compatible with conventional
silicon integrated circuit processing, but offer superior performance as the device is
scaled into the nanometer range. However, the physics of the MOSFETs operation
in these new device structures is somewhat different. This study aims to investigate
the differences in performance of these two devices and their device design using a
commercial, three-dimensional numerical simulator ATLAS from Silvaco
International [3].
Introduction
Shown in Figures 1 (a) and (b) are the schematic views of a dual-gate transistor
(FinFET) [l] and a Tri-Gate transistor [2], respectively. Both transistors make use of
a polysilicon gate and have a marked three dimension nature. In the FinFET the
channel is a thin, vertical stripe of silicon (fin) where the gate consists of two
polysilicon electrodes along the vertical sides of the fin located between the source
and drain contacts at the ends of the fin. Typical fin thicknesses range &om 10 nm to
50 nm, while the height of the fin is analogous to the channel width and is larger, e.g.
50 nm. As in a conventional MOSFET, the polysilicon gate length along the direction
of current flow defines the channel length, which is -10 to 50 nm. Tri-Gate transistors
are similar in structure to the FinFETs, but keep the fin width and height the same so
that the polysilicon gate is present on three sides of the silicon channel. Both the
FinFET and the TriGate transistor make use of a raised source-drain structure which
eliminates parasitic resistance and at the same time facilitates local interconnection
and large-scale integration.

Figure 1

Cross sectional view of a FinFET (a) and Tri-Gate (b) transistor.

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Device Modeling
Using commercial modeling software from Silvaco International [3], the
performance of the FinFET and Tri-Gate MOSFET were studied. The devices were
assumed to have an initial body width, height and gate length of 50nm each and one
parameter was varied to study its effect on device behavior, e.g. the sub-threshold
slope and the threshold voltage. The results are shown in Figures 2(a)-2(d).

0.22,

2
0

0.21

i?

.
,

95

8
B

70

-3

65

0.2

I-

J 60

0.19
10

90

Fin Height (nm)

(4

(e)

Figure 2

Threshold voltage 0and subthreshold slope (---) for a FinFET ( 0 ) and a

Tri-Gate Transistor (m) for variations in gate length (a), fin height (b) fin
width (c) and substrate doping (d), respectively.
References

1.

D.Hisamoto, W-C. Lee, J. Kedzierski and C. Hu, IEEE Trans. Elecrr. Dev.,vol.

47, pp. 2320-2325 (December 2000).

2. B. Doyle, B. Boyanov, S. Datta, M. Doczy and R. Chau, Tech. Dig. Symp. VLSI
Technol., pp. 133-134 (2003).
3. ATLAS, Silvaco International, Santa Clara, CA, 2001.

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