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2125
AbstractVoltage balance issue of dc-link capacitors is very important for applications of a cascade multilevel converter or a
modular multilevel converter. In this paper, a novel diode-clamped
modular multilevel converter (DCM2 C) topology is proposed and
a power feedback control method is developed. With the developed
control strategy, the proposed diode-clamped circuit becomes a
controllable closed loop which enables the capacitor voltages to be
clamped by low power rating clamping diodes. The proposed topology and control strategy has quicker response and requires much
fewer voltage sensors than the normally used traditional method;
therefore, the system performance improvement and cost reduction
are expected. Based on the proposed DCM2 C, a novel N +1-level
cascade multilevel topology is proposed for a cascade active power
filter (CS-APF). The simulation and experimental results from the
CS-APF have demonstrated and verified the effectiveness of the
proposed novel topology and control method.
Index TermsCapacitor voltage balance, cascade active power
filter (CS-APF), diode-clamped modular multilevel converter
(DCM2 C), minimum number of voltage sensors.
I. INTRODUCTION
EDIUM- and high-voltage application of power electronic converters is growing, for instance, an active
power filter (APF) which is an ideal choice for power conditioning [1][3]. A high switching frequency is normally required for
such electronic converters to achieve good performance, such
as fast response, good filtering, and low harmonics; however,
the high switching frequency may limit the capacity of a normal two-level converter due to the power loss. A multiple converter configuration may be an effective solution for high-power
medium-voltage applications [4][7], but a bulky transformer is
usually required. Recently, the topology of multilevel converter
Manuscript received February 24, 2012; revised June 2, 2012; accepted July
26, 2012. Date of current version November 22, 2012. This work was supported
by the National 863 Plan 2007AA05Z227, China. Recommended for publication by Associate Editor B. Ozpineci.
C. Gao was with the Department of Electrical Engineering, Tsinghua University, Beijing 100084, China, He is now with the Automation School, Beijing
Institute of Technology, Beijing 100081, China (e-mail: gcz_fly@163.com).
X. Jiang and Y. Li are with the National Key Laboratory of Power Systems,
Department of Electrical Engineering, Tsinghua University, Beijing 100084,
China (e-mail: jiangxj@mail.tsinghua.edu.cn; liyd@mail.tsinghua.edu.cn).
Z. Chen is with the Department of Energy Technology, Aalborg University,
DK-9220 Aalborg, Denmark (e-mail: zch@et.aau.dk).
J. Liu is with the Automation School, Beijing Union University, Beijing,
100101, China (e-mail: jingyunliu@163.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2212915
2126
Fig. 1.
Fig. 2.
Fig. 3.
the voltage drop of the diode and the saturation voltage of the
switch), as shown in Fig. 3(a). Then, udj will rise and udj +1 will
drop until udj = udj +1 . If udj udj +1 , the diode Dj will keep
OFF. Thus, the capacitor voltage relationship is ud1 ud2
. . . udN . ud1 is the dc voltage of the top cell, and udN is the
dc voltage of the bottom cell.
Consequently, if ud1 could be clamped at the same level as
udN , all capacitors would have the same voltage. Fig. 3(b) shows
a downward clamping topology (DCT), which uses the similar
principle to the UCTs. If udj +1 < udj , Cdj +1 will be clamped
by Cdj when Sj 1 is ON, as shown in Fig. 3(b).
Now, the key point is to realize ud1 = udN . The following
part presents a method to solve the problem by using an energy
feedback circuit to form a closed voltage clamping loop with
the clamping diodes. Several energy feedback topologies are
proposed. Fig. 4(a) shows an energy feedback topology based
on an auxiliary full-bridge inverter (AFBI) which shares the dc
bus with the top cell of the UCT (or with the bottom cell of the
DCT). The ac side of the AFBI is connected to the primary of
an isolation transformer Tac . The secondary of Tac is connected
with a rectifier that shares the dc bus with the bottom cell of
the UCT (or with the top cell of the DCT). The winding turning
ratio of Tac is 1: wT . When the AFBI works as a square wave
ac inverter (The output voltage of the inverter is uac .), a square
wave voltage with the same amplitude as uac (wT = 1) will be
induced at the secondary side of Tac . The induced ac voltage is
converted into a dc voltage by the rectifier. If the dc voltage of
cell N is lower than that of cell 1, energy will be transmitted
from Cd1 to CdN via the feedback circuit. Then, udN will rise
and ud1 will drop, so ud1 and udN will be equalized by the
feedback circuit. Therefore, a closed voltage clamping circuit
is realized. Considering the leakage inductance of Tac and the
voltage drop of the switches, wT should be a little larger than 1,
and the output power of the auxiliary circuit can be controlled
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
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TABLE I
SUMMARY OF THREE AUXILIARY CIRCUITS
2128
Fig. 5.
U ac Lm
,
Lm (1/Cac )
s Lm
U C ac
10
s Cac
(2)
1
.
f Cac
(3)
Thus, U C ac f U ac f . U C ac f and U ac f are the fundamental components of U C ac and U ac , respectively. f is the fundamental frequency (frequency of the modulated wave). When
Tac is loaded, there will be switching frequency ripples uC ac
on Cac , and the capacitor Cac should be designed to satisfy the
following expression:
uC ac 0.1ud1 .
(4)
(5)
udN ud1 .
(6)
D is the duty cycle of the drive signal of S11 which is interlocked with S12 . Then, the expression of the current iac2 can be
derived, with which the output power of the auxiliary circuit can
be calculated approximately. Since the switching frequency is
much higher than the fundamental frequency, um and uC ac can
be taken as constant in a switching cycle. Thus, the expression
of iac2 in a switching cycle can be derived, as shown in Fig. 7.
Ts is the switching cycle. During time 0t1 , uT 1 is
uT 1 = ud1 uC ac ud1 Dud1 , (0 D < 0.5).
(7)
(9)
Since the secondary circuit is closed, the current iac2 will rise
from time 0 to t1 according to the following expression:
t
1
(wT uT 1 udN )dt
iac2 (t) 2
wT L 0
D Ts
Equation(6),(7)
ud1
= 2
[wT (1 D) 1]dt,
wT L 0
(0 t t1 ).
(10)
From time t1 to t2 , uac becomes zero, and uT 1 is
uT 1 = 0 uC ac Dud1 .
(11)
At the same time, the current iac2 will drop, and the expression
is
ud1
iac2 (t) 2
wT L
(wT D + 1)dt,
t1
(t1 t t2 ).
(12)
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
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ud1 [wT (1 D) 1]
,
wT2 L
i2 =
ud1 (wT D + 1)
. (13)
wT2 L
When D < 0.5, i1 < i2 . Thus, iac2 will fall to zero before
the end of each cycle and will start from zero at the start of each
cycle (iac2 = 0, t = 0) in the steady state. Then, the expression
of iac2 could be obtained
iac2 (t)
ud1 [wT (1 D) 1]
t,
wT2 L
(0 t t1 ).
(14)
t2
iac2 (t)dt = S1 + S2 =
0
i1 + i2
i2
t1
iac2 (t)dt.
(16)
(17)
Ts
ET s =
P (t)dt ud1
t2
|iac2 (t)| dt
i1 + i2 t 1
iac2 (t)dt
i2
0
u2
wT (1 D) 1
= 2 d1 1 +
wT L
1 + wT D
D Ts
[wT (1 D) 1]tdt
= ud1
w T =2
2D)
,
4L (1 + 2D)
(18)
(0 D < 0.5). (19)
d u2d1 Ts D2 (1 2D)
51
dPT s
=
.
=0D=
dD
dD
4L (1 + 2D)
4
(21)
Similarly, D is replaced by 1D when D 0.5. The relationship of PT s and D is given in Fig. 8, and max(PT s ) can be
used to design the parameters of SHI.
C. Design Rules of the Auxiliary Circuit (SHI)
Considering that the voltage unbalance between cells is
mainly caused by the loss difference and the nonideal drive
pulses, the required power for balance control is usually lower
than 5% of the rated power Pcell . Thus, the current of the clamping diode in the DCM2 C is lower than 5% of the rated current
of the main circuit. However, 20% of the IGBTs rated current
is chosen as the diode rated current for a reliable design. Of
course, the diode should be fast recovery diode and have the
same voltage rating as the IGBTs.
The design of SHI is focused on the auxiliary capacitor Cac
and the auxiliary transformer Lm , L .
According to (4), the design rules of Cac could be obtained
Ts
1
iac1 (t)dt
uC ac =
Cac 0
Ts
Ts
1
wT
wT iac2 (t)dt =
P (t)dt (22)
Cac 0
ud1 Cac 0
Ts
wT
wT Ts max(PT s )
P (t)dt
0.1ud1 (23)
ud1 Cac 0
ud1 Cac
20Ts max(PT s )
,
u2d1
(wT = 2).
(24)
Cac
t=0
Fig. 8.
ET s
u2 Ts D2 (1 2D)
.
= d1
Ts
4L (1 + 2D)
(20)
Equation(20)
u2d1 Ts D2 (1 2D)
.
max(PT s )4(1 + 2D)
(25)
1
Lm Cac
0.1s .
(26)
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Fig. 9.
Similarly for L
1
10f
0.3s .
L Cac
(27)
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
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TABLE II
SUMMARY OF FOUR CASCADE TOPOLOGIES
(29)
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Fig. 10.
C32 =
1
0
C23
1
1
=
2
3
2
.
2
follows:
sin t
C+ =
cos t
cos t
,
sin t
C =
cos t sin t
.
sin t cos t
(32)
(31)
(33)
M
(udj + udM +j )
(35)
D = uF
2
j =1
uF (k) =
M
(udj + udM +j )
= M udav
2
j =1
M
(ud1 + udN ).
2
(36)
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
Fig. 11.
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Fig. 12.
Fig. 13.
cell voltages and udav is the average value of the dc-link voltage
of a phase arm.
C. DC-Link Voltage Control
The dc-link voltage control includes the universal dc-link
voltage control (or phase arm dc-link voltage control) and the
auxiliary circuit control. Fig. 11 shows the universal dc-link
voltage control scheme where ud is the reference voltage, and
uda , udb , and udc are, respectively, the sum of the dc-link voltage
in the relevant arm of phases a, b, and c. Since only the top
and bottom cells dc-link voltage is monitored by the voltage
sensors, uda can be calculated by (37) approximately. G1 is
the gain in (37). Similarly, udb and udc can be calculated. The
errors are the inputs of the proportional-integral regulators. The
outputs of the regulators are multiplied by the phase-locked
loop signals. Thus, the outputs of the universal dc-link voltage
control are the active power reference currents (iP a , iP b , iP c )
for each phase
uda =
j =1
M
(uda1 + udN ). (37)
2
ET line
.
Tline
(39)
(40)
(41)
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Fig. 14.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 15. Relationship between the output voltage and the drive signals of the
equivalent unit.
TABLE III
OUTPUT VOLTAGE OF THE EQUIVALENT UNIT AND SWITCH STATE
.
M
(42)
The drive signals for the six upper switches are shown in
Fig. 16. uphase is the output voltage of a phase arm.
Since the auxiliary circuit control of cell 1 will change the
duty cycle, it will be better if the duty cycle control for cell 1
is independent from that of other cells in the phase arm. The
PWM duty cycle for cell 1(see Fig. 13), and Da is for the other
cells of phase a.
The gain G2 is determined by the following expression:
G2 =
1
.
2M 1
(43)
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
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TABLE IV
SPECIFICATION AND PARAMETERS OF THE SIMULATION MODEL
Fig. 20. DC-link voltages of CS-APF based on DCM2 C with the energy
feedback circuit turned OFF.
Fig. 21.
Fig. 22.
Fig. 19. DC-link voltages of CS-APF (phase a) with the clamping circuit in
operation.
The common-mode voltage of the neutral point of a sevenlevel CS-APF based on DCM2 C is shown in Fig. 22.
The sequence of the waveforms is (from top to bottom)
un , un , and uF a . un is the voltage between the negative pole of
CdN and the neutral point of the power source. It is much lower
than the source voltage. un is the voltage filtered from un by a
low-pass filter with the cutoff frequency of 1 kHz. un is lower
than 200 V. uF a is the voltage of phase arm a of the CS-APF,
and is seven-level voltage.
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Fig. 23.
Fig. 24.
Waveforms of is a , iL a , and iF a .
Fig. 25.
Waveforms of is a and u F a .
DCM2 C.
TABLE V
PARAMETERS OF A SEVEN-LEVEL CS-APF BASED ON DCM2 C
3) Experiment Results: An oscilloscope DSOX2024A produced by Agilent and a scopecorder DL850 produced by Yokogawa are used to collect the experiment data. Fig. 24 shows the
harmonics suppression results of seven-level CS-APF, where
isa is the source current, iL is the load current, and iF a is
the CS-APF current. The harmonics components in the source
current are greatly declined, and the waveform of is becomes
sinusoidal.
The output voltage uF a of phase a in the seven-level CS-APF
is shown in Fig. 25. The harmonics components of the voltage
are much lower than the two-level inverter.
Fig. 26 shows the experiment results with all three-phase
auxiliary circuits in operation. The sequence of the curves is
(from top to bottom) source current isa , CS-APF current iF a ,
common cell dc-link voltage udN , dc-link voltages: uda5 of cell
5, uda4 of cell 4, uda3 of cell 3, uda2 of cell 2, and uda1 of
cell 1. The experiment results of phases b and c are similar to
that of phase a. The process of the system from the start to the
steady state is recorded. The dc-link voltages of CS-APF are
well balanced with the maximum voltage difference less than
2 V. The detailed results of the steady state are presented in
Fig. 27.
For the common cell shared by phases a, b, and c, the auxiliary circuit of one phase is beneficial for voltage balance of
other phases, as shown in Figs. 28 and 29. Fig. 28 demonstrates
the experiment results with auxiliary circuit of phases b and c
GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
Fig. 26.
Fig. 27.
Fig. 28.
in operation. The dc-link voltages ud2 ud5 and udN are about
117 V, while ud1 is higher than the others by about 6 V which
nearly has no effect on the system performance. Fig. 29 demonstrates the experiment results with only auxiliary circuit of phase
c in operation. Still ud1 is the highest, about 21 V higher than
the others. Yet, the system keeps stable without obvious effects
on the system performance.
The experiment with auxiliary circuits out of operation during
the process has been carried out for comparison. The results are
shown in Fig. 30. After the system went into steady state, all
Fig. 29.
Fig. 30.
Fig. 31.
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GAO et al.: DC-LINK VOLTAGE SELF-BALANCE METHOD FOR A DIODE-CLAMPED MODULAR MULTILEVEL CONVERTER
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