DECODER: A slightly more complex decoder would be the n-to-2n type binary decoders.

These types
of decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit combinations, the
decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other
examples.

2:4 DECODER

Table : Truth Table of 2:4 decoder

Fig : Logic Diagram of 2:4 decoder

Representation of 2:4 decoder

3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND gates
are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it takes a
3-bit binary input code and activates one of the 8(octal) outputs corresponding to that code. The truth
table is as follows:

Table : Truth Table of 3:8 decoder

Fig : Logic Diagram of 3:8 decoder

1:8 Demultiplexer
A demultiplexer (or demux) is a device taking a single input signal and selecting one of many dataoutput-lines, which is connected to the single input. A multiplexer is often used with a complementary
demultiplexer on the receiving end. A demultiplexer is a single-input, multiple-output switch.
Demultiplexers take one data input and a number of selection inputs, and they have several outputs.
They forward the data input to one of the outputs depending on the values of the selection inputs.
Demultiplexers are sometimes convenient for designing general purpose logic, because if the
demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function
of the selection bits can be constructed by logically OR-ing the correct set of outputs. Demultiplexer is
called as a distributro, since it transmits the same data to different destinations.

Table : Truth Table of 1:8 DEMUX

Fig : Logic Diagram of 1:8 DEMUX

VERILOG
1:2 DEMUX
TYPE 1
module demux ( D, select, y0, y1);
input D;
input select;
output y0,y1;
wire
y0,y1;
assign y0 = (~select) & D;
assign y1 = select & D;
endmodule
TYPE 2
input D;
input select;
output y0,y1;
wire
y0,y1,N;
and g1(y0, D, N);
and g2(y1, D, Select);
not g0(N, Select);
endmodule
TYPE3
module demux ( D, select, y0, y1);
input D, select;
output y0,y1;
reg y0,y1;
always @( D or select ) begin
if( select == 1b0)
begin
y0 = D;
D
y
0
y1 = 1b0;
end
else
begin
y0 = 1b0;
y1 = D;

end
end
endmodule
2:4 DECODER
module decoder_2_4_data(in,out,en);
input [1:0] in;
input en;
output [3:0] out;
assign out = (en)?(1<<in):4'b0;
endmodule
1:8 Demultiplexer
module demux8_data(select,d,q);
input d;
input [2:0] select;
output [7:0] q;
assign q=d<<select;
endmodule
1:4 Demultiplexer
module demux4_data(select,d,q);
input d;
input [1:0] select;
output [3:0] q;
assign q=d<<select;
endmodule

Other programs
//Full Adder Using Half Adders
//Data Modelling
//Full Adder module
module fadd_data(x,y,s,c_in,c_out);
input x,y,c_in;
output s,c_out;
wire w1,w2,w3;
hadd ha1(x,y,w1,w2);
hadd ha2(c_in,w1,s,w3);

assign c_out=w3|w2;
endmodule
//Half Adder module
module hadd(x_in,y_in,s,c);
input x_in,y_in;
output s,c;
assign s=(x_in^y_in);
assign c=x_in&y_in;
endmodule
//SR Flip Flop
//Behavorial Modelling
module srff_data(c,s,r,q);
input c,s,r;
output q;
reg q=1'b0;
always @(posedge c)
begin
if(s & ~r) q<=1;
else if(~s & r) q<=0;
else if(s & r) q<=0;
end
endmodule
//T Flip Flop
//Behavorial Modelling
module tff_data(c,t,q);
input c,t;
output q;
reg q<=1'b0;
always @(posedge c)
begin
if(t)
q<=~q;
end
endmodule