Bioelectric potential Amplfier Design

Senior Design Project P09004

Table of Contents

Introduction
The following document details each stage of the biopotential amplifier for project
P09004. The amplifiers used for this project are used for both EEG signals and EOG
signals, the difference between these signals is the valuable frequency ranges and
the gains. The EEG amplifiers filter out DC, and then filter out high frequencies
above 50 Hz. The EOG amplifier keeps DC content in order to provide information
about relative position of the eye, and the upper frequency is set at 30 Hz. The
frequency range for the EEG is based on direct interaction and decisions with Dr.
Phillips, and the EOG decision was also made based on direct interaction and
decisions with Dr. Phillips and the conclusion to adhere to the ISCEV EOG standards
for amplifier design. This document details the choice of filter and amplifier
architecture, as well as over voltage protection on the input, the right leg drive
circuitry for noise cancellation. The analog amplifier schematic can be seen below in
Figure 1.

Figure 1: Analog amplifier and filter topology for bioelectric potential signals

HF Reject Circuitry
Theory
The first stage of the biopotential amplifier circuitry is a stage used to reject high
frequency interference picked up from radio frequency signals coupled in through
electrode leads for the EOG and EEG signals. The selected circuitry can be seen in
Figure 2.

Figure 2: Front end HF-reject circuitry

This circuitry provides the transfer function defined by Equation 1, where R1=R2=R,
C1=C1, and C2=C3=C.

VOUT
1
( j )
VIN
1 jR (C 2C1 )
Equation 1

Using the component values in Figure 2, the -3dB cutoff point for the front end
circuitry is 602.859 kHz. Since the frequency range of interest is well below 1 kHz
then this circuitry should not cause any trouble or distorition of the frequency range
of interest. It will help to filter and remove the higher frequency signals that are
coupled in through electrode leads.
Simulation

(1.0000m,-1.0354u)

-2.0

(495.807K,-3.0328)

-4.0

-6.0

-8.0
1.0mHz
10mHz
100mHz
dB(V(U1:-,U1:+)/(V(V3:+)-V(V3:-)))

1.0Hz

10Hz

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

Frequency

Figure 3: PSpice Frequency Sweep for entire circuit examining the effect of the
input HF reject circuitry

As stated before with the given values of resistance and capacitance offers a
frequency cut off of roughly 600 kHz, however in the above simulation Figure 3 the
cutoff frequency is roughly 500 kHz. The reason for this is easily explained due to
two things, both having to do with the fact that the theory for the circuit was
analyzed while considering it on its own rather than included into the rest of the
circuit. Referring back to Figure 1, the next stage after the HF reject circuitry is the
overvoltage protection circuitry and then the Preamplifier. The shift in frequency is
easily explained by stray capcitances in the BJTs and the Preamp. Though both
have small capcitances associated with they are in the same range as the
capacitances of the HF reject circuitry. The HF reject circuitry uses a 10 pF capacitor
and the front end of the Preamp is rated at 2 pF which is enough to cause the shift
seen. This is further shown in Figure 4 which compares simulations swept with just
the circuit itself and then once it was placed into the remaineder of the circuit.

(604.296K,-3.0081)
-2.0

-4.0

(492.843K,-3.0058)

-6.0

-8.0
1.0Hz
10Hz
db(V(C7:2,C9:1)/V(R7:1,V4:-))

100Hz
db(V(U1:-,U1:+)/V(R1:1,R2:1))

1.0KHz

10KHz

100KHz

1.0MHz

Frequency

Figure 4: Graph with the frequency response of both the front end HF reject
circuitry by itself and included into the rest of the circuitry, the green sweep
represents the circuit itself isolated from the rest of the amplifier whereas the red
sweep is made once the rest of the circuitry is included

Experiments
Refer to the appendix for the actual waveform captures (Figure 11, Figure 12, Figure
13, Figure 14) but a summary of useful information can be obtained in Table 1, for
each of these values the input was approximately 100 mV, due to the resolution of
the oscilloscope this may have varied slightly due to noise.
Table 1: Summary of frequency sweep in hardware for front end circuitry

Frequency (Hz)
0
30
100
500000

Amplitude of output voltage

(mV)
108
102
105
67.2

Conclusions
The primary purpose of the HF reject circuitry is remove any noise added to the
signal by RF signals coupling in through long leads. This ties back to the
requirements in that in order to obtain useful bioelectric signals for research then

any signal content outside of the frequency range of interest needs to be filtered
otherwise it could be confused for useful signal. The other big takeaway for this
particular circuitry is that it does not affect the frequency range of interest at all
even with the extra loading caused by the front end.
Overvoltage Protection
It is important that the device be safe for making a direct connection with a person.
It is also impotant to ensure that the device itself is protected from any static shock
that zaps the person so as to ensure that the device is robust, and continues to
operate properly. The chosen overvoltage protection circuitry can be seen in Figure
5.

Figure 5: Overvoltage protection for the input of the amplifier

This circuit provides protection in two directions. If the positive terminal of Vin
becomes too large, greater than approximately 0.7 volts greater than VGND than
the voltage drop across R3 will provide the base current Q1 which in turn causes
current to be drawn from the collector of Q1 which clamps down the voltage and
makes sure that it does not become too large. The same idea follows for the
negative terminal of Vin. The corresponding transistor Q2 is PNP which protects
against overvoltage in the negative direction.
The circuitry also protects a person as well if either terminal of Vout becomes too
high it will provide the base current for any of the transistors, since the voltage drop
from the base to emitter will remain roughly constant, the terminals of Vin will be
pulled down, and the transistors will pull the voltage on the input terminals which
are connected to the individual to VGND.
There were two considered alternatives for this circuit topology, first was to depend
on the overvoltage protection provided by the preamplifier. This was not a valid
option because it did not provide high enough voltage protection to the circuitry and

does not provide any protection for the individual. Another alternative is to provide
clamping diodes. They would operate the same when considering the protection of
the circuitry but they would not provide the same protection of the person. While it
is sufficient to clamp a lower voltage to protect the next amplifier stage it is better
to full short the leads in an overvoltage when it could potentially harm someone.
Amplifiers are designed to have voltage differences, humans however are not so the
chosen architecture offers the best design choice.

Preamplifier circuitry
The input signal is a differential signal of the voltage taken between two electrodes,
but it needs to be a single ended signal, i.e. a referenced to a common point for
useful analog to digital conversion. Referring back to the specifications the required
input impedance is greater than 100 M, and the CMRR is greater than 110 dB. It is
very easy to accomplish this with an integrated component known as an
instrumentation amplifier. Since it is easy to match various components on an
integrated chip the CMRR is much better for an instrumentation amplifier than for
some topology created by other amplifiers. Also modern manufacturing techniques
have allowed for astounding input impedances. The topology chosen can be seen in
Figure 6, this uses the INA128 instrumentation amplifier.

Figure 6: Preamplifier stage utilizing the INA128 instrumentation amplifier

The specifications for the INA128 instrumentation amplifier guarentee that the input
impedance is at least 1010 ohms which is 10 G, which greatly exceeds the
specification. Furthermore the INA128 is rated at a CMRR of between 100 and 120
dB depending on the gain. So a gain must be selected and tested in order to ensure
that it meets specifications. Looking at C7 and C8, they are placed there as a
common PCB practice to help noise reduction, by placing these capacitors as
physically close to the amplifier chip as possible. Also Rg1 and Rg2 are selected

separately instead of a single component because the center point will be used later
on to provide the right leg drive circuitry. There is no concern with stability with this
stage because there is no external feedback, save for the gain resistor, because the
INA128 is an integrated package. The gain for this stage is defined by Equation 2.

VOUT
50k
1
VIN
Rg1 Rg 2
Equation 2

Gain Stage
The next stage is the real drive for the gain of the amplifier. It can be seen in Figure
7, this is the first stage where there is difference between the EEG and EOG
amplifiers.

Figure 7: Gain stage for amplifier

This architecture is the standard non-inverting amplifier configuration. The transfer

function of this stage can be seen in Equation 3.

VOUT
R8
1
1
VIN
R 7 1 j ( R8)(C 4)
Equation 3

The only concern here is that R7 cannot be zero otherwise the op-amp will saturate.
This stage offers gain but it also includes a pole to help remove higher frequency
signals. This stage alone does not offer enough filtering however it does provide
sufficient gain. The topology is simple to understand an use and offers sufficient
gain. The TLC277 is chosen due to the low level of input offset voltage, which is

required given the low level of the signals that are being amplified. The component
C9 is used to help remove as much noise from the power supply by keeping it as
close to the chip as possible. The TLC277 offers two op-amps in a single package
and so the next stage will use the other op-amp.

Filtering stage
The next stage is the primary filtering stage. The chosen topolgy is the Sallen-Key
architecture, the reasoning for this is that the filter roll-off for the Sallen-Key filter is
the same as that in the specifications (-12 dB/Octave). This architecture can be seen
inFigure 8.

Figure 8: Sallen-Key low-pass architecture with some added gain

The transfer function of this architecture is seen in Equation 4.

VOUT
VIN

R11
R12

RR
1 j ( R10 C 6 R9 C6 9 11 C5 ) ( j ) 2 R9 R10 C5 C6
R12
1

Equation 4

By setting R9=R10=R and C5=C6=C then Equation 4 simplifies to Equation 5.

VOUT
VIN

R11
R12

R
1 jRC (2 11 ) ( jRC ) 2
R12
1

Equation 5

Based on the Routh-Hurwitz Criteria for stability is is easy to see that this amplifier
configuration will become unstable if the ratio R 11/R12 is greater than or equal to 2,
so by selecting R11=R12 then even with consideration to component tolerances it
does not come even close to instability.

80

(1.0000,60.974)
(247.618m,58.187)

(10.000,61.176)

(47.160,58.181)

60
(100.000m,50.228)
(2.9970,61.166)
(100.000,42.064)
(128.472,35.619)

40
(500.590m,60.355)

20

(299.698,13.661)

(1.0000K,-17.019)

-20

-40
1.0mHz
10mHz
dB(V(U2B:OUT)/V(V3:+,V3:-))

100mHz

1.0Hz

10Hz

100Hz

1.0KHz

Frequency

Figure 9: Graph of PSpice capture of frequency sweep for the EEG amplifier
architecture

80

(1.0000,61.191)
(1.0000m,61.191)
(34.173,58.061)

60

(100.000,32.990)

40

(128.472,26.478)

20

(358.430,-64.746m)
0

(1.0000K,-25.547)
-20

-40
1.0mHz
10mHz
dB(V(U2B:OUT)/V(V3:+,V3:-))

100mHz

1.0Hz

10Hz

100Hz

1.0KHz

Frequency

Figure 10: Graph of PSpice capture of frequency sweep for the EOG amplifier
architecture

PSoC Mixed-Signal Array

Finally a mixed-signal array microprocessor was chosen as the final gain control
stage, as well as the sample and hold, analog to digital conversion and is used to
transmit data in UART format. The PSoC contains 12 configureable analog blocks, for
this project we will be utilizing 5 of them, four EEG channels and one EOG channel.
Each channel will then go through a customizeable set of operations such as a gain
stage, a filter stage, sample and hold and finally into an analog to digital converter.

The PSoC also has built in SRAM and built in flash in order to store various states of
operation and the software that will be developed. A transciever chip along with an
isolation chip will be used in colaboration with the PSoC in order to convert the UART
data into RS232 protocol, and the isolation chip will isolate the RS232 data being
sent and the data being received from outside paths. Each Packet of information
sent via RS232 will contain 12 bits of raw bio potential data as well as a 4 bit header
to mark the source of the information, such as EEG channel 1.

Appendix

Figure 11: Oscilloscope Waveform capture of the front end circuitry at 0 Hz (Vin is
98.8 mV)

Figure 12: Oscilloscope Waveform capture of the front end circuitry at 30 Hz

Figure 13: Oscilloscope Waveform capture of front end circuitry at 100 Hz

Figure 14: Oscilloscope Waveform capture of front end circuitry at 500 kHz
20V

10V

0V

-10V

-20V

0s

10ms
20ms
V(U1:-,U1:+)
V(R20:2,R2:1)

30ms

40ms

50ms

60ms

70ms

80ms

90ms

100ms

Time

Figure 15: Graph of PSpice Input and output waveforms with the input of 2 Vp-p
applied at the front end of the amplifier denoted in red and the output taken at
the input to the preamp stage denoted in green

2.0V
(62.517m,2.0000)
(12.581m,1.1429)

1.0V

0V

-1.0V

-2.0V

0s

10ms
20ms
V(U1:-,U1:+)
V(V3:+,R2:1)

30ms

40ms

50ms

60ms

70ms

80ms

90ms

100ms

Time

Figure 16: Graph of PSpice Input and output waveforms with the input of 4 Vp-p
applied at the front end of the amplifier denoted in red and the output taken at
the input to the preamp stage denoted in green

20V

(62.783m,19.963)
10V

(11.797m,1.3040)

0V

-10V

-20V

0s

10ms
20ms
V(U1:-,U1:+)
V(V3:+,R2:1)

30ms

40ms

50ms

60ms

70ms

80ms

90ms

100ms

Time

Figure 17: Graph of PSpice Input and output waveforms with the input of 40 Vp-p
applied at the front end of the amplifier denoted in red and the output taken at
the input to the preamp stage denoted in green
20V

10V

0V

-10V

-20V

0s

10ms
20ms
V(U1:-,U1:+)
V(R20:2,R2:1)

30ms

40ms

50ms

60ms

70ms

80ms

90ms

100ms

Time

Figure 18: Graph of PSpice Input and output waveforms with the input of 4 Vp-p
applied at the input to the preamp denoted in green and the output taken at the
input of the front end denoted in red

20V

10V

0V

-10V

-20V

0s

10ms
20ms
V(U1:-,U1:+)
V(R20:2,R2:1)

30ms

40ms

50ms

60ms

70ms

80ms

90ms

100ms

Time

Figure 19: Graph of PSpice Input and output waveforms with the input of 20 Vp-p
applied at the input to the preamp denoted in green and the output taken at the
input of the front end denoted in red

Figure 20: Oscilloscope captures for input and output of front end circuitry where
Channel 2 is the input applied to the front end of the amplifier and Channel 1 is
the output taken at the input terminals of the preamp (Vin=2Vp-p)

Figure 21: Oscilloscope captures for input and output of front end circuitry where
Channel 2 is the input applied to the front end of the amplifier and Channel 1 is
the output taken at the input terminals of the preamp (Vin=4Vp-p)

Figure 22: Oscilloscope captures for input and output of front end circuitry where
Channel 2 is the input applied to the front end of the amplifier and Channel 1 is
the output taken at the input terminals of the preamp (Vin=20Vp-p)

Figure 23: Oscilloscope captures for input and output of front end circuitry where
Channel 2 is the input applied to the input terminals of the preamp and Channel 1
is the output taken at the input terminals of the front end (Vin=3Vp-p)

Figure 24: Oscilloscope captures for input and output of front end circuitry where
Channel 2 is the input applied to the input terminals of the preamp and Channel 1
is the output taken at the input terminals of the front end (Vin=20Vp-p)

Figure 25: Graph of input and output waveforms for the INA128 preamplifier stage
with differential input Channel 1 is the input and Channel 2 is the output

Figure 26: Graph of input and output waveforms for the INA128 preamplifier stage
with common mode input Channel 1 is the input and Channel 2 is output

Figure 27: Graph of Input and Output waveforms applied in a voltage divider
circuit to measure the impedance of scope probe

Figure 28: Graph of Input and Output waveforms applied in a voltage divider
circuit to measure the input impedance of the INA128 amplifier

Figure 29: Graph of output waveform of entire EOG amplifier at 1 Hz (the gain
here is taken as the nominal value for the remaining frequencies)

Figure 30: Graph of output waveform of entire EOG amplifier at the 3-dB
frequency

Figure 31: Graph of output waveform of entire EOG amplifier at 100 Hz

Figure 32: Graph of output waveform of entire EOG amplifier at 128 Hz

Figure 33: Graph of output waveform of entire EOG amplifier at 300 Hz (60 Hz
noise is very prominent at this level)

Figure 34: Graph of output waveform for entire EEG circuitry at 0.1 Hz

Figure 35: Graph of output waveform for entire EEG circuitry at 0.5 Hz

Figure 36: Graph of output waveform for entire EEG circuitry at 1 Hz

Figure 37: Graph of output waveform for entire EEG circuitry at 3 Hz

Figure 38: Graph of output waveform for entire EEG circuitry at 10 Hz

Figure 39: Graph of output waveform for entire EEG circuitry at 45.5 Hz (the upper
3-dB frequency)

Figure 40: Graph of output waveform for entire EEG circuitry at 100 Hz

Figure 41: Graph of output waveform for entire EEG circuitry at 128 Hz

Figure 42: Graph of output waveform for entire EEG circuitry at 300 Hz