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BLOCK DIAGRAM
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
COUNTER
DATA
REGISTER
OUTPUT
BUFFER
DO
DI
MODE
DECODE
LOGIC
CS
CLK
Vcc
Vss
CLOCK
GENERATOR
DESCRIPTION
The Microchip Technology Inc. 93LC56A/B are 2K-bit,
low-voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC56A) or
x16 bits (93LC56B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC56A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC56AX/BX are only offered in a
150-mil SOIC package.
PACKAGE TYPE
DIP
3
4
CS
7
NC
NC
CLK
1
2
DI
DO
Vss
VCC
NC
NC
Vcc
NC
CS
Vss
CLK
93LC56A/BX
DI
Vcc
93LC56A/B
93LC56A/B
CLK
DO
SOIC
TSSOP
NC
Vss
DO
DI
CS
CLK
DI
DO
1
2
3
4
93LC56A/B
CS
SOIC
8
7
6
5
Vcc
NC
NC
Vss
DS21208C-page 1
93LC56A/B
1.0
1.1
ELECTRICAL
CHARACTERISTICS
TABLE 1-1
Name
Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. Vss ............... -0.6V to Vcc +1.0V
Storage temperature .....................................-65C to +150C
Ambient temp. with power applied ................-65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under Maximum ratings may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2
CS
Chip Select
CLK
DI
DO
VSS
Ground
NC
No Connect
VCC
Power Supply
Commercial (C):
Industrial (I):
Tamb = 0C to +70C
Tamb = -40C to +85C
Symbol
Min.
Max.
Units
VIH1
2.0
Vcc +1
Conditions
VIH2
0.7 Vcc
Vcc +1
VIL1
-0.3
0.8
VIL2
-0.3
0.2 Vcc
VOL1
0.4
VOL2
0.2
VOH1
2.4
VOH2
Vcc-0.2
ILI
-10
10
VIN = VSS
ILO
-10
10
VOUT = VSS
Pin capacitance
(all inputs/outputs)
Operating current
Standby current
CIN, COUT
pF
ICC read
1
500
mA
A
ICC write
1.5
mA
ICCS
A
MHz
MHz
ns
Clock frequency
FCLK
2
1
CS = VSS; DI = VSS
VCC > 4.5V
VCC < 4.5V
TCKH
250
TCKL
250
ns
TCSS
50
ns
Relative to CLK
TCSH
ns
Relative to CLK
TCSL
250
ns
TDIS
100
ns
Relative to CLK
TDIH
100
ns
Relative to CLK
TPD
400
ns
Cl = 100 pF
TCZ
100
ns
Cl = 100 pF (Note 2)
TSV
500
ns
Cl = 100 pF
TWC
ms
ERASE/WRITE mode
ERAL mode
Endurance
TEC
ms
TWL
15
ms
1M
cycles
WRAL mode
25C, VCC = 5.0V, Block Mode (Note 3)
DS21208C-page 2
93LC56A/B
2.0
PIN DESCRIPTION
2.1
After detection of a START condition the specified number of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3
2.2
Data In (DI)
2.4
The Serial Clock is used to synchronize the communication between a master device and the 93LC56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive
edge of CLK).
TABLE 2-1
Instruction SB Opcode
Data In
Data Out
ERASE
11
A7
A6
A5
A4
A3
A2
A1
A0
(RDY/BSY)
12
ERAL
00
(RDY/BSY)
12
EWDS
00
HIGH-Z
12
EWEN
00
HIGH-Z
12
READ
10
A7
A6
A5
A4
A3
A2
A1
A0
D7 - D0
20
WRITE
01
A7
A6
A5
A4
A3
A2
A1
A0
D7 - D0
(RDY/BSY)
20
WRAL
00
D7 - D0
(RDY/BSY)
20
Data In
Data Out
TABLE 2-2
Address
Instruction SB Opcode
Address
ERASE
11
A6
A5
A4
A3
A2
A1
A0
(RDY/BSY)
11
ERAL
00
(RDY/BSY)
11
EWDS
00
HIGH-Z
11
EWEN
00
HIGH-Z
11
READ
10
A6
A5
A4
A3
A2
A1
A0
D15 - D0
27
WRITE
01
A6
A5
A4
A3
A2
A1
A0
D15 - D0
(RDY/BSY)
27
WRAL
00
D15 - D0
(RDY/BSY)
27
DS21208C-page 3
93LC56A/B
3.0
FUNCTIONAL DESCRIPTION
3.1
3.2
3.3
START Condition
Data Protection
FIGURE 3-1:
CS
VIL
TCKH
TCKL
TCSH
VIH
CLK
VIL
TDIS
TDIH
VIH
DI
VIL
TPD
TPD
DO VOH
(READ)
VOL
TCZ
TSV
DO VOH
(PROGRAM)
VOL
Note:
TCZ
STATUS VALID
DS21208C-page 4
93LC56A/B
3.4
ERASE
3.5
The ERASE instruction forces all data bits of the specified address to the logical 1 state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
FIGURE 3-2:
ERASE TIMING
TCSL
CS
CHECK STATUS
CLK
DI
AN
AN-1
AN-2
A0
TCZ
TSV
DO
HIGH-Z
BUSY
READY
HIGH-Z
TWC
FIGURE 3-3:
ERAL TIMING
TCSL
CS
CHECK STATUS
CLK
DI
X
TSV
DO
HIGH-Z
BUSY
TCZ
READY
HIGH-Z
TEC
Guaranteed at Vcc = 4.5V to +6.0V.
DS21208C-page 5
93LC56A/B
3.6
3.7
FIGURE 3-4:
READ
EWDS TIMING
TCSL
CS
CLK
DI
FIGURE 3-5:
EWEN TIMING
TCSL
CS
CLK
DI
FIGURE 3-6:
READ TIMING
CS
CLK
DI
DO
HIGH-Z
DS21208C-page 6
An
A0
Dx
D0
Dx
D0
Dx
D0
93LC56A/B
3.8
WRITE
3.9
FIGURE 3-7:
WRITE TIMING
TCSL
CS
CLK
DI
An
A0
Dx
D0
TSV
HIGH-Z
DO
TCZ
BUSY
READY
HIGH-Z
Twc
FIGURE 3-8:
WRAL TIMING
TCSL
CS
CLK
DI
Dx
D0
TSV
DO
HIGH-Z
BUSY
TCZ
READY
HIGH-Z
TWL
Guaranteed at Vcc = 4.5V to +6.0V.
DS21208C-page 7
93LC56A/B
NOTES:
DS21208C-page 8
93LC56A/B
NOTES:
DS21208C-page 9
93LC56A/B
NOTES:
DS21208C-page 10
93LC56A/B
93LC56A/B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
93LC56A/B
/P
Package:
Temperature
Range:
P
SN
SM
ST
Blank = 0 C to +70C
I = -40C to +85C
93LC56A
93LC56AT
93LC56AX
93LC56AXT
Device:
=
=
=
=
93LC56B
93LC56BT
93LC56BX
93LC56BXT
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21208C-page 11
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ASIA/PACIFIC (continued)
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All rights reserved. 2000 Microchip Technology Incorporated. Printed in the USA. 12/00
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DS21208C-page 12
Preliminary