Digital Electronics

Experiment 8

2014-15 Spring

Latch, Flip-flop and Ripple Counter

In this experiment, the two basic modules required for the design of sequential circuits LATCH for
asynchronous circuits, and FLIP-FLOP for synchronous circuits will be studied first, followed by a study of
simple Ripple Counters using flip-flops. Apart from the CMOS NAND and NOR gates you are already familiar
with, we will be using in this experiment the CD4013 dual D Flip-flop chip and the CD4027 dual JK Flip-flop
chip, both belonging to the CMOS family.
A. NAND and NOR Latches
1. Assemble a NOR latch using two gates in the CD4001 chip, with the two outputs Q and Q connected to two
LEDs through 1k resistors. Observe and tabulate the sequence of Q and Q in response to the following
sequence of the two inputs S and R applied by connecting the two inputs to VDD / Gnd through two wires:
S R = 01, 00, 10, 00, 01, 10, 11, 00, 01, 11, 00, 11, 00.
Interpret the observed result and verify the latch operation. Remember that an input left disconnected does
not have any logic level (0 / 1).
2. Repeat the experiment with a NAND latch assembled using two gates in the 74HC00 chip, applying the
following sequence of inputs through two Input switches:
S R = 10, 11, 01, 11, 10, 01, 00, 11, 10, 00, 11, 00, 11.
B. Manual Pulser using Latch
The Clock input required by all synchronous sequential circuits is a sequence of rectangular pulses, each pulse
consisting of a leading edge and a trailing edge. If one tries to generate such a pulse by a simple toggle switch
(SPDT Single Pole Double Throw) so that the output is connected to the 1 level in one position of the switch
and to the 0 level in the other position, every throw of the switch leads to multiple edges because of the
mechanical vibration of the moving contact. A simple circuit using just a NAND latch, as shown in Fig. 8.1 can
ensure that a clean pulse having a single leading edge and a single trailing edge is generated manually by a
toggle switch in spite of the mechanical vibration.
+5V set up in Part A
1. Add two 10k resistors to the NAND latch
to obtain the circuit given in Fig. 8.1, using10kjust S
a wire
instead of the SPDT switch.
SPDT

switch
2. Test the Manual Pulser by alternately connecting
the S and
R inputs of the latch to Ground, and verifying that the LED
lights up when S is grounded (Q 1 and Q 0), and
R
remains off when R is grounded. Hence note down the
sequence of the wire connection for creating clock pulses
10k
1k
with leading edge 0 1 and trailing edge 1 0.

Fig. 8.1 Manual Pulser

C. D and JK Flip-flops
14

13

12

11

10

VDD Q
Q CK RD
D SD
CD4013
FF2
Dual D FF
FF1
Q
Q CK RD D
SD Gnd

16

15

14

13

12

11

10

Q
Q CK RD
CD4027
FF2
Dual J-K FF
FF1
Q
Q CK RD
K

VDD

SD

SD Gnd

888

Fig

Table 8.1 Truth Tables of Flip-flops

SD

RD

Qnext

Qold

0 D Qold
Qnext
0 0 1 0
1 1 0 1

1
?
(a) SD-RDTruth Table

Qnext

1
Qold
(b) D Truth Table

(c) J-K Truth table

The pin connections of the CD4013 and the CD4027 chips are given above. Note that each FF in the chip has
a direct (asynchronous) Set input SD and a direct (asynchronous) clear input RD, besides the synchronous
inputs D / J-K. This enables one either to Set (Q 1) or cleaR (Q 0) the flip-flop to set up initial conditions
as desired, by making SD-RD = 1 0 or SD-RD = 0 1 respectively. SD-RD are asynchronous inputs as in the case of
a latch, and hence SD-RD = 1 1 is an illegal input combination.
1. The first step is to test each type of FF (one from each given chip) one by one. Connect the Clock Out of
the Manual Pulser to the CK input of the FF to be tested, and the Q and Q outputs to two LEDs through
1k resistors. Leaving the synchronous inputs open, verify the SD-RD Truth Table given in Table 8.1, by
applying the following sequence of values of SD and RD and tabulating the resulting sequence of Q and Q:
SD-RD = 01, 00, 10, 00, 01, 10, 01, 00.
2. Verify that the action of SD and RD is independent of the synchronous and clock inputs by repeating
step C.1 for each type of FF with a few different combinations of D / J-K and CK.
3. With the asynchronous inputs disabled, i.e. with SD = RD = 0, verify the D Truth Table given Table 8.1 for the
D FF, by observing Q and Q before and after applying a manual Clock Out (0-1-0) pulse from the Manual
Pulser for D = 0 and D = 1.
4. In a similar fashion, verify the J-K Truth Table given in Table 8.1 for the JK FF, applying synchronous
inputs J-K in the following sequence:
J-K = 01, 00, 10, 00, 01, 10, 01, 11, 00, 11, 00.
For each clock pulse, verify that Q and Q change at the 0 1 transition of the Clock Out (Positive-logic)
of the Manual Pulser.
D. Binary Ripple Counter
A binary counter is required to count the number of applied pulses in the binary number sequence either in
the increasing order (UP counting) or in the decreasing order (DOWN counting). A ripple counter consists of T
flip-flops with T = 1 connected in cascade: Manual Pulser Clock Out CK0, Q0 CK1, Q1 CK2, Q2 CK3.
As T flip-flops are normally not available commercially, one has to either use JK flip-flops with J = K = 1, or use
D flip-flops with D = Q.
1. Draw the circuit diagram of the binary DOWN counter using two JK flip-flops and two D flip-flops, available
in the given chips, indicating all the pin numbers of the two chips, and assemble the complete circuit on the
breadboard. Connect all the SD inputs together to one Input Switch, all the RD inputs together to another
Input Switch, and the outputs Q0, Q1, Q2, Q3 to four LED Displays.
2. Apply SD-RD = 1 0 to initialise the counter to the starting state 1111for DOWN counting.
3. Now make SD = RD = 0 so that counting is enabled. Apply 16 clock pulses from the Manual Pulser to CK0
and tabulate the state sequence for the entire cycle.
4. Repeat step D.1 with the clock connections changed to obtain a binary UP counter, with other connections
unchanged.
5. Apply SD-RD = 0 1 to initialise the counter to 0000 for UP counting, and repeat step D.3.