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8.0
COMPARATOR MODULE
REGISTER 8-1:
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41250E-page 93
PIC16F917/916/914/913
8.1
FIGURE 8-1:
Comparator Operation
CxOUT
FIGURE 8-2:
VIN-
Output
Output
Output
8.2
VV
ININ+
+
Input Conditions
VIN+
VIN
VIN
TABLE 8-1:
SINGLE COMPARATOR
Rs < 10K
RIC
AIN
VA
CPIN
5 pF
VT = 0.6V
Leakage
500 nA
Vss
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE= Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
DS41250E-page 94
Preliminary
PIC16F917/916/914/913
8.3
Comparator Configuration
Note:
FIGURE 8-3:
VINVIN+
Off (Read as 0)
C2
RA0/AN0/
A
C1-/SEG12
A
RA3/AN3/
C1+/VREF+/SEG15
VIN-
RA1/AN1/
A
C2-/SEG7
A
RA2/AN2/
C2+/VREF-/COM2
VIN-
C1OUT
C1
VIN+
RA1/AN1/
A
C2-/SEG7
A
RA2/AN2/
C2+/VREF-/COM2
RA2/AN2/
C2+/VREF-/
COM2
VIN+
C1OUT
C1
VIN+
C1
Off (Read as 0)
C2
Off (Read as 0)
CIS = 0
CIS = 1
C1OUT
VINC2
VIN+
C2OUT
VINVIN+
C1OUT
C1
RA4
RA1/AN1/
C2-/SEG7
VINVIN+
VIN-
VIN+
C2OUT
C2
C1
CIS = 0
CIS = 1
VIN+
C2
VIN-
A
RA2/AN2/
C2+/VREF-/COM2
VIN+
C2OUT
C2
RA5
Off (Read as 0)
VIN-
A
A
VIN-
RA0/AN0/
C1-/SEG12
VIN-
RA1/AN1/
D
C2-/SEG7
D
RA2/AN2/
C2+/VREF-/COM2
VIN+
RA1/AN1/
C2-/SEG7
VIN-
D
RA0/AN0/
C1-/SEG12
D
RA3/AN3/
C1+/VREF+/SEG15
A
RA1/AN1/
C2-/SEG7
A
RA2/AN2/
C2+/VREF-/COM2
C2OUT
C2
VIN+
Comparators Off
CM<2:0> = 111
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/
SEG15
C2OUT
RA0/AN0/
A
C1-/SEG12
A
RA3/AN3/
C1+/VREF+/SEG15
RA1/AN1/
A
C2-/SEG7
A
RA2/AN2/
C2+/VREF-/COM2
CIS = 0
CIS = 1
VINVIN+
C1
C1OUT
C2
C2OUT
VINVIN+
RA5
D = Digital Input.
Preliminary
DS41250E-page 95
PIC16F917/916/914/913
FIGURE 8-4:
Port Pins
C1INV
To C1OUT pin
To Data Bus
D
EN
RD CMCON
D
RD CMCON
EN
CL
NReset
FIGURE 8-5:
Port Pins
C2INV
C2SYNC
To TMR1
0
To C2OUT pin
1
D
TMR1
Clock Source(1)
EN
To Data Bus
D
EN
RD CMCON
D
RD CMCON
EN
CL
Reset
Note 1:
DS41250E-page 96
Preliminary
PIC16F917/916/914/913
REGISTER 8-2:
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
T1GSS
C2SYNC
bit 7
bit 0
bit 7-2:
Unimplemented: Read as 0
bit 1
bit 0
8.4
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Comparator Outputs
8.5
x = Bit is unknown
Comparator Interrupts
a)
b)
Preliminary
DS41250E-page 97
PIC16F917/916/914/913
8.6
8.6.2
Comparator Reference
8.6.1
VOLTAGE REFERENCE
ACCURACY/ERROR
EQUATION 8-1:
VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR3:VR0 x VDD/32)
FIGURE 8-6:
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR<3:0>
VREN
VR <3:0> = 0000
VRR
DS41250E-page 98
Preliminary
PIC16F917/916/914/913
8.7
8.9
8.8
Effects of a Reset
Preliminary
DS41250E-page 99
PIC16F917/916/914/913
REGISTER 8-3:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
TABLE 8-2:
Address
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
0Dh
PIR2
OSFIF
C2IF
C1IF
LCDIF
LVDIF
CCP2IF
0000 -0-0
0000 -0-0
9Ch
CMCON0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
97h
CMCON1
T1GSS
C2SYNC
---- --10
---- --10
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
8Dh
PIE2
OSFIE
C2IE
C1IE
LCDIE
LVDIE
CCP2IE
0000 -0-0
0000 -0-0
9Dh
VRCON
VREN
VRR
VR3
VR2
VR1
VR0
0-0- 0000
0-0- 0000
Legend:
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by the comparator or Comparator Voltage
Reference module.
DS41250E-page 100
Preliminary