Sie sind auf Seite 1von 36
Lecture 5: DC & Transient Response

Lecture 5:

DC & Transient Response

Outline

Outline  Pass Transistors  DC Response  Logic Levels and Noise Margins  Transient Response

Pass Transistors

DC Response

Logic Levels and Noise Margins

Transient Response

RC Delay Models

Delay Estimation

Response  RC Delay Models  Delay Estimation 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign
Response  RC Delay Models  Delay Estimation 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

2

Pass Transistors

Pass Transistors  We have assumed source is grounded  What if source > 0? –

We have assumed source is grounded

What if source > 0?

– e.g. pass transistor passing V DD

V g = V DD

– If V s > V DD -V t , V gs < V t

– Hence transistor would turn itself off

V DD

V DD

t – Hence transistor would turn itself off V DD V DD  nMOS pass transistors
t – Hence transistor would turn itself off V DD V DD  nMOS pass transistors
t – Hence transistor would turn itself off V DD V DD  nMOS pass transistors
t – Hence transistor would turn itself off V DD V DD  nMOS pass transistors

nMOS pass transistors pull no higher than V DD -V tn

– Called a degraded “1”

– Approach degraded value slowly (low I ds )

pMOS pass transistors pull no lower than V tp

Transmission gates are needed to pass both 0 and 1

t p  Transmission gates are needed to pass both 0 and 1 5: DC and

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

3

Pass Transistor Ckts

Pass Transistor Ckts V DD V DD V SS V s = V D D -V

V DD

V DD V

V SS
V
SS

V s = V DD -V tn

V s = |V tp |

V

V

V DD V DD V DD DD -V tn V DD -V tn V DD
V DD
V DD
V DD
DD
-V tn
V DD -V tn
V DD
DD
V
DD -V tn
V DD
V
-2V tn
DD

V DD -V tn

tn V DD DD V DD -V tn V DD V -2V tn DD V DD

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

4

DC Response

DC Response  DC Response: V o u t vs. V i n for a gate

DC Response: V out vs. V in for a gate

Ex: Inverter

– When V in = 0

– When V in = V DD

– In between, V out depends on transistor size and current

– By KCL, must settle such that

V out = V DD

V out = 0

->

->

such that V out = V DD V o u t = 0 -> -> V

V in

I dsn = |I dsp |

V DD V out I dsp I dsn
V DD
V out
I dsp
I dsn

– We could solve equations

– But graphical solution gives more insight

equations – But graphical solution gives more insight 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

5

Transistor Operation

Transistor Operation  Current depends on region of transistor behavior  For what V i n

Current depends on region of transistor behavior

For what V in and V out are nMOS and pMOS in

– Cutoff?

– Linear?

– Saturation?

are nMOS and pMOS in – Cutoff? – Linear? – Saturation? 5: DC and Transient Response

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

6

nMOS Operation

nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V

Cutoff

Linear

Saturated

V gsn < V tn

V gsn > V tn

V gsn > V tn

V in < V tn

V in > V tn

V in > V tn

V dsn < V gsn V tn

V dsn > V gsn V tn

V out < V in - V tn

V out > V in - V tn

V gsn = V in

V dsn = V out

V in

- V tn V gsn = V in V dsn = V out V in V

V DD

I dsp

I dsp

I dsn

I

dsn

 
= V out V in V DD I dsp I dsn   V out 5: DC

V out

out V in V DD I dsp I dsn   V out 5: DC and Transient

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

7

pMOS Operation

pMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V

Cutoff

Linear

Saturated

V gsp > V tp

V gsp < V tp

V gsp < V tp

V in > V DD + V tp

V in < V DD + V tp

V in < V DD + V tp

V dsp > V gsp V tp

V dsp < V gsp V tp

V out > V in - V tp

V out < V in - V tp

V gsp = V in - V DD

V tp < 0

V dsp = V out - V DD

V in

p < 0 V dsp = V out - V DD V in V DD I

V DD

I dsp

I dsp

I dsn

I

dsn

V out - V DD V in V DD I dsp I dsn V out 5:

V out

- V DD V in V DD I dsp I dsn V out 5: DC and

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

8

I-V Characteristics  Make pMOS is wider than nMOS such that β n = β
I-V Characteristics
 Make pMOS is wider than nMOS such that β n = β p
V
gsn5
I dsn
V
gsn4
V
gsn3
-V dsp
V
-V DD
gsn2
V
gsp1
V
gsn1
V
0
gsp2
V DD
V
gsp3
V dsn
V
gsp4
-I dsp
V
gsp5
5: DC and Transient Response
CMOSCMOS VLSIVLSI DesignDesign
4th Ed.
9
Current vs. V out , V in V V in0 in5 V V in1 in4
Current vs. V out , V in
V
V
in0
in5
V
V
in1
in4
I dsn , |I dsp |
V
V
in2
in3
V
V
in3
in2
V
V
in4
in1
V DD
V out
5: DC and Transient Response
CMOSCMOS VLSIVLSI DesignDesign
4th Ed.
10

Load Line Analysis

Load Line Analysis  For a given V i n : – Plot I d s

For a given V in :

– Plot I dsn , I dsp vs. V out

– V out must be where |currents| are equal in

I dsn , |I dsp |

V in0 V in1 V in2 V in3 V in4 V DD V out
V
in0
V
in1
V
in2
V
in3
V
in4
V DD
V out

V

V

V

V

in5

in4

in3

in1

V DD I dsp I dsn
V DD
I dsp
I dsn
in4 V DD V out V V V V in5 in4 in3 in1 V DD I

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

11

V

in2

V in

V out

Load Line Analysis

Load Line Analysis   V = 0.2V0 = 0 V 0.4V 0.6V 0.8V V in

 

V = 0.2V0 = 0 V 0.4V 0.6V 0.8V V in in DD DD DD
V
= 0.2V0
= 0 V
0.4V
0.6V
0.8V
V in
in
DD
DD
DD
DD
DD
V
V
in0
in0
V
V
, , , , , ,
|I
|I
|I
|I
|I
|I
|
| | | | |
in1
in1
dsn
dsp
dsn
dsn
dsn
dsn
dsn
dsp
dsp
dsp
dsp
dsp
V
V
in2
in2
V
V
in3
in3
V
V
in4
in4
V
V
V
V
V
V
V
DD
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
out
out
out
out
out
out
out
V V in5 in5 V V I I I I I I in4 in4 V
V V
in5
in5
V V
I I I I I I
in4
in4
V V
in3
in3
V V
in2
in2
V
V
V
in0
in1
in1
in4 V V in3 in3 V V in2 in2 V V V in0 in1 in1 5:

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

12

DC Transfer Curve  Transcribe points onto V in vs. V out plot V V
DC Transfer Curve
 Transcribe points onto V in vs. V out plot
V
V
in0
DD
V
V
V in1 V in2
in0
in5
A
B
V
V
V out
in1
in4
C
V
V
in2
in3
V
in3
V
V
V
D
in4
V
in3
in2
in5
E
V
V
0
in4
in1
V DD /2
V tn
V DD +V tp
V
DD
V DD
V out
V in
5: DC and Transient Response
CMOSCMOS VLSIVLSI DesignDesign
4th Ed.
13

Operating Regions

Operating Regions  Revisit transistor operating regions Region nMOS pMOS A Cutoff Linear B

Revisit transistor operating regions

Region

nMOS

pMOS

A

Cutoff

Linear

B

Saturation

Linear

C

Saturation

Saturation

D

Linear

Saturation

E

Linear

Cutoff

V out

V in

V DD

Saturation E Linear Cutoff V out V in V DD V out V DD A B

V out

V DD A B C D E 0 V DD +V tp V DD /2
V
DD
A
B
C
D
E
0
V DD +V tp
V DD /2
V tn
V
DD

V in

A B C D E 0 V DD +V tp V DD /2 V tn V

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

14

Beta Ratio

Beta Ratio  If β p / β n ≠ 1, switching point will move from

If β p / β n 1, switching point will move from V DD /2

Called skewed gate

Other gates: collapse into equivalent inverter

V out

V DD β p = 10 β n 2 1 0.5 β p = 0.1
V
DD
β
p
= 10
β
n
2
1
0.5
β
p
= 0.1
β
n
0
V DD
V in
= 10 β n 2 1 0.5 β p = 0.1 β n 0 V DD

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

15

Noise Margins

Noise Margins  How much noise can a gate input see before it does not recognize

How much noise can a gate input see before it does not recognize the input?

can a gate input see before it does not recognize the input? Output Characteristics V DD
can a gate input see before it does not recognize the input? Output Characteristics V DD

Output Characteristics

V DD

Input Characteristics

Logical High Output Range

Logical High Output Range

Logical Low Output Range

Logical Low Output Range
V OH NM H V IH V IL
V OH
NM H
V
IH
V
IL

NM L L

V OL

Indeterminate Region

Indeterminate

Region

Indeterminate Region
NM H V IH V IL NM L V OL Indeterminate Region Logical High Input Range

Logical High

Input Range

L V OL Indeterminate Region Logical High Input Range Logical Low Input Range GND 5: DC

Logical Low

Input Range

GND

Region Logical High Input Range Logical Low Input Range GND 5: DC and Transient Response CMOSCMOS

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

16

Logic Levels

Logic Levels  To maximize noise margins, select logic levels at – unity gain point of

To maximize noise margins, select logic levels at

– unity gain point of DC transfer characteristic

V V out out V V DD DD Unity Gain Points Slope = -1 V
V V
out out
V V
DD DD
Unity Gain Points
Slope = -1
V OH
β
β
p /β /β n n > > 1 1
p
V
V
V
V
in in
out out
V OL
V
V
0
0
in in
-
V V
V DD
V tn
V IL
V IH
DD
DD
|
|V tp
0 in in - V V V DD V tn V IL V IH DD DD

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

17

Transient Response

Transient Response  DC analysis tells us V o u t if V i n is

DC analysis tells us V out if V in is constant

Transient analysis tells us V out (t) if V in (t) changes

– Requires solving differential equations

Input is usually considered to be a step or ramp

– From 0 to V DD or vice versa

to be a step or ramp – From 0 to V D D or vice versa

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

18

Inverter Step Response  Ex: find step response of inverter driving load cap ( )
Inverter Step Response
 Ex: find step response of inverter driving load cap
( ) =
t
ut
(
t
) V
V i n
0
DD
V
in (t)
( t
< t
) = V
V out (t)
V ou t
0
DD
C
load
d V
( t )
I
( t )
o ut
d sn
=−
I
dsn (t)
dt
C
loa d
V
in (t)
0
t
≤ t
0
V
out (t)
t
(
t )
β
V
V
V out
V
( t )
V
<
V
V
t 0
DD
t
2
out
out
D D
t
 
 
5: DC and Transient Response
CMOSCMOS VLSIVLSI DesignDesign
4th Ed.
19

I

ds n

( ) =

t

β

2

(

V

DD

V

)

2 V

out

>

V

DD

V

t

Delay Definitions

Delay Definitions  t p d r : rising propagation delay – From input to rising

t pdr : rising propagation delay

– From input to rising output crossing V DD /2

t pdf : falling propagation delay

– From input to falling output crossing V DD /2

t pd : average propagation delay

– t pd = (t pdr + t pdf )/2

t r : rise time

– From output crossing 0.2 V DD to 0.8 V DD

t f : fall time

– From output crossing 0.8 V DD to 0.2 V DD

time – From output crossing 0.8 V D D to 0.2 V D D 5: DC
time – From output crossing 0.8 V D D to 0.2 V D D 5: DC

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

20

Delay Definitions

Delay Definitions  t c d r : rising contamination delay – From input to rising

t cdr : rising contamination delay

– From input to rising output crossing V DD /2

t cdf : falling contamination delay

– From input to falling output crossing V DD /2

t cd : average contamination delay

– t pd = (t cdr + t cdf )/2

delay – t p d = (t c d r + t c d f )/2

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

21

Simulated Inverter Delay

Simulated Inverter Delay  Solving differential equations by hand is too hard  SPICE simulator solves

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically – Uses more accurate I-V models too!

But simulations take time to write, may hide insight

(V)

2.0 1.5 1.0 t pdf = 66ps t pdr = 83ps V in V out
2.0
1.5
1.0
t pdf = 66ps
t pdr = 83ps
V in
V out
0.5
0.0
0.0
200p
400p
600p
800p
1n

t(s)

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

22

Delay Estimation

Delay Estimation  We would like to be able to easily estimate delay – Not as

We would like to be able to easily estimate delay

– Not as accurate as simulation

– But easier to ask “What if?”

The step response usually looks like a 1 st order RC response with a decaying exponential.

Use RC delay models to estimate delay

– C = total capacitance on output node

– Use effective resistance R

– So that t pd = RC

Characterize transistors by finding their effective R

– Depends on average current as gate switches

effective R – Depends on average current as gate switches 5: DC and Transient Response CMOSCMOS

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

23

Effective Resistance

Effective Resistance  Shockley models have limited value – Not accurate enough for modern transistors –

Shockley models have limited value

– Not accurate enough for modern transistors

– Too complicated for much hand analysis

Simplification: treat transistor as resistor

– Replace I ds (V ds , V gs ) with effective resistance R • I ds = V ds /R

– R averaged across switching of digital gate

Too inaccurate to predict current at any given time

– But good enough to predict RC delay

at any given time – But good enough to predict RC delay 5: DC and Transient

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

24

RC Delay Model

RC Delay Model  Use equivalent circuits for MOS transistors – Ideal switch + capacitance and

Use equivalent circuits for MOS transistors

– Ideal switch + capacitance and ON resistance

– Unit nMOS has resistance R, capacitance C

– Unit pMOS has resistance 2R, capacitance C

Capacitance proportional to width

Resistance inversely proportional to width

g

d k
d
k

s

g

d R/k kC s
d
R/k
kC
s

kC

kC

g

d k
d
k

s

g

s kC 2R/k kC kC
s
kC
2R/k
kC
kC

d

k s g d R/k kC s kC kC g d k s g s kC

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

25

RC Values

RC Values  Capacitance – C = C g = C s = C d =

Capacitance

– C = C g = C s = C d = 2 fF/µm of gate width in 0.6 µm

– Gradually decline to 1 fF/µm in nanometer techs.

Resistance

– R 6 K*µm in 0.6 µm process

– Improves with shorter channel lengths

Unit transistors

– May refer to minimum contacted device (4/2 λ)

– Or maybe 1 µm wide device

– Doesn’t matter as long as you are consistent

device – Doesn’t matter as long as you are consistent 5: DC and Transient Response CMOSCMOS

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

26

Inverter Delay Estimate

Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter A 2 Y 2 1

Estimate the delay of a fanout-of-1 inverter

A

2 Y 2 1 1
2
Y 2
1
1

d = 6RC

2C R 2C 2C Y C C R C
2C
R
2C
2C
Y
C
C
R
C
inverter A 2 Y 2 1 1 d = 6RC 2C R 2C 2C Y C

R

 
    2C
 
    2C

2C

2C

 
     
     
C

C

 
  C

C

2C 2C         C   C 5: DC and Transient Response CMOSCMOS VLSIVLSI

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

27

Delay Model Comparison

Delay Model Comparison 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign 4th Ed. 28
Delay Model Comparison 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign 4th Ed. 28
Delay Model Comparison 5: DC and Transient Response CMOSCMOS VLSIVLSI DesignDesign 4th Ed. 28

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

28

Example: 3-input NAND

Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

2 2 2 3 3 3
2
2
2
3
3
3
resistances equal to a unit inverter (R). 2 2 2 3 3 3 5: DC and

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

29

3-input NAND Caps

3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2C

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2C 2C 2C 2C 2C 2C 2 2 2 2 2 2 2 2 2
2C
2C
2C
2C
2C
2C
2
2
2
2
2
2
2
2
2
2C
2C
2C
9C
3C
3
3
3
5C
3C
3C
3C
3
3
3
5C
3C
3C
3C
3
3
3
5C
3C
3C
5C 3C 3C 3C 3 3 3 5C 3C 3C 3C 3 3 3 5C 3C
5C 3C 3C 3C 3 3 3 5C 3C 3C 3C 3 3 3 5C 3C

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

30

Elmore Delay  ON transistors look like resistors  Pullup or pulldown network modeled as
Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t
≈ ∑
RC
pd
i
− to −
source
i
nodes i
=
RC
+
(
R
+
R
)
C
++ + ++
(
R
R
R
)
C
11
1
2
2
1
2
N
N
R 1
R 2
R 3
R N
C
C 1
C 2
C N
3
5: DC and Transient Response
CMOSCMOS VLSIVLSI DesignDesign
4th Ed.
31

Example: 3-input NAND

Example: 3-input NAND  Estimate worst-case rising and falling delay of 3-input NAND driving h identical

Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.

2 2 2 Y 9C 3 n 2 3C 3 n 1 3C 3 t
2
2
2
Y
9C
3
n
2
3C
3
n
1
3C
3
t
=
( )()
3
C
R
+
(
3
C
)(
RR
+
)
+  95 +
(
h
)
pdf
C  
3
33
=
(
11
+
5 h RC
)

5hC

( h ) pdf C   3 33 = ( 11 + 5 h RC
( h ) pdf C   3 33 = ( 11 + 5 h RC

h copies

t
t

pdr

(

RRR

++

333

)

(9

+

5

)

h RC

=

5hC h copies t pdr ( RRR ++ 333 ) ( 9 + 5 ) h

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

32

Delay Components

Delay Components  Delay has two parts – Parasitic delay • 9 or 11 RC •

Delay has two parts

Parasitic delay

• 9 or 11 RC

• Independent of load

Effort delay

• 5h RC

• Proportional to load capacitance

Effort delay • 5h RC • Proportional to load capacitance 5: DC and Transient Response CMOSCMOS

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

33

Contamination Delay

Contamination Delay  Best-case (contamination) delay can be substantially less than propagation delay.  Ex: If

Best-case (contamination) delay can be substantially less than propagation delay.

Ex: If all three inputs fall simultaneously

2 2 2 Y 9C 5hC 3 n 2 3C 3 n 1 3C 3
2
2
2
Y
9C
5hC
3
n
2
3C
3
n
1
3C
3
t = + ( 95 h ) cdr 
t
= +
(
95
h
)
cdr



 3

R

5

3

95 h ) cdr     3 R 5 3   5: DC

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

34

C



=+

3

C  =+ 3 h  RC

h

RC

Diffusion Capacitance

Diffusion Capacitance  We assumed contacted diffusion on every s / d.  Good layout minimizes

We assumed contacted diffusion on every s / d.

Good layout minimizes diffusion area

Ex: NAND3 layout shares one diffusion contact

– Reduces output capacitance by 2C

– Merged uncontacted diffusion might help too

2C 2C 3C 3C 3C
2C
2C
3C 3C
3C

Shared

Contacted

Diffusion

Isolated

Contacted

Diffusion

2 2 2 7C 3 3C 3 3C 3
2
2
2
7C
3
3C
3
3C
3

Merged

Uncontacted

Diffusion

2 2 2 7C 3 3C 3 3C 3 Merged Uncontacted Diffusion 5: DC and Transient

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

35

Layout Comparison

Layout Comparison  Which layout is better? V DD GND A B Y V DD GND

Which layout is better?

V DD

GND

Layout Comparison  Which layout is better? V DD GND A B Y V DD GND
Layout Comparison  Which layout is better? V DD GND A B Y V DD GND

A B

Comparison  Which layout is better? V DD GND A B Y V DD GND A
Comparison  Which layout is better? V DD GND A B Y V DD GND A

Y

Comparison  Which layout is better? V DD GND A B Y V DD GND A

V DD

GND

 Which layout is better? V DD GND A B Y V DD GND A B

A

B

Which layout is better? V DD GND A B Y V DD GND A B Y
Which layout is better? V DD GND A B Y V DD GND A B Y

Y

Which layout is better? V DD GND A B Y V DD GND A B Y
Which layout is better? V DD GND A B Y V DD GND A B Y
Which layout is better? V DD GND A B Y V DD GND A B Y

5: DC and Transient Response

CMOSCMOS VLSIVLSI DesignDesign

4th Ed.

36