Asdlea

SERDES Transmitter/Receiver (ALTLVDS)
Megafunction User Guide
101 Innovation Drive

San Jose, CA 95134
www.altera.com
UG-MF9504-4.0
Software Version:
Document Version:
Document Date:
8.1
4.0
November 2008
Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
UG-MF9504-4.0
Contents
Chapter 1. About This Megafunction

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft CDR Recovered Clock Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resource Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-1
1-1
1-2
1-3
1-3
1-3
1-4
1-4
Chapter 2. Getting Started

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
MegaWizard Plug-In Manager Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
MegaWizard Plug-In Manager Page Options and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
MegaWizard Plug-In Manager Pages for the LVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
LVDS Transmitter Using a Dedicated SERDES Block or SERDES in LEs . . . . . . . . . . . . . . . . . . . . 2-2
LVDS Transmitter Using an External PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
MegaWizard Plug-In Manager Pages for the LVDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
LVDS Receiver Using a Dedicated SERDES Block or SERDES in LEs . . . . . . . . . . . . . . . . . . . . . . . 2-9
LVDS Receiver Using an External PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Common Pages for ALTLVDS Receiver and Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Instantiating Megafunctions in HDL Code or Schematic Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Generating a Netlist for EDA Tool Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Using the Port and Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Identifying a Megafunction After Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies . . . . . . . . . . . . . . . . . . 2-22
Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Generate an ALTLVDS Receiver and ALTLVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera
Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Design Example 2: Cyclone II ALTLVDS Using External PLL Option . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Integrating the ALTLVDS Receiver and Transmitter in the Design . . . . . . . . . . . . . . . . . . . . . . . 2-32
Parameters Used by ALTPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the Quartus II Software
2-35
Timing ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the Quartus II Software . .
2-36
Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
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SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide
iv
Contents
Design Example 3: Stratix III Soft Clock Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
Chapter 3. Specifications
Ports and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-1
Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
November 2008 Altera Corporation
1. About This Megafunction
Introduction
As design complexities increase, use of vendor-specific Intellectual Property (IP)
blocks have become a common design methodology. Altera provides parameterizable
megafunctions that are optimized for Altera device architectures. Using
megafunctions instead of coding your own logic saves valuable design time.
Additionally, the Altera-provided functions may offer more efficient logic synthesis
and device implementation. You can scale the megafunctions size by setting
parameters.
Device Family Support

The SERDES transmitter/receiver (ALTLVDS) megafunction support the following
target Altera device families:
Arria GX
Stratix IV
Stratix III
Stratix II
Stratix II GX
Stratix GX
Stratix
Cyclone III
Cyclone II
Cyclone
HardCopy II
HardCopy Stratix
APEX II
APEX 20KC
APEX 20KE
Features
The ALTLVDS megafunction implement either an LVDS deserializer receiver or an
LVDS serializer transmitter and offer many additional features:
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Parameterizable data channel widths.
Parameterizable serializer/deserializer (SERDES) factors.
Registered inputs and outputs.
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Chapter 1: About This Megafunction

General Description
Dynamic Phase Alignment (DPA) mode support in Stratix IV, Stratix III, Stratix II
GX, Stratix II and Stratix GX receivers.
Ability to share fast phase-locked loops (PLLs) between transmitter and receivers.
PLL control signals.
Flexibility to implement in dedicated circuitry or in logic cells. This varies

according to the device.
Support for separate PLL in Stratix IV, Stratix III, Stratix II, Stratix II GX,
Cyclone III, Cyclone II, Cyclone, and HardCopy II devices.
Soft Clock-Data Recovery (CDR) mode support for Stratix IV and Stratix III
devices.
General Description
The ALTLVDS megafunction is provided in the Quartus II software, through the
MegaWizard Plug-In Manager. The ALTLVDS megafunction instantiates LVDS
transmitters (ALTLVDS_TX) and LVDS receivers (ALTLVDS_RX). The ALTLVDS_TX
megafunction implements a serialization transmitter, and the ALTLVDS_RX
megafunction implements a deserialization receiver. These megafunctions can be
used to take advantage of the dedicated SERDES circuitry for high-speed differential
data transfer applications in Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX,
Stratix, HardCopy II, and HardCopy Stratix devices. The ALTLVDS megafunction can
also be used to implement SERDES circuitry using logic elements (LEs) and PLLs in
Cyclone III, Cyclone II and Cyclone devices. By using the LVDS megafunctions, you
can customize and control the LVDS data received or transmitted to many source
synchronous channels. The ALTLVDS megafunction has features that are unique to
each supported device family.
To achieve high data transfer rates, the Stratix IV, Stratix III, Stratix II, Stratix II GX,
Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices support True-LVDS
differential I/O interfaces that have dedicated SERDES circuitry for each differential
I/O pair.
f
For transmitting and receiving data rates for respective devices, refer to the specific
device data sheets.
On the receiver side, the high-frequency clock generated by the PLL shifts the serial
data through a shift register (also called the deserializer). The parallel data is clocked
out to the logic array that is synchronized with the low frequency clock.
On the transmitter side, the parallel data from the logic array is first clocked into a
parallel-in, serial-out shift register that is synchronized with the low-frequency clock,
and then transmitted out by the output buffers.
The dedicated phase alignment (DPA) circuitry supports multiple SERDES factors.
Each channel has its own DPA circuit that provides independent data alignment for
each channel; therefore, DPA can reduce channel-to-channel skew as well as
clock-to-channel skew.
Cyclone series (Cyclone III, Cyclone II, and Cyclone) devices do not support the
dedicated DPA circuitry.
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General Description
13
Cyclone series (Cyclone III, Cyclone II, and Cyclone) devices also allow the SERDES
implementation at certain data rates for a specific device. For the LVDS transmitter
and receiver, the ALTLVDS megafunction implements serialization and
deserialization using LEs and PLLs.
f
For supported data rates, refer to the specific device data sheets.
Soft CDR Mode

The Stratix IV and Stratix III series of devices support a new soft CDR mode. This
mode supports the Serial Gigabit Media Independent Interface (SGMII) protocol.
Clock-data recovery removes the clock from the clock-embedded data, a capability
required for SGMII support.
The Stratix IV and Stratix III LVDS block requires the new mode to support clock
forwarding to the core, described in the Clock Forwarding section. In Stratix IV
and Stratix III devices, each LVDS channel can be in soft CDR mode and can drive
the core. However, Stratix IV and Stratix III devices do not contain dedicated
hardware for the CDR support. Instead, the CDR circuitry is implemented as part
of the ALTLVDS megafunction instantiation.
Clock Forwarding
The Stratix IV and Stratix III LVDS block supports clock forwarding to the core. In soft
CDR mode, the DPA clock is forwarded to the core after being divided by the
deserialization factor. The divclkout output signal from the LVDS block holds the
forwarded clock signal. The signal is routed to the new periphery clock (PCLK)
network.
The DPA block determines the optimal DPA clock, which is forwarded to the core. In
normal DPA operation, the DPA block selects an optimal phase to sample the data.
The captured data is passed to the bitslip block, then to the deserializer. The
deserializer divides the DPA clock and the data by the deserialization factor. The
newly divided clock signal is placed on the PCLK network, which carries the clock
signal to the core. In Stratix IV and Stratix III devices, each LVDS channel can be in
soft CDR mode and can drive the core using the PCLK network.
f
The PCLK network originates in the DPA block of a Stratix IV or a Stratix III device.
For more information about PCLKs, refer to the Clock Networks and PLLs in Stratix IV
Devices chapter in volume 1 of the Stratix IV Device Handbook and the Clock Networks
and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
Soft CDR Recovered Clock Simulation

The Quartus II software supports simulation of the forwarded clock, also called the
recovered clock, based on the user-specified ppm value. The ppm value specifies the
number of clock cycles drift between the transmitter and receiver after a million clock
cycles. The drift is positive if the transmitter is faster than the receiver, and negative if
the receiver is faster than the transmitter.
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Resource Utilization and Performance
You can specify the ppm value using two new simulation-only parameters for the
ALTLVDS megafunction. The value of NET_PPM_VARIATION is the absolute value of
the drift, and the IS_NEGATIVE_PPM_DRIFT parameter specifies whether the drift is
positive or negative. The Quartus II simulator simulates the ppm variation by shifting
the recovered data and clock based on the user-specified ppm value.
Common Applications
The SERDES interface is used to transmit and receive high-speed differential data.
This enables moving data from board-to-board or box-to-box with great efficiency.
This high performance consumes minimum power, is relatively immune to noise, and
is cost effective. Typical applications of LVDS technology are common in PC
computing (such as flat panel displays and monitor links), telecommunication and
data-communication systems (such as routers, hubs, and switches) and other common
consumer and commercial applications (such as set-top boxes and in-flight
entertainment).
The Stratix IV and Stratix III LVDS block supports a new soft CDR mode. This mode
supports the widely-used SGMII protocol. A clock-data recovery removes the clock
from the clock-embedded data, a capability required for the SGMII support. This new
mode is called soft CDR mode because the CDR circuitry is implemented in the LEs.
f
For additional information about common applications supported, and for full details
on the I/O standards and high-speed protocols supported, refer to the applicable data
sheet or device handbook for each device family.

Every instantiation of ALTLVDS megafunction uses one fast PLL. The Quartus II
software properly configures the PLL according to the settings you apply in the
ALTLVDS MegaWizard Plug-In Manager. Stratix IV, Stratix III, Stratix II, Stratix II GX,
Cyclone III, Cyclone II, Cyclone, HardCopy II, and HardCopy Stratix devices provide
the option to use an external PLL, which requires you to enter the appropriate PLL
parameters.
f
For more information about the PLL parameters, refer to the ALTPLL Megafunction
User Guide.
All Stratix families support the Use Shared PLL(s) for Receiver and Transmitter
option to place both the LVDS transmitter and the LVDS receiver in the same device
I/O bank. The Quartus II software lets the transmitter and the receiver share the same
fast PLL when both use the same input clock frequency. Although you must separate
the transmitter and receiver modules in your design, the Quartus II software merges
the fast PLLs, when appropriate, and gives you the following message:
Info: Receiver fast PLL <lvds_rx PLL name> and transmitter fast PLL
<lvds_tx PLL name> are merged together
The Quartus II software displays the following message when it cannot merge the fast
PLLs for the LVDS transmitter and receiver pair in the design:
Warning: Can't merge transmitter-only fast PLL <lvds_tx PLL name>
and receiver-only fast PLL <lvds_rx PLL name>
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For Stratix device families, the side I/O banks contain dedicated SERDES circuitry,
which includes the fast PLLs, serial shift registers, and parallel registers. The transmit
and receive functions use varying numbers of LEs depending on the number of
channels, serialization and deserialization factors. For best performance, these LEs
must be placed in columns as close to the SERDES circuitry and LVDS pins as
possible. This is done by the Quartus II software automatically during
place-and-route.
Cyclone III, Cyclone II, and Cyclone devices use DDIO registers as part of the
SERDES interface. Since data is clocked on both the rising and falling edge, the clock
frequency must be half the data rate; therefore, the PLL runs at half the frequency of
the data rate. The core clock frequency for the transmitter is data rate divided by the
serialization factor (J). For the odd serialization factors, depending on the output
clock-divide factor (B) and device family, an optional core clock frequency of data rate
divided by two times the serialization factor (J) is also available.
Use Table 11 and Table 12 to determine the clock and data rate relationships.
Table 11. Cyclone III, Cyclone II, and Cyclone ALTLVDS Receiver Clock Relationships
Clock Type
J = Even
J = Odd
Fast Clock
Data Rate / 2
Data Rate / 2
Slow Clock (outclock)
Data Rate / J
Data Rate / J
Table 12. Cyclone III, Cyclone II, and Cyclone ALTLVDS Transmitter Clock Relationships
Clock Type
J = Even
J = Odd
Fast Clock
Data Rate / 2
Data Rate / 2
Slow Clock (outclock)
Data Rate / 2 * B
Data Rate / 2 * B
Core Clock
Data Rate / J
Data Rate / J
The Quartus II software reports the number of LEs used per ALTLVDS function in the
Fitter Resource Utilization by Entity section within the Resource section of the
Compilation Report file.
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2. Getting Started
Introduction
The most efficient way to customize your ALTLVDS megafunction is the
MegaWizard Plug-In Manager . Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix,
Stratix GX, HardCopy II, and HardCopy Stratix devices each have different features
available when using the dedicated serializer/deserializer (SERDES) circuitry.
Cyclone III, Cyclone II, and Cyclone devices do not have dedicated SERDES
circuitry; therefore, the functions are implemented in registers using logic elements
(LEs). The wizard displays only the features that are appropriate to the selected
device family. Within each selected device, certain features are available, depending
on the modes that you specify.
Software and System Requirements

The instructions in this section require the Quartus II software version 8.1. For
operating system support information, refer to the Operating System Support page in
Altera website (www.altera.com).
MegaWizard Plug-In Manager Customization

Use the MegaWizard Plug-In Manager to create or modify design files that contain
custom ALTLVDS variations that can be instantiated in a design file. The MegaWizard
Plug-In Manager provides a wizard that allows you to specify options for the custom
ALTLVDS megafunction features in your design.
Start the MegaWizard Plug-In Manager in one of the following ways:
November 2008
On the Tools menu, click MegaWizard Plug-In Manager.
When working in the Block Editor, from the Edit menu, click Insert Symbol as
Block, or right-click in the Block Editor, point to Insert, and click Symbol as
Block. In the Symbol window, click MegaWizard Plug-In Manager.
Start the stand-alone version of the MegaWizard Plug-In Manager by typing the
following command at the command prompt:
qmegawiz r
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Chapter 2: Getting Started

MegaWizard Plug-In Manager Page Options and Descriptions

This section provides descriptions of the options available on page 1 and page 2a of
the ALTLVDS MegaWizard Plug-In Manager.
The first two pages of the megafunction are the same for all supported devices. On
page 1 of the MegaWizard Plug-In Manager, you can select Create a new custom
megafunction variation, Edit an existing custom megafunction variation, or Copy
an existing custom megafunction variation.
On page 2a of the MegaWizard Plug-In Manager, you can specify the megafunction,
the family of device to use, the type of output file to create, and the name of the ouput
file. The ALTLVDS megafunction appears in the I/O category. you can choose AHDL
(.tdf), HVDL (.vhd), or Verilog HDL (.v) as the output file type.
The selections you make on page 3 dictate the format of the remaining pages. The
device family that you select determines the ports and parameters that are available
on page 3 and the following pages. For every device family, the pages for the LVDS
transmitter are different than the pages for the LVDS receiver. For the receiver or the
transmitter, if the device allows you to choose whether to implement the
serializer/deserializer (SERDES) circuitry in logic cells or in a dedicated SERDES
block, your choice affects the other parametrization choices available to you.
Similarly, you can choose whether to use an external PLL. For the receiver, if you
choose to enable the DPA mode, your choice affects the other parametrization choices
available to you.
On page 3, you specify whether this megafunction is an LVDS transmitter or receiver,
the number of channels, and the deserialization factor. The number of channels you
select changes the width of the rx_in port, and the deserialization factor changes the
width of the rx_out port. If the required number of channels is not available in the
list, type the desired number in the What is the number of channels? box. The list for
the deserialization factor is device-dependent.
Your choice of device and transmitter or receiver determines whether the remaining
options on this page are available to you or are disabled.
The left pane of the MegaWizard Plug-In Manager displays a schematic
representation of the custom megafunction variation that you are creating. The
schematic updates automatically as the ports and parameters change.
1
For online help, click the Documentation button to view the Quartus II Help file for
the LVDS transmit or receive megafunction.
MegaWizard Plug-In Manager Pages for the LVDS Transmitter

On page 3, after you select the LVDS transmitter, depending on the device you
selected, you can choose to implement the SERDES circuitry in logic cells or in a
dedicated SERDES block. Similarly, depending on the device, you can choose to use
an external PLL.
LVDS Transmitter Using a Dedicated SERDES Block or SERDES in LEs

This section discusses the options available for configuring the LVDS transmitter
megafunction if an internal PLL is used.
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On page 3, several options can be customized for the transmitter settings. The options
are described in Table 21.
Table 21. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 3)
Option
Description
Comments
Implement Serializer/Deserializer
circuitry in logic cells
If not enabled, the megafunction takes

advantage of dedicated SERDES circuitry
in the device. If enabled, SERDES
circuitry is implemented in logic cells.
This feature is supported by Arria GX,
Stratix IV, Stratix III, Stratix II,
Stratix II GX, Stratix GX, Stratix,
HardCopy II, and HardCopy Stratix
devices. In the Cyclone series of devices,
SERDES circuitry is always implemented
in logic cells.
If enabled, the transmitter starts its

operation on the first fast clock edge after
the PLL is locked. This option is intended
for slow speeds and byte alignment may be
different from the hard SERDES
implementation.
What is the number of channels?
Number of output channels available for

the LVDS transmitter. The allowed values
depend on the pins available in the
device. For the allowed values for your
device, refer to the relevant device
handbook.
For example, if the number of channels is

44, a tx_out[43..0] port is created.
What is the deserialization factor? This value determines the number of

parallel bits from the core that the
transmitter serializes and sends out. For
the valid deserialization factors for your
handbook.
Altera recommends you to use the

ALTIOBUF megafunction to connect the
channels to actual FPGA pins via the I/O
buffer. By using ALTIOBUF
megafunction, you can control whether
the buffer should be differential.
For further details, refer to the I/O Buffer

(ALTIOBUF) Megafunction User Guide.
For example, if the deserialization factor is

10 and the number of output channels is 1,
the transmitter serializes every 10 parallel
bits into the single output channel. If the
deserialization factor is 10 and the number
of channels is 44, a tx_in[439..0] port
is created.
The wizard has disabled the 50/50 duty
cycle for 7, 5 and 9 mode when
divide_by_factor shown in the
wizard GUI is same as the deserialization
factor.
Megafunction issues a warning and
implements the 4:3 duty cycle.
Use External PLL
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Altera Corporation
This determines whether to use an

external PLL to clock the SERDES
transmitter. If this option is not enabled,
the megafunction automatically
implements an internal PLL to clock the
LVDS transmitter block. If this option is
enabled, a separate PLL must be used to
provide the clocking source. It is your
responsibility to make the necessary
connections.
If not enabled, the next page displays the

PLL settings. The PLL settings page is
skipped if this option is enabled.
Take note when you have a deserialization
factor of two, the SERDES is bypassed and
its functionality is implemented in DDR
registers. You need at least a deserialization
factor of four to use the external PLL
option.
24

Page 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This
page appears only if an internal PLL is used.
Table 22 describes the options you have on page 4 to customize the frequency and
PLL settings.
Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4)
Option
What is the output data rate?
Specify the input clock rate by
(Part 1 of 2)
Description
Comments
The value specifies the data rate

for the output channel of the
transmitter, in Mbps. For data rate
ranges, refer to the specific DC &
Switching Characteristics chapter
in the appropriate device
handbook.
This value determines the allowed input clock rate

values.
The value specifies the
tx_inclock frequency to the
internal PLL. The allowed values

depend on the output data rate
selected.
What is the phase alignment of
tx_in with respect to the rising
edge of 'tx_inclock'? (in degrees)
This value determines the phase

alignment of the data transmitted
by the transmitter core with
respect to tx_inclock.
Available values are 0
(edge-aligned), 45, 90, 135, 180
(center-aligned), 225, 270, 315.
Use tx_pll_enable input port
This port gives you control over

the enable port of the fast PLL
that is used with this function.
If the transmitter shares the PLL with the receiver,

and the tx_pll_enable port is used, this port
must be used in both megafunction instantiations
and the two signals must be tied together in the
design file. If the PLL-enable port is used in one
megafunction instance and not the other, the PLLs
are not shared, and a warning appears during
compilation.
Use pll_areset input port
This option gives you control over

the asynchronous reset port of
the fast PLL that is used with this
function.
When the transmitter shares the PLL with the

receiver and the pll_areset port is used, this
port must be used in both megafunction
instantiations and the two signals must be tied
together in the design file. If the PLL-enable port is
used in one megafunction instance and not the
other, the PLLs are not shared, and a warning
appears during compilation.
The PLL must be reset in order for the output clock
phase relationships to be set correctly when the
PLL loses lock or if the PLL input reference clock is
not stable when the device completes the
configuration process
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Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4)
Option
Description
(Part 2 of 2)
Comments
Align clock to the center of the

data window
When enabled, a phase shift of

90 is added to the clock to center
the clock in the data. Use this
parameter for PLL merging if the
receiver has the option enabled.
This option is available only for Arria GX,

Stratix II GX, Stratix II, and HardCopy II devices
when SERDES is implemented in logic cells, and
for Cyclone II devices. For Cyclone III, Stratix IV,
and Stratix III (LE Implementation) devices, the
option is always enabled.
Enable self-reset on lost lock in

PLL
If enabled, the PLL resets

automatically whenever it loses
lock.
This option is available only for Stratix IV,

Stratix III, and Cyclone III devices when SERDES is
implemented in logic cells.
Use shared PLL(s) for receivers

and transmitters
When this option is enabled, your

LVDS receivers and transmitters
can share the same PLL.
This option can be used if the LVDS receivers and

transmitters use the same input clock frequency,
deserialization factor, and data rates.
Register tx_in input port using
If enabled, specify whether input

registers are clocked by
tx_inclock or by
tx_coreclock. When PLLs are
shared, the tx_inclock port
should be connected to the same
reference clock as the receiver
function. For example, if
tx_inclock is connected to a
500 MHz input reference clock,
and the parallel data rate is not
500 MHz, then the parallel data
should be registered using
tx_coreclock, that runs at the
output serial data rate divided by
the deserialization factor. This
frequency matches the parallel
data rate from the FPGA core.
If you turn this parameter off, a warning message

appears that directs you to pre-register the inputs
in the logic that feeds the transmitter. When using
Cyclone series devices with the ALTLVDS
megafunction, the interface will always send the
MSB of your parallel data first.
November 2008
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26

Page 5 is the Transmitter settings page. It is used to specify the transmitter settings
options. The options for this page are described in Table 23.
Option
Use tx_outclock output port
What is the outclock divide factor

(B)?
(Part 1 of 2)
Description
Comments
The tx_outclock signal is

associated with the serial transmit
data stream.
Except for the following parameter configurations,

every tx_outclock now goes through the shift
register logic:
Specifies the frequency of the

tx_outclock port as
[transmitter output data rate / B].
For valid values, refer to the
relevant device handbook.
When outclock_divide_by = 1, or
When outclock_divide_by =
deserialization_factor (for odd
factors only) and outclock_duty_cycle
is 50.
The tx_outclock frequency is the transmitter

output data rate divided by the outclock divide
factor.
The outclock_duty_cycle of 50 is not
supported when:
deserialization_factor is 5, 7 or 9
outclock_divide_by =
deserialization_factor
outclock_multiply_by is 2.
This is for Cyclone II and Cyclone III (always) and

Stratix IV, Stratix III, and Stratix II when
IMPLEMENT_IN_LES is ON.
Note that for SERDES factor of 5 and 9, outclock
divide factor available are 1, 5, and 9, respectively.
There is no 2.
This is for the Quartus II software version 8.1
tx_outclock with respect to
tx_out (in degrees)?
This value specifies the phase

alignment of tx_outclock with
respect to tx_out or
tx_inclock.
This option is available only if the tx_outclock

port is used.
Use tx_locked output port
This port allows you to monitor

the lock status of the PLL.
The status of the lock port is identical for the

transmitter and receiver when shared PLLs are
used.
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Option
Description
Use tx_coreclock output port
(Part 2 of 2)
Comments
This port is used to show the core

clock frequency during
simulation. The
tx_coreclock port should be
used to register all logic that
feeds the LVDS transmitter
function. If any other clock feeds
the transmit function, your design
must implement the clock domain
transfer circuitry.
You need to add a false path constraint from the

slow_clock to the fast_clock in the
ALTLVDS_TX megafunction, whenever the faster
core_clock implementation is used for odd
deserialization factors.
When using the transmitter function of ALTLVDS
(ALTLVDS_TX), you may get setup timing
violations when using tx_inclock to register
the data that feeds the SERDES blocks. The
ALTLVDS_TX megafunction gives you the choice to
register the tx_in data with either
tx_inclock or tx_coreclock. Beginning in
Quartus II version 5.1, the default setting is
tx_coreclock. Using tx_coreclock to
register the data before it feeds the SERDES is the
better choice since it will have the optimal phase
position to register the data with respect to the
high speed clock that drives the SERDES.
Your setup timing violations should be eliminated
when using tx_coreclock instead of
tx_inclock to register the data in the
ALTLVDS_TX function. Additionally, you should
see better timing margins when using
tx_coreclock instead of tx_inclock even
if you do not have timing violations
What is the clock resource used

for tx_coreclock?
This value specifies the clock

resource type fed to the
tx_coreclock port. Allowed
values are Auto Selection (type is
determined by the compiler),
Global Clock, and Regional
Clock. The default value is Auto
Selection.
This information assists with clock management in

the device.
LVDS Transmitter Using an External PLL

This section discusses the options available for configuring the LVDS transmitter
megafunction if an external PLL is used. To use an external PLL, select Use External
PLL on page 3 of the MegaWizard Plug-In Manager. The options for this page are
described in Table 21 on page 23.
If you choose to implement the LVDS transmitter using an external PLL, you must
implement a PLL outside of the LVDS megafunction. You must ensure your circuit has
the correct input and functionality to generate an appropriate clock frequency, and is
connected to the LVDS transmitter correctly.
f
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For more information about external PLL options, refer to the AN 409: Design Example
Using the ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.
Altera Corporation
28

LVDS Transmitter Using External PLL and Dedicated SERDES Block

The ability to use a dedicated SERDES block in your LVDS transmitter and to clock
the transmitter using an external PLL is device-dependent.
If you use a Stratix IV and a Stratix III device, clock your LVDS transmitter using an
external PLL, and implement the SERDES for the transmitter using a dedicated
SERDES block, a notification window pops up after you enter these settings on page 3
of the MegaWizard Plug-In Manager (Figure 21).
Figure 21. MegaWizard Plug-In Manager Notification for Stratix III Device (LVDS Transmitter)
If you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your
LVDS transmitter using an external PLL, and implement the SERDES for the
transmitter using a dedicated SERDES block, a different notification window pops up
after you enter these settings on page 3 of the MegaWizard Plug-In Manager
(Figure 22).
Figure 22. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Transmitter)
For Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES
for your LVDS transmitter using a dedicated SERDES block, you do not have the
option to use an external PLL.
The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not
have a dedicated SERDES block available for use by your LVDS transmitter.
Therefore, you do not have the option to use a dedicated SERDES block in these
devices.
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29
After you select Use External PLL and do not select Implement
Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In
Manager, and click Next, the Transmitter settings page appears. If you choose to use
an external PLL, this page appears only if you choose to implement SERDES in a
dedicated SERDES block.
This page is the same as the Transmitter settings page that appears when you choose
to use an internal PLL, except the options to create tx_locked and tx_coreclock
output ports are not available. The options that appear in the Transmitter settings
page are described in Table 23 on page 26.
LVDS Transmitter Using External PLL and SERDES in LEs
If you use an Arria GX, Stratix series, Cyclone series, HardCopy II, or
HardCopy Stratix device, clock your LVDS transmitter using an external PLL, and
implement the SERDES for the transmitter using logic cells, a notification window
pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager
(Figure 22).
Figure 23. MegaWizard Plug-In Manager Notification for SERDES in LEs (LVDS Transmitter)
The Transmitter settings page does not appear.
MegaWizard Plug-In Manager Pages for the LVDS Receiver

On page 3, after you select the LVDS receiver, depending on the device you selected,
you can choose to implement the SERDES circuitry in logic cells or in a dedicated
SERDES block. Similarly, depending on the device, you can choose to use an external
PLL. In addition, for the LVDS receiver only, you can choose to enable DPA mode.
LVDS Receiver Using a Dedicated SERDES Block or SERDES in LEs

This section discusses the options available for configuring the LVDS receiver
megafunction if an internal PLL is used.
On page 3, several options can be customized for the receiver settings. The options are
described in Table 24. Except for the option to enable DPA mode, these options are
the same as those described in Table 21 on page 23 for the LVDS transmitter.
However, these meanings are slightly different for the LVDS receiver, because both
the data flow and SERDES functionality are reversed.
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Table 24. ALTLVDS Receiver Settings Page Options and Descriptions (Page 3)
Option
Description
Comments
Implement Serializer/Deserializer
circuitry in logic cells
If not enabled, the megafunction takes

advantage of the dedicated SERDES
circuitry in the device. If enabled, the
SERDES circuitry is implemented in logic
cells. This feature is supported by
Arria GX, Stratix IV, Stratix III, Stratix II,
Stratix II GX, Stratix GX, Stratix,
HardCopy II, and HardCopy Stratix
devices. In the Cyclone series devices,
the SERDES circuitry is always
implemented in logic cells.
If enabled, the receiver starts its operation

on the first fast clock edge after the PLL is
locked. This option is intended for slow
speeds and byte alignment may be different
from the hard SERDES implementation.
Enable Dynamic Phase Alignment

mode (receiver only)
If enabled, the DPA mode helps to

correct skew created by different trace
lengths on the data channels routed to
the device. This mode adds several ports
and parameters to the megafunction
instantiation. This option is available for
Arria GX, Stratix III, Stratix II,
Stratix II GX, Stratix GX, and HardCopy II
devices only.
Enabling the DPA mode changes the

appearance of the graphic representation of
the megafunction in the left-hand pane.
When the DPA mode is turned on, two
pages are added to the MegaWizard Plug-In
Manager to include the additional DPA
mode ports and parameters (the
DPA settings 1 and DPA settings 2 pages).
The number of input channels available

for the LVDS receiver. The allowed values
depend on the pins available in the
device. For the allowed values for your
handbook.
For example, if the number of channels is

44, an rx_in[43..0] port is created.
Altera recommends you to use the

ALTIOBUF megafunction to connect the
channels to actual FPGA pins via the I/O
buffer. By using ALTIOBUF
megafunction, you can control whether
the buffer should be differential.
For further details, refer to the I/O Buffer

(ALTIOBUF) Megafunction User Guide.
What is the deserialization factor? This value determines the number of

serial input data bits that the receiver
deserializes to send to the core on a
single cycle. For the valid deserialization
factors for your device, refer to the
relevant device handbook.
For example, if the deserialization factor is

10 and the number of input channels is 1,
the transmitter deserializes every 10 serial
bits into 10 bits of parallel data to send to
the core. If the deserialization factor is 10
and the number of channels is 44, an
rx_out[439..0] port is created.
Use External PLL
If not enabled, the next page displays the

PLL settings. The PLL settings page is
skipped if this option is enabled.
This determines whether to use an

external PLL to clock the SERDES
receiver. If this option is not enabled, the
megafunction automatically implements
an internal PLL to clock the LVDS
receiver block. If this option is enabled, a
separate PLL must be used to provide
the clocking source. It is your
responsibility to make the necessary
connections.

its functionality is implemented in DDR
factor of four to use the external PLL
option.
Page 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This page
appears only if an internal PLL is used.
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Table 25 describes the options you have on page 4 to customize the frequency and PLL settings,
depending on the device and options you selected on previous pages. These options are different
than those described in Table 22 on page 24 for the LVDS transmitter.
Table 25. ALTLVDS Receiver Frequency and PLL Settings Options (Page 4)
Option
(Part 1 of 3)
Description
Comments
This value determines the allowed input
clock rate values.
This value specifies the data rate for the

input channel of the receiver, in Mbps. For
data rate ranges, refer to the specific DC &
Switching Characteristics chapter in the
appropriate device handbook.
The value specifies the input clock

frequency to the internal PLL. The allowed
values depend on the input data rate
selected.
Use source-synchronous mode of

the PLL
If enabled, the phase relationship between

data and clock at the pin is maintained at
the data capture point. Selecting this option
forces the megafunction instantiation to
make the required phase adjustments to
guarantee a consistent relationship between
the clock and data at the capture register
and at the pin.
This option should always be selected,

unless you have already performed all of
the necessary phase adjustments
manually. Altera recommends that you
enable this option when using
non-dedicated SERDES schemes. This
option is available only if the SERDES is
implemented in LEs.
Align clock to the center of the

data window
When enabled, a phase shift of 90 is added

to the clock to center the clock in the data.
This option is available only for Arria GX,

Stratix II GX, Stratix II, and HardCopy II
devices when SERDES is implemented in
logic cells, and for Cyclone II devices. For
Cyclone III devices, Stratix IV, and
Stratix III (LE Implementation) devices,
this option is not available.
Enable self-reset on lost lock in

PLL
If enabled, the PLL resets automatically

whenever it loses lock.
This option is available only for Stratix IV,

Stratix III and Cyclone III devices when
SERDES is implemented in logic cells.
Use shared PLL(s) for receivers

and transmitters
When this option is enabled, your LVDS

receivers and transmitters can share the
same PLL.
This option can be used if the LVDS

receivers and transmitters use the same
input clock frequency, deserialization
factor, and data rates.
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Option
(Part 2 of 3)
Description
This option gives you control over the
asynchronous reset port of the fast PLL
that is used with this function.
Comments
When the transmitter shares the PLL
with the receiver and the pll_areset
port is used, this port must be used in
both megafunction instantiations and the
two signals must be tied together in the
design file. If the pll_areset port is
used in one megafunction instance and
not the other, the PLLs are not shared,
and a warning appears during
compilation.
The PLL must be reset in order for the
output clock phase relationships to be
set correctly when the PLL loses lock or
if the PLL input reference clock is not
stable when the device completes the
configuration process.
Use rx_pll_enable input port
This port gives you control over the enable

port of the fast PLL that is used with this
function.
If the receiver shares the PLL with the

transmitter, and the rx_pll_enable
port is used, this port must be used in
both megafunction instantiations and the
two signals must be tied together in the
design file. If the PLL-enable port is used
in one megafunction instance and not the
other, the PLLs are not shared, and a
warning appears during compilation.
Use rx_locked output port
This port allows you to monitor the lock

status of the PLL. The status of the lock
port is identical for the transmitter and the
receiver when shared PLLs are used. In this
case, monitor the lock output from the
receiver megafunction.
This value determines the phase alignment

of the data received by the receiver core
rx_in with respect to the rising
edge of 'rx_inclock'? (in degrees) with respect to rx_inclock. Available
values are 0 (edge-aligned), 45, 90, 135,
180 (center-aligned), 225, 270, 315.If the
DPA mode is not used, the extra two pages
for DPA do not appear, but the option, What
is the alignment of data with respect to
the rising edge of rx_inclock? (in
degrees) is added.
This option is only available if DPA mode

is not enabled.
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Option
(Part 3 of 3)
Description
Comments
What is the clock resource used

for rx_outclock?
This value specifies the clock resource type

fed from the rx_outclock port. Allowed
values are Auto Selection (type is
determined by the compiler), Global Clock,
and Regional Clock. The default value is
Auto Selection.
Enable FIFO for DPA channels
The phase-compensation FIFO

synchronizes parallel data to the global
clock domain of the core. This option is
available only in Stratix GX devices when
the DPA mode is enabled.
This information assists with clock

management in the device.
If the DPA mode is enabled, the DPA settings 1 and DPA settings 2 pages appear. The
DPA mode is supported by Arria GX, Stratix IV, Stratix III, Stratix II, Stratix II GX,
Stratix GX, and HardCopy II devices only.
The options on the DPA settings 1 page are described in Table 26.
Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 1 of 2)
Option
Description
Comments
Use rx_divfwdclk output port and

bypass the DPA FIFO
This feature is the soft CDR feature. It

If enabled, the DPA clock is divided by the
deserialization factor and then forwarded to is available in Stratix IV and Stratix III
devices only.
the core. The DPA clock drives the bitslip
and alignment circuitry, bypassing the FIFO.
What is the simulated recovered

clock phase drift?
The Quartus II software supports

simulation of the recovered clock using the
user-specified ppm value. The ppm value
specifies the number of clock cycles drift
between the transmitter and the receiver
after a million clock cycles. The drift is
positive if the transmitter is faster than the
receiver, and negative if the receiver is
faster than the transmitter. The Quartus II
simulator simulates the ppm variation by
shifting the recovered data and clock based
on the user-specified ppm value.
This feature is available in Stratix IV

and Stratix III devices only. It is part of
the soft-CDR feature. It is available
only if the Use rx_divfwdclk output
port and bypass the DPA FIFO option
is enabled.
Use rx_dpll_enable input port
This port enables the path through the DPA

circuitry. The option supports dynamic,
channel-by-channel control of the DPA
circuitry.
To enable the DPA circuitry for a

channel, set the port for the target
channel to 1. If this port is not used,
the Quartus II software enables all of
the channels. This option is available
only if the Use rx_divfwdclk output
port and bypass the DPA FIFO option
is disabled.
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Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 2 of 2)
Option
Description
Comments
Use rx_dpll_hold input port
This port prevents the DPA circuitry from

switching to a new clock phase on the
target channel. Each DPA block monitors
the phase of the incoming data stream
continuously, and selects a new clock
phase when needed. When this port is held
high, the selected channels hold their
current phase setting.
Use rx_fifo_reset input port
This port resets the FIFO between the DPA

circuit and the data alignment circuit. The
FIFO holds data passing between the DPA
and the LVDS clock domains. When this
port is held high, the FIFOs in the selected
channels are reset.
This option is available only if the Use

rx_divfwdclk output port and bypass
the DPA FIFO option is disabled.
The options on the DPA Settings 2 page are described in Table 27.
Table 27. ALTLVDS Receiver DPA Settings 2 Options (Page 6)

Parameter
Description
Use rx_reset input port
This port resets all of the components of

the DPA circuit.
Use rx_dpa_locked output port
The DPA block samples the data on one of

eight phase clocks with a 45 resolution
between phases. This port lets you monitor
the status of the DPA circuit and determine
when it has locked onto the phase closest
to the incoming data phase.
rx_dpa_Locked will be de-asserted for
at least one parallel clock cycle.
Comments
The DPA circuit must be retrained
after it is reset using this port.
After power up or reset, the
rx_dpa_locked signal is asserted
after the DPA circuitry acquires an

initial lock to the optimum phase.
You must not use the
rx_dpa_locked signal to validate
the integrity of the LVDS link. Use
error checkers (for example, CRC or
DIP4) to validate the integrity of the
LVDS link.
Use a DPA initial phase selection of
This option selects the initial phase setting. This option is available for Stratix IV
and Stratix III devices only.
Specify whether to enable this option and
its value. Simulation honors this phase
selection in simulating the forwarded clock.
Align DPA to rising edge of data only
This option determines whether the DPA

aligns to the rising edge of the data only or
to both the rising and falling edges of the
data.
This option is available for Stratix IV

and Stratix III devices only.
For more information about the DPA receiver circuit, refer to the AN 236: Using
Source-Synchronous Signaling with DPA in Stratix GX Devices.
The options on the Receiver settings page are described in Table 28.
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Table 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 1 of 2)
Parameter
Description
Comments
Register outputs
If this option is enabled, the outputs of

the receiver are registered by
rx_outclock.
If you do not register the receiver

outputs here, you must register them
in the design logic that is fed by the
receiver and specify a 'Source
Multiply' assignment from the receiver
to the output registers with a value
equal to the deserialization factor.
Use 'rx_channel_data_align' input port
This port lets you control bit insertion

on a channel-by-channel basis to align
the word boundaries of the incoming
data. The data slips one bit for every
pulse on rx_channel_data_align
port. This option is available only if a
dedicated SERDES block is used.
The following requirements must be

met for this port:
The minimum pulse width is one

period of the parallel clock in the
logic array (rx_outclock).
The minimum low time between

pulses is one period of the parallel
clock.
There is no maximum high or low

time.
Valid data is available two parallel

clock cycles after the rising edge of
rx_channel_data_align.
Use 'rx_cda_reset' input port
This port is available only if Use

'rx_channel_data_align' input port is
turned on. The port resets the data
alignment circuitry, restoring the
latency bit counter to zero. This option
is available only if a dedicated SERDES
block is used.
Use 'rx_cda_max' output port
This port indicates when the rollover

point has been reached in the data
alignment circuit. This port is available
only if Use 'rx_channel_data_align'
input port is turned on. This option is
available only if a dedicated SERDES
block is used.
After how many pulses does the data

alignment circuitry restore the serial
latency back to 0?
Available values for this option range

from 1 to 11. The value does not have
to be the same as the deserialization
factor. This option is available only if a
dedicated SERDES block is used.
Altera recommends you to set this

value to be equal to or greater than the
deserialization factor, allowing enough
depth in the alignment circuit to cycle
through an entire word.
Align data to the rising edge of clock
LVDS input data is aligned at the rising

edge of the LVDS clock. This option is
available only if a dedicated SERDES
block is used.
If the selection is unchecked, the LVDS

data is aligned to the falling edge of the
clock.
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Table 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 2 of 2)
Parameter
Description
Comments
Enable bitslip control
This port lets you control bit insertion

to align the word boundaries of the
incoming data. The data slips one bit
for every pulse on rx_data_align
port. This option is available only if the
SERDES is implemented in LEs.
The port skips a bit when it is asserted

long enough to be captured by the fast
clock edge. rx_data_align is
slightly different from the Stratix
behavior in that, each pulse has to be
long enough for one slow clock cycle
(instead of two in Stratix).
Enable independent bitslip controls for

each channel
If enabled, it allows independent

rx_data_align port for each
channel so you can control each
channels bit-slip capability
independently.
This option is available if the SERDES

is implemented in LEs
Register the bitslip control input using

'rx_outclock'
This port allows you to enable the

receivers synchronization register.

is implemented in LEs.
If you enable this option, you can also

add an extra register to register
rx_data_align port using
rx_outclock.
Use 'rx_data_align_reset' input port
If enabled, creates the reset port for

the bit-slip circuitry.

is implemented in LEs.
LVDS Receiver Using an External PLL

This section discusses the options available for configuring the LVDS receiver
megafunction when an external PLL is used. To use an external PLL, select Use
External PLL on page 3 of the MegaWizard Plug-In Manager. The options for this
page are described in Table 24 on page 210.
If you choose to implement the LVDS receiver using an external PLL, you must
implement a PLL outside of the LVDS megafunction. You must ensure your circuit has
the correct input and functionality to generate an appropriate clock frequency, and is
connected to the LVDS receiver correctly.
f
For more information about external PLL, refer to AN 409: Design Example Using the
ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.
LVDS Receiver Using External PLL and Dedicated SERDES Block
The ability to use a dedicated SERDES block in your LVDS receiver and to clock the
transmitter using an external PLL is device-dependent, just as it is for an LVDS
transmitter.
If you use a Stratix IV or a Stratix III device, clock your LVDS receiver using an
external PLL, and implement the SERDES for the receiver using a dedicated SERDES
block, a notification window pops up after you enter these settings on page 3 of the
MegaWizard Plug-In Manager Figure 24).
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Figure 24. MegaWizard Plug-In Manager Notification for Stratix III Device (LVDS Receiver)
If you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your
LVDS receiver using an external PLL, and implement the SERDES for the receiver
using a dedicated SERDES block, a different notification window pops up after you
enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 25).
Figure 25. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Receiver)
In Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES
for your LVDS receiver using a dedicated SERDES block, you do not have the option
to use an external PLL.
The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not
have a dedicated SERDES block available for use by your LVDS receiver. Therefore,
you do not have the option to use a dedicated SERDES block in these devices.
After you select Use External PLL and do not select Implement
Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In
Manager, and then click Next, the DPA settings 1 page or the Receiver settings page
appears.
This page is the same as the Receiver settings page that appears when you choose to
use an internal PLL, except different options are disabled. The options that appear in
the Receiver settings page are described in Table 28 on page 215.
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Instantiating Megafunctions in HDL Code or Schematic Designs
LVDS Receiver Using External PLL and SERDES in LEs

If you use an Arria GX, Stratix series, Cyclone series, HardCopy II, or
HardCopy Stratix device, clock your LVDS receiver using an external PLL, and
implement the SERDES for the receiver using logic cells, a notification window pops
up after you enter these settings on page 3 of the MegaWizard Plug-In Manager
(Figure 26).
Figure 26. MegaWizard Plug-In Manager Notification for SERDES in LEs (LVDS Receiver)
The Receiver settings page appears with only the Use rx_data_align input port
option available.
Common Pages for ALTLVDS Receiver and Transmitter

Page 8 lists the simulation libraries required for functional simulation by third-party
tools. On this page, you can choose to generate a synthesis area and timing estimation
netlist.
Page 9 of the ALTLVDS MegaWizard Plug-In Manager displays a list of the types of
files to be generated. The automatically generated Variation file contains wrapper
code in the language you specified on page 2a. On page 9, you can specify additional
types of files to be generated. Choose from the PinPlanner ports PPF file (.ppf), AHDL
Include file (<function name>.inc), VHDL component declaration file, <function
name>.cmp), Quartus II symbol file (<function name>.bsf), Instantiation template file
(<function name> .v), and Verilog HDL black box file (<function name>_bb.v). If you
selected Generate netlist on page 8, the file for the synthesis area and timing
estimation netlist is also available. A gray checkmark indicates a file that is
automatically generated, and a red checkmark indicates an optional file.
f
For more information about the ports and parameters for the ALTLVDS
megafunction, refer to Chapter 3, Specifications.

When you use the MegaWizard Plug-In Manager to customize and parameterize a
megafunction, it creates a set of output files that allow you to instantiate the
customized function in your design. Depending on the language you choose in the
MegaWizard Plug-In Manager, the wizard instantiates the megafunction with the
correct parameter values and generates a megafunction variation file (wrapper file) in
Verilog HDL (.v), VHDL (.vhd), or AHDL (.tdf), along with other supporting files.
The MegaWizard Plug-In Manager provides options to create the following files:
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A sample instantiation template for the language of the variation file (_inst.v,
_inst.vhd, or _inst.tdf)
Component Declaration File (.cmp) that can be used in VHDL Design Files
ADHL Include File (.inc) that can be used in Text Design Files (.tdf)
Quartus II Block Symbol File (.bsf) that can be used in schematic designs
Verilog HDL module declaration file that can be used when instantiating the
megafunction as a black box in a third-party synthesis tool (_bb.v)
For more information about the wizard-generated files, refer to the Quartus II Help or
to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
Generating a Netlist for EDA Tool Use

If you use a third-party EDA synthesis tool, you can instantiate the megafunction
variation file as a black box for synthesis. Use the VHDL component declaration or
Verilog module declaration black box file to define the function in your synthesis tool,
and then include the megafunction variation file in your Quartus II project.
If you enable the option to generate a synthesis area and timing estimation netlist in
the MegaWizard Plug-In Manager, the wizard generates an additional netlist file
(_syn.v). The netlist file is a representation of the customized logic used in the
Quartus II software. The file provides the connectivity of the architectural elements in
the megafunction but may not represent true functionality. This information enables
certain third-party synthesis tools to better report area and timing estimates.
Additionally, synthesis tools can use the timing information to focus timing-driven
optimizations and improve the quality of results.
f
For more information about using megafunctions in your third-party synthesis tool,
refer to the appropriate chapter in the Synthesis section in volume 1 of the Quartus II
Handbook.
Using the Port and Parameter Definitions

Instead of using the MegaWizard Plug-In Manager, you can instantiate the
megafunction directly in your Verilog HDL, VHDL, or AHDL code by calling the
megafunction and setting its parameters as you would any other module, component,
or subdesign. For the ALTLVDS megafunction, many ports and parameters are
available for specific device families only, and some are available only when other
features have been enabled. For example, in Stratix GX devices,
rx_channel_data_align[] port is available only when the DPA mode option is
turned on. When DPA mode is turned off, rx_data_align port is available for use.
1
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Altera strongly recommends that you use the MegaWizard Plug-In Manager for
complex megafunctions. The MegaWizard Plug-In Manager ensures that you set all
megafunction parameters properly.
Refer to Chapter 3, Specifications for a list of the megafunction ports and parameters.
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Identifying a Megafunction After Compilation
Example 21 contains the VHDL code from a Stratix LVDS receiver. This template can
be used for any VHDL ALTLVDS function. Substitute appropriate ports and
parameters as needed in your design.
Example 21. VHDL Code from the Stratix LVDS Receiver
INCLUDE "altlvds_rx.inc";
SUBDESIGN stratix_rx
(
rx_in[0..0] : INPUT;
rx_inclock : INPUT = GND;
rx_pll_enable : INPUT = VCC;
rx_data_align : INPUT;
pll_areset : INPUT = GND;
rx_out[3..0] : OUTPUT;
rx_locked : OUTPUT;
rx_outclock : OUTPUT;
)
VARIABLE
ALTLVDS_rx_component : altlvds_rx WITH (
INTENDED_DEVICE_FAMILY = "Stratix",
NUMBER_OF_CHANNELS = 1,
DESERIALIZATION_FACTOR = 4,
LPM_TYPE = "altlvds_rx",
COMMON_RX_TX_PLL = "ON",
OUTCLOCK_RESOURCE = "AUTO",
INCLOCK_PERIOD = 9523,
INPUT_DATA_RATE = 840,
INCLOCK_DATA_ALIGNMENT = "EDGE_ALIGNED",
REGISTERED_OUTPUT = "ON",
REGISTERED_DATA_ALIGN_INPUT = "ON"
);
BEGIN
rx_locked = altlvds_rx_component.rx_locked;
rx_out[3..0] = altlvds_rx_component.rx_out[3..0];
rx_outclock = altlvds_rx_component.rx_outclock;
altlvds_rx_component.pll_areset = pll_areset;
altlvds_rx_component.rx_inclock = rx_inclock;
altlvds_rx_component.rx_in[0..0] = rx_in[0..0];
altlvds_rx_component.rx_data_align = rx_data_align;
altlvds_rx_component.rx_pll_enable = rx_pll_enable;
END;

During compilation with the Quartus II software, analysis and elaboration is
performed to build the structure of your design. To locate your megafunction in the
Project Navigator window, expand the compilation hierarchy and find the
megafunction by its name. To search for node names within the megafunction (using
the Node Finder), click Browse in the Look in box and select the megafunction in the
Hierarchy box (Figure 27).
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Figure 27. Compilation Hierarchy Window
You can use the project hierarchy to find megafunction instantiations in the Floorplan
Editor. Right-click on the megafunction you want to view, and choose the Quartus II
editor in which you want to view it (Figure 28).
Figure 28. Compilation Hierarchy Navigation Option
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Design Example 1: LVDS-to-LVDS Bridge Using Different Clock
You can also locate your megafunctions in the Node Finder when making
assignments in the assignment editor. Figure 29 shows an example of how the
megafunction logic is shown in the Node Finder.
Figure 29. Node Finder View of ALTLVDS Transmitter Megafunction

Frequencies
With the inclusion of DPA circuitry, Stratix II devices offer enhanced support for
source-synchronous protocols. The enhanced source-synchronous channels on
Stratix II devices support 1-Gbps data transfer, while the dedicated DPA circuitry
simplifies printed circuit board design by eliminating signal-alignment issues
introduced by clock-to-channel and channel-to-channel skew. Stratix II devices
support a wide array of high-speed protocols and can be used to bridge high-speed
interfaces.
This design example uses a Stratix II device to bridge a 1-Gbps LVDS interface using a
500-MHz reference clock to a 1-Gbps LVDS interface using a 250-MHz reference clock.
The ALTLVDS receiver function uses DPA circuitry. The transmitter and receiver
share one fast PLL.
The focus of this design is to illustrate the features available in the MegaWizard
Plug-In Manager. No user logic is shown between the receiver and transmitter blocks,
and all ports are connected to input or output pins. Most designs use custom logic for
many of the control ports within the FPGA. However, for this design example, all
such parameters are controlled outside of the Stratix II device.
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Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies
223
Design Files
The design files are available with this user guide in the Quartus II Project section and
in the User Guides section of the Altera website (www.altera.com).
In this example, you create two files using the MegaWizard Plug-In Manager: one for
an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in
Verilog HDL (.vhd) and are included in your project directory when completed.
Example
In this example, you will complete the following tasks:
Generate a high-speed differential receiver in DPA mode using the ALTLVDS

megafunction and the MegaWizard Plug-In Manager
Generate a high-speed differential transmitter using the ALTLVDS megafunction

and the MegaWizard Plug-In Manager
Implement the receiver and transmitter functions in the device by adding your
custom megafunctions to the project and compiling the project
Simulate the high-speed differential interface design using the ModelSim -Altera
software
Generate an ALTLVDS Receiver and ALTLVDS Transmitter

To generate the LVDS receiver, perform the following steps:
1. Open the ALTLVDS_DesignExample.zip file and extract the Quartus II archive
project ALTLVDS_stratixII.qar.
2. In the Quartus II software, open ALTLVDS_stratixII.qar and restore the archive
file into your working directory.
3. Open the top-level block editor file ALTLVDS_stratixII.bdf.
The file ALTLVDS_stratixII.bdf is an incomplete file that you will complete in the
course of this example. The ALTLVDS megafunction created in this example are
added to the top-level file.
4. Double-click anywhere in the white space in the block editor file. The Symbol
window appears.
5. In the Symbol window, click on MegaWizard Plug-In Manager. Page 1 of the
MegaWizard Plug-In Manager appears.
6. Select Create a new custom megafunction variation.
7. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.
8. In the MegaWizard Plug-In Manager pages, select or verify the configuration
settings shown in Table 29. Click Next to advance from one page to the next.
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Table 29. Configuration Settings for Design Example 1 (LVDS Receiver)

MegaWizard Plug-In Manager
Page
2a
(Part 1 of 2)

Configuration Setting
Value
Megafunction
Under I/O, select ALTLVDS
Device family
Stratix II
Output file type
Verilog HDL
Output file name
stratixii_rx
Return to this page for another create

operation
Selected
Currently selected device family
Stratix II
Match project/default
Selected
This module acts as an
LVDS receiver
Implement SERDES in logic cells
Not selected
Enable Dynamic Phase Alignment mode

(receiver only)
Selected
What is the deserialization factor?
Use External PLL
Not selected
What is the input data rate?
1 Gbps (1,000 Mbps)
Clock frequency
Clock frequency
500 MHz
Use shared PLLs(s) for receivers and

transmitters
Selected
Selected (The PLL must be reset in order

for the output clock phase relationships
to be set correctly when the PLL loses
lock or if the PLL input reference clock is
not stable when the device completes the
configuration process.)
Selected
Not selected
What is the clock resource for

rx_outclock?
Auto selection
Selected
Selected
Use rx_fifo_reset input port
Selected
Selected
Reset DPA circuitry
Automatically reset the bit serial FIFO

when rx_dpa_locked rises for the first
time.
Selected
When should the rx_dpa_locked fall

low?
When there are two phase changes in

same direction.
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Page
7
(Part 2 of 2)

Value
Register outputs
Selected
Use rx_channel_data_align input port
Selected
Use rx_cda_reset input port
Selected
Use rx_cda_max output port
Selected
After how many pulses does the data

alignment circuitry restore the serial data
latency back to 0?
Generate netlist
Not selected
Variation file (.v)
Selected
PinPlanner ports file (.PPF)
Selected
AHDL Include file (.inc)
Selected
VHDL component declaration file (.cmp)
Selected
Quartus II symbol file (.bsf)
Selected
Instantiation template file (_inst.v)
Selected
Verilog HDL black box file (_bb.v)
Selected
9. Click Finish. The stratixii_rx module is built.

10. Click OK. The MegaWizard Plug-In Manager resets to page 2a to allow you to
create a new custom megafunction variation for the LVDS transmitter.
settings shown in Table 210.
Table 210. Configuration Settings for Design Example 1 (LVDS Transmitter)
Page
2a
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(Part 1 of 2)

Value
Megafunction
Device family
Stratix II
Output file type
Verilog HDL
Output file name
stratixii_tx

operation
Not selected
Stratix II
Selected
LVDS transmitter
Not selected
Use External PLL
Not selected
226


Page
4
(Part 2 of 2)

Value
1 Gbps (1,000 Mbps)
Clock frequency
Clock frequency
500 MHz
What is the phase alignment of tx_in

with respect to the rising edge of
tx_inclock (in degrees)
Selected
Selected
(The PLL must be reset in order for the
set correctly when the PLL loses lock or
if the PLL input reference clock is not
stable when the device completes the
Use shared PLL(s) for receivers and

transmitters
Selected
Register tx_in using
tx_coreclock
Selected
What is the outclock divide factor (B)?

tx_outclock with respect to tx_out (in
degrees)
Selected
Selected
What is the clock resource used for

tx_coreclock?
Auto selection
Generate netlist
Not selected
Variation file (.v)
Selected
Selected
Selected
Selected
Selected
Selected
Selected
12. Click Finish. The stratixii_tx module is built.

13. Click OK.
14. Place the stratixii_tx symbol in the altlvds_stratixii block editor design file under
the text INSERT STRATIXII_TX HERE, aligning the input and output ports with
the signals already present in the design file.
15. Double-click anywhere in the white space of the design file. The Symbol window
appears.
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16. Choose stratixii_rx from the Project library list and click OK (Figure 210). You
may have to expand the Project folder to see the megafunctions it contains.
Figure 210. Design Example 1 Symbol View of stratixii_rx
17. Place the stratixii_rx symbol in the altlvds_stratixII block editor design file under
the text INSERT STRATIXII_RX HERE and align the input and output ports with
the signals already present in the design file.
The block diagram file should look similar to Figure 210.
Figure 211. Design Example 1 Top-Level Block Design File
18. On the File menu, click Save.

19. On the Processing menu, click Start Compilation.
20. When the Full Compilation was successful message box appears, click OK.
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Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the

ModelSim-Altera Simulator
Simulate the design in the ModelSim-Altera software to generate a waveform display
of the device behavior.
This user guide assumes that you are familiar with using the ModelSim-Altera tool
before trying out the design example. If you are unfamiliar with using the
ModelSim-Altera simulator, refer to the Support page for software products on the
Altera website (www.altera.com). On the Support page, there are various links to
topics such as installation, usage, and troubleshooting.
Set up the ModelSim-Altera simulator by performing the following steps:
1. Unzip the altlvds_ex1_msim.zip file to any working directory on your PC.
2. Start the ModelSim-Altera software.
3. On the File menu, click Change Directory.
4. Select the folder in which you unzipped the files. Click OK.
5. On the Tools menu, point to TCL and click Execute Macro. The Execute Do File
dialog box will appear.
6. Select the altlvds_ex1_msim.do file and click Open. This is a script file for the
ModelSim software that automates all the necessary settings for the simulation.
7. Verify the results shown in the Waveform Viewer window.
You can rearrange signals, remove signals, add signals, and change the radix by
modifying the script in altlvds_ex1_msim.do. Figure 212 shows the expected
simulation results in the ModelSim simulator.
Figure 212. Design Example 1 ModelSim Simulation Results
This waveform file contains only the input and output pins that are shown. You can
add internal post-compilation nodes with the Node Finder to view all of the data
paths in the design. You can verify that tx_outclock has a 4-ns period, which
corresponds to a 250-MHz clock rate, as specified in the design.
The input serial data rx_in is edge-aligned to the reference clock clk_in_500MHz,
and the output serial data tx_out is edge-aligned to tx_outclock as specified in
the transmitter megafunction.
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229
This simulation output verifies that 1-Gbps data can be successfully received by and
transmitted from the Stratix II device.
You can change the input vectors in the waveform editor to experiment with the other
features, such as data alignment, to view the functionality and help you understand
the ALTLVDS megafunction.

The following design example illustrates the connection scheme used in Cyclone II
devices for an ALTLVDS receiver and transmitter using a common PLL. The
ALTLVDS_RX and ALTLVDS_TX functions are set up using the external PLL option.
This example shows step by step how to set up the ALTLVDS_RX and ALTLVDS_TX
functions. Note that the ALTPLL function has already been set up in the design file.
f
For PLL-specific information and for examples of PLL clock relationships, refer to the
ALTPLL Megafunction Users Guide.
You can use the external PLL option in ALTLVDS to give you direct access to all of the
PLL clocks that are not accessible when you allow ALTLVDS to infer the PLL for you.
This option gives you the ability to use the PLL output clocks throughout your design
for other functions besides the serialization and deserialization of data.
Design Files
VHDL (.vhd) and are included in your project directory when completed. The PLL
block is already customized in the design.
Example
This example shows how to design a 600 Mbps receiver with a deserialization factor
of 8 and a 600 Mbps transmitter with the same deserialization factor of 8. The input
reference clock frequency is 75 MHz.
In this example, you will perform the following activities:
November 2008
Generate a high-speed differential receiver using the ALTLVDS megafunction and

the MegaWizard Plug-In Manager.

and the MegaWizard Plug-In Manager.
View description of the external PLL settings used to clock the transmitter and
receiver blocks.
Implement the receiver, transmitter, and PLL in the device by adding your custom
megafunctions to the project and compiling the project.
Simulate the high-speed differential interface design.
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1. Open the altlvds_DesignExample_ex2.zip file and extract the Quartus II archive
project cii_ALTLVDS_extpll.qar.
2. In the Quartus II software, open cii_altlvds_extpll.qar and restore the archive file
into your working directory.
3. Open the top-level block editor file cii_altlvds_extpll.bdf.
4. The file cii_altlvds_extpll.bdf is an incomplete file that you will complete in the
course of this example. The ALTLVDS megafunction created in this example are
added to the top-level file.
5. Double-click anywhere in the white space in the block editor file. The Symbol
window appears.
6. In the Symbol window, click on MegaWizard Plug-In Manager. Page 1 of the
Table 211. Configuration Settings for Design Example 2 (LVDS Receiver) (Part 1 of 2)
Page
2a

Value
Megafunction
Device family
Cyclone II
Output file type
VHDL
Output file name
rx_block

operation
Selected
Cyclone II
Match project / default
Selected
LVDS receiver
Selected
What is deserialization factor?
Use External PLL
Selected
set correctly when the PLL loses lock
or if the PLL input reference clock is
not stable when the device completes
the configuration process)
Enable bitslip control
Not selected
Generate netlist
Not selected
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Table 211. Configuration Settings for Design Example 2 (LVDS Receiver) (Part 2 of 2)
Page
6

Value
Variation file (.v)
Selected
Selected
Selected
Selected
Selected
Instantiation template file (inst.v)
Selected
10. .Click Finish. The rx_block module is built.

settings shown in Table 212.
Page
2a
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(Part 1 of 2)

Value
Megafunction
Device family
Cyclone II
Output file type
VHDL
Output file name
tx_block

operation
Not selected
Cyclone II
Selected
LVDS transmitter
Selected
Number of channels
Deserialization factor
Use External PLL
Selected
output clock phase relationships to be set
correctly when the PLL loses lock or if the
PLL input reference clock is not stable
when the device completes the
Generate netlist
Not selected
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Page
5
(Part 2 of 2)

Value
Variation file (.v)
Selected
Selected
Selected
VHDL component declaration file

(.cmp)
Selected
Selected
Selected
13. Click Finish. The tx_block module is built.

The symbol for the ALTLVDS transmitter function you just created appears in the
Symbol window (Figure 213).
Figure 213. Design Example 2 Symbol View of tx_block
Integrating the ALTLVDS Receiver and Transmitter in the Design

To integrate the ALTLVDS receiver and transmitter in the final design:
1. After the ALTLVDS transmitter function you just created appears in the Symbol
window, click OK to return to the block design editor with the tx_block attached
to your cursor.
2. Place the rx_block representation in the top-level file under the text Place tx_block
here, aligning the input and output ports to the existing connections. Left-click to
drop the tx_block in place.
3. Double-click anywhere in the white space of the design file. The Symbol window
appears.
4. Select rx_block from the Project library list and click OK. You may have to expand
the Project folder to see the megafunctions it contains.
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5. Place the rx_block symbol in the block editor design file under the text Place
rx_block here and align the input and output ports with the signals already
present in the design file.
The rest of the components for this design are already in the top-level file. They
include two instantiations of DFF and one instantiation of ALTPLL named lvds_pll
in this example. After you place the rx_block and tx_block, the top level should
look like Figure 214.
Figure 214. Design Example 2 Top-Level Block Design File
If you do not want to create the rx_block and tx_block, they are located in the
backup folder within the project directory. You can move them to the top-level
directory and insert them directly into the top-level design.
Parameters Used by ALTPLL

When you instantiate an ALTLVDS megafunction in external PLL mode, Altera
recommends you set up the data rate and clocking using the ALTPLL megafunction.
For Cyclone devices, you must use the Normal Mode compensation. For Cyclone II
devices, you can choose either the Normal Mode or the Source-Synchronous
Compensation Mode. The Source-Synchronous is the recommended compensation
mode in Cyclone II devices.
f
For details about PLL compensation modes, refer to the PLL chapter of the relevant
device handbook.
The LVDS receiver and transmitter in this design example operate at a 600 Mbps data
rate with deserialization and serialization factors of 8. The reference clock frequency is
equal to the data rate divided by the deserialization factor, which is 75 MHz.
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Cyclone and Cyclone II devices use DDIO registers as part of the SERDES interface.
Because the data is clocked on both the rising and falling edge, the clock frequency
must be half the data rate; therefore, the fast clock from the PLL runs at half the data
rate. The core clock frequency (also referred to as the slow clock) is the data rate
divided by the serialization factor (J). In this example, the slow clock is the same
frequency as the reference clock, but is phase-aligned to the fast clock from the PLL.
The PLL in this design example is in the Source-Synchronous Compensation mode,
using the following selections for the megafunction.
Select C0 for Which output clock will be compensated for?
Enter 75 MHz for What is the frequency of the inclock0 input?
Turn on ports for the asynchronous reset function and locked output.
C0 is the high speed clock. The data rate for this design example is 600 Mbps. The C0
signal must have a frequency of one half the data rate, so the output frequency must
be set to 300 MHz. The phase you select depends on the reference clock to data
relationship at the pins of the device. The Source-Synchronous Compensation mode
maintains the clock to data relationship to the I/O element capture registers on the
receiver.
In this design example, the reference clock and data are rising edge aligned (the bit
boundary is synchronous to the rising edge of the reference clock, and 8 bits are
received in every clock period). The C0 must be phase-shifted to properly capture the
data internally at the registers.
For edge-aligned interfaces, you would normally phase-shift your high speed clock
by 180 to center-align the clock and data relationship at the capture register.
However, because Cyclone and Cyclone II devices use a half-rate high-speed clock,
due to the DDIO implementation, a 180 phase-shift would simply switch the rising
edge with the falling edge. To move the capture clock with respect to the DDIO data, a
90 phase shift is required.
C1 is the low speed clock. For even SERDES factors, it must be the data rate divided
by the SERDES factor (J). In this example, the C1 is 75 MHz (600 Mbps / 8). The
phase-shift on the C1 must correspond to the phase-shift on the C0. The data is
edge-aligned with respect to the reference clock at the input pins, so the clocks have to
phase-shift to center-align the rising edge in the core. The high speed to low speed
data transfer does not use the DDIO circuitry, so you can calculate 180 / J to
determine the correct phase shift for this clock to achieve the desired data alignment.
In this example, the result is 22.5, which you use for the C1 phase-shift.
The receiver and transmitter use the same PLL in this example. The phase shifts are
optimized to capture data at the receiver, but they also determine a fixed relationship
of clock and data at the transmitter. If the slow clock is forwarded with the transmit
data, it is center-aligned. If a different clock frequency and phase are desired, you can
enable the C2 output port of the PLL (in Cyclone devices, the third port of the PLL is
E0). The frequency and phase are restricted to the possibilities available for the
ALTPLL megafunction parameters.
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235

Quartus II Software
This section describes how to verify the cii_altlvds_stratixii design example
you just created. It illustrates the data and clock relationship on the serial channels
received and transmitted by the Cyclone II device. The design example files include a
simple vector waveform created for this example. The following steps assume that
you have successfully compiled the cii_altlvds_extpll design.
1. On the Processing menu, click Generate Functional Simulation Netlist.
2. When the Functional Simulation Netlist Generation was successful message box
appears, click OK.
3. On the Assignments menu, click Settings.
4. In the Category list, select Simulator Settings.
5. In the Simulation mode list, select Functional.
6. In the Simulation input box, type cii_altlvds_extpll.vwf, or click Browse
(...) to select the file in the project folder.
7. Select Run simulation until all vector stimuli are used.
8. In the Category list, select Simulation Verification.
9. Select Simulation coverage reporting and deselect Check outputs.
10. In the Category list, select Simulation Output Files.
11. Select Automatically add pins to simulation output waveforms, deselect
Overwrite simulation input file with simulation results, and deselect Generate
Signal Activity File.
12. Click OK.
13. On the Processing menu, click Start Simulation.
14. When the Simulator was successful message box appears, click OK.
15. Verify the simulation results in the Simulation Report window. A portion of the
vector waveform output is shown in Figure 215.
Figure 215. Design Example 2 Functional Simulation Results
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236

Timing ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the Quartus II

Software
This section describes how to verify the cii_altlvds_extpll design example you
just created via timing. It illustrates the requirement for word boundary detection
logic to be added to the design. The design example files include a simple vector
waveform created for this example. The following steps assume that you have
successfully compiled the cii_altlvds_extpll design.
1. On the Processing menu, click Generate Functional Simulation Netlist.
2. When the Functional Simulation Netlist Generation was successful message box
appears, click OK.
3. On the Assignments menu, click Settings.
4. In the Category list, select Simulator Settings.
5. In the Simulation mode list, select Timing.
6. In the Simulation input box, type cii_altlvds_extpll.vwf or click Browse
(...) to select the file in the project folder.
7. Select Run simulation until all vector stimuli are used.
8. In the Category list, select Simulation Verification.
9. Select Simulation coverage reporting and deselect Check outputs.
10. In the Category list, select Simulation Output Files.
11. Select Automatically add pins to simulation output waveforms, deselect
Overwrite simulation input file with simulation results, and deselect Generate
Signal Activity File.
12. Click OK.
13. On the Processing menu, click Start Simulation.
14. When the Simulator was successful message box appears, click OK.
15. Verify the simulation results in the Simulation Report window. A portion of the
timing vector waveform output is shown in Figure 216.
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237
Figure 216. Design Example 2 Timing Simulation Results
The receiver channels bring the serial data in to the device, edge-aligned with the
reference clock (ref_clock). The rx_in0 receives a data value of 1, the rx_in1
receives a data value of 2, rx_in2 receives a data value of 3, and the rx_in3 receives
a data value of 4. You can expand the parallel receiver channels (rx_parallel_out)
in the waveform editor to see the word alignment position. The parallel data is shifted
two bits toward the MSB in each channel.
The transmitter channel sends data from the device center aligned with the
slow_clock output pin. The tx_out0 transmits a data value of 1, the tx_out1
transmits a data value of 2, the tx_out2 transmits a data value of 3, and the tx_out3
transmits a data value of 4. Depending on your system requirements, you can add the
remaining output clock port of the PLL and forward a clock that is aligned differently
with respect to the data. The timing simulation shows the transmitted data is three bit
positions shifted toward the MSB with respect to the slow_clock.

Simulate the design in the ModelSim-Altera software to compare the results of both
simulators.
This user guide assumes that you are familiar with using the ModelSim-Altera tool
before trying out the design example. If you are unfamiliar with using the
Altera website (www.altera.com). The Support page contains various links to topics
such as installation, usage, and troubleshooting.
November 2008
Unzip the altlvds_ex2_msim.zip file to any working directory on your PC.
Start the ModelSim-Altera software.
On the File menu, click Change Directory.
Altera Corporation
238

Design Example 3: Stratix III Soft Clock Data Recovery
Select the folder in which you unzipped the files. Click OK.
On the Tools menu, point to TCL and click Execute Macro. The Execute Do File
dialog box appears.
Select the altlvds_ex2_msim.do file and click Open. This is a script file for the
Verify the results shown in the Waveform Viewer window.

With the inclusion of soft CDR circuitry for clock data recovery (CDR), Stratix III
devices offer support for the widely-used Gigabit Ethernet / SGMII protocol.
Clock-data recovery removes the clock from the clock-embedded data, a capability
required for the SGMII support. Stratix III devices support a wide array of high-speed
protocols and can be used to bridge high-speed interfaces.
This design example uses a Stratix III device to receive a single, 1-Gbps LVDS channel
using a 50-MHz reference clock to the FPGA core. This design uses an LVDS
transmitter and an LVDS receiver. The transmitter and receiver use separate PLLs. The
core clock frequency is 100 MHz. The deserialization factor in both the receiver and
the transmitter is 10. The LVDS receiver function uses soft-CDR circuitry.
The focus of this design is to illustrate the recovered clockthe clock that is recovered
and forwarded to the core by the LVDS receiver.
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239
Design Files
Verilog HDL (.v) and are included in your project directory when completed.
Example
In this example, you will complete the following tasks:
Generate a high-speed differential receiver in DPA mode and soft-CDR mode

using the ALTLVDS megafunction and the MegaWizard Plug-In Manager.

and the MegaWizard Plug-In Manager.
Implement the receiver and transmitter functions in the device by adding your
custom megafunctions to the project and compiling the project.
Simulate the high-speed differential interface design using the ModelSim-Altera

software.

1. Open the altlvds_DesignExample_ex3.zip file and extract the Quartus II archive
project altlvds_s3_serial_link.qar.
2. In the Quartus II software, open altlvds_s3_serial_link.qar and restore the archive
file into your working directory.
3. Open the top-level file altlvds_s3_serial_link.v.
4. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the
MegaWizard Plug-In Manager Page
2a
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Altera Corporation
(Part 1 of 2)

Value
Megafunction
Device family
Stratix III
Output file type
Verilog HDL
Output file name
rx_block
Return to this page for another create operation
Selected
240


3
(Part 2 of 2)

Value
Stratix III
Selected
LVDS receiver
Not selected

(receiver only)
Selected
10
Use External PLL
Not selected
What is the input data rate
1 Gbps (1,000 Mbps)
Clock frequency
Clock frequency
50 MHz
Use shared PLL(s) for receivers and transmitters Not selected
7
8
9
Not selected
Not available
Selected
What is the clock resource used for

rx_outclock?
Auto selection
Use rx_divfwdclk output port and bypass the

DPA FIFO
Selected
What is the simulated recovered clock phase

drift?
0 PPM
Not available
Not selected
Use rx_fifo_reser input port
Not available
Not selected
Not selected
Use DPA initial phase selection
Not selected
Align DPA to rising edge of data only
Not selected
Register outputs
Selected
Use rx_channel_data_align input port
Not selected
Generate netlist
Not selected
Variation file (.vhd)
Selected
Selected
Selected
Selected
Selected
Instantiation template file (_inst.vhd)
Selected
Selected
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241
8. Click Finish. The rx_block module is built.

settings shown in Table 214 .
Table 214. Configuration Settings for Design Example 3 (LVDS Transmitter) (Part 1 of 2)
2a
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Altera Corporation

Value
Megafunction
Device family
Stratix III
Output file type
Verilog HDL
Output file name
tx_block

operation
Not selected
Stratix III
Selected
LVDS transmitter
Not selected

(receiver only)
Not available
What is the deserialization factor
10
Use External PLL
Not selected
1 Gbps (1,000 Mbps)
Clock frequency
Clock frequency
50 MHz
What is the phase alignment of tx_in

with respect to the rising edge of
tx_inclock?
Not available
Not selected
Align clock to center of data window
Selected
Use shared PLL(s) for receivers and

transmitters
Not selected
Register tx_in input port using
tx_coreclock
Not selected
Selected
Not selected
Generate netlist
Not selected
242

Table 214. Configuration Settings for Design Example 3 (LVDS Transmitter) (Part 2 of 2)

7
Value
Variation file (.vhd)
Selected
Selected
Selected
Selected
Selected
Instantiation template file (_inst.vhd)
Selected
Verilog HDL black-box file (_bb.v)
Selected
11. Click Finish. The tx_block module is built.

12. On the File menu, click Save Project.
13. On the Processing menu, click Start Compilation.
14. When the Full Compilation was successful message box appears, click OK.
15. On the Tools menu, select Netlist Viewers and click RTL Viewer to view the
design schematic in the RTL Viewer.
The block diagram file should look like Figure 218.
Figure 218. Design Example 3 in RTL Viewer
16. On the Processing menu, click Compilation Report to view the resource usage of
this design.

Simulate the design in the ModelSim-Altera software to generate a waveform display
of the device behavior.
This user guide assumes that you are familiar with using the ModelSim-Altera
simulator before trying out the design example. If you are unfamiliar with using the
Altera website (www.altera.com). The Support page contains various links to topics
such as installation, usage, and troubleshooting.
1. Unzip the altlvds_ex3_msim.zip file to any working directory on your PC.
2. Start the ModelSim-Altera software.
3. On the File menu, click Change Directory.
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Conclusion
243
4. Select the folder in which you unzipped the files. Click OK.
5. On the Tools menu, point to TCL and click Execute Macro. The Execute Do File
dialog box appears.
6. Select the altlvds_ex3_msim.do file and click Open. This is a script file for the
7. Verify the results shown in the Waveform Viewer window.
This waveform file contains only the input and output pins that are shown. You can
add internal post-compilation nodes with the Node Finder to view all of the data
paths in the design, including the soft-CDR data path.
This simulation output confirms that 1-Gbps data can be successfully received using
the recovered clock from the soft CDR and then transmitted from the Stratix III
device. You can observe this by comparing the values on text_rx_in and
text_tx_out ports.
Conclusion
The Quartus II software provides parameterizable megafunctions ranging from
simple arithmetic units, such as adders and counters, to advanced PLL blocks,
multipliers, and memory structures. These megafunctions are performance-optimized
for Altera devices and therefore provide more efficient logic synthesis and device
implementation, because they automate the coding process and save valuable design
time. Altera recommends using these functions during design implementation so you
can consistently meet your design goals.
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244

Conclusion
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3. Specifications
Ports and Parameters

The Quartus II software provides the ALTLVDS megafunction that supports LVDS
transmitter and receiver functionality. This chapter describe the ports and parameters
of the ALTLVDS megafunction. These ports and parameters are available to
customize the ALTLVDS megafunction according to your application.
Enabling or disabling some parameters changes which ports are available for use in
the ALTLVDS megafunction. For example, if you enable the DPA mode for Stratix IV,
Stratix III, Stratix II, Stratix II GX, or Stratix GX devices, several different ports become
available. Some of these ports replace non-DPA ports, and some control features that
are unique to the DPA function. The following tables show all of the available ports
and parameters and which Stratix and Cyclone device families support those
features.
The parameter details are only relevant if you bypass the MegaWizard Plug-In
Manager interface and use the megafunction as a directly parameterized instantiation
in your design. The details of these parameters are hidden from you of the
MegaWizard Plug-In Manager interface.
f
For the most current information on the ports and parameters for this megafunction,
refer to the latest version of the Quartus II Help.
Table 31 shows the transmitter input ports, Table 32 shows the transmitter output
ports, and Table 33 shows the transmitter parameters. Table 34 shows the receiver
input ports, Table 35 shows the receiver output ports, and Table 36 shows the
receiver parameters.
Optional clock for the input registers. This port is available for
APEX 20KE, APEX 20KC, Mercury , and APEX II devices only.
tx_in[]
Yes
Input port
[DESERIALIZATION_FACTOR NUMBER_OF_CHANN
ELS 1..0] wide. This is parallel data that is serially
transmitted by the megafunction.
Port Name
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Altera Corporation
Cyclone III and Cyclone II
Cyclone
Stratix GX
No
Stratix
sync_inclock
Required
Stratix II, Stratix II GX, and Stratix III
Table 31. Transmitter Input Ports (Part 1 of 2)
Description
32
Chapter 3: Specifications
Port Name
Cyclone
Stratix GX
Stratix
Required
Table 31. Transmitter Input Ports (Part 2 of 2)
Description
tx_inclock
Yes
LVDS reference input clock.
tx_pll_enable
No
Enable control for the LVDS PLL. Not available in Cyclone III
device.
pll_areset
No
Asynchronously resets all PLL counters to initial values.
tx_enable
No
This port is used only when USE_EXTERNAL_PLL is

selected and must connect to the enable0 or enable1
output port of an ALTPLL megafunction configured in LVDS
mode.
The PLL must be reset in order for the output clock phase
relationships to be set correctly when the PLL loses lock or if
the PLL input reference clock is not stable when the device
completes the configuration process.
tx_syncclock
No
ALTLVDS_TX needs tx_syncclock for external PLL mode

for even deserialization factors in 8.0. This is to guarantee the
bit alignment even if the PLL loses lock.
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33
Port Name
Cyclone
Stratix GX
Stratix
Required
Table 32. Transmitter Output Ports
Description
tx_out[]
Yes
tx_outclock
No
Output port [NUMBER_OF_CHANNELS 1..0] wide.

After serialization, tx_in[n-1] is the first bit transmitted
and tx_in[0] is the last bit transmitted for channel one; for
channel two, tx_in[2n-1] is the first bit transmitted and
tx_in[n] is the last bit transmitted.
External reference clock.
Except for the following parameter configurations, every
tx_outclock now goes through the shift register logic:
tx_coreclock
No
1. When outclock_divide_by = 1 or
2. when outclock_divide_by =
DESERIALIZATION_FACTOR (for odd factors only)
and outclock_duty_cycle is 50.
Output clock used to feed non-peripheral logic.

When using the transmitter function of ALTLVDS
(ALTLVDS_TX), you may get setup timing violations when
using tx_inclock to register the data that feeds the
SERDES blocks. The ALTLVDS_TX megafunction gives you
the choice to register the tx_in data with either the
tx_inclock or the tx_coreclock. Beginning in
Quartus II version 5.1, the default setting is
tx_coreclock. Using tx_coreclock to register the
data before it feeds the SERDES is the better choice since it
will have the optimal phase position to register the data with
respect to the high speed clock that drives the SERDES.
Your setup timing violations should be eliminated when using
tx_coreclock instead of tx_inclock to register the
data in the ALTLVDS_TX function. Additionally, you should see
better timing margins when using tx_coreclock instead
of tx_inclock even if you do not have timing violations
tx_locked
No
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Altera Corporation
Gives the status of the LVDS PLL. When the PLL is locked, this
signal is VCC. When the PLL fails to lock, this signal is GND.
34
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Table 33. Transmitter Parameters (Part 1 of 5)
Description
INTENDED_DEVICE_FAMILY
Yes
[String] Select from Stratix IV, Stratix III,

Stratix II GX, Stratix II, Stratix, Stratix GX,
Cyclone III, Cyclone II, or Cyclone. The ports
and parameters that are available in the
MegaWizard Plug-In Manager change
depending on this selection, since some
features are device-dependent.
NUMBER_OF_CHANNELS
Yes
[Integer] Specifies the number of LVDS

channels.
DESERIALIZATION_FACTOR
Yes
[Integer] Specifies the number of bits per

channel. Values are:
Device Family
Values
1, 2,3,4, 5, 6, 7, 8,
Stratix IV, Stratix III,
Stratix II, Stratix II GX, 9, 10
Cyclone III,
Cyclone II, Cyclone,
HardCopy II, and
APEX II
Stratix and Stratix GX
1, 2,3,4, 7, 8, 10
APEX 20KC, APEX

20KE
1,3, 4, 7, 8
Mercury
1, 2, 3,4, 7, 8, 9,
10, 11, 12, 14, 16,
18, 20
The MegaWizard Plug-In Manager has disabled

the 50/50 duty cycle for 7, 5 and 9 mode
when divide_by_factor shown in the
wizard GUI is same as the deserialization factor.
Megafunction issues a warning and implements
the 4:3 duty cycle.
LPM_TYPE
Yes
[String] Select LVDS transmitter in the wizard

to instantiate a serializer function. For HDL
instantiation, the usage is altlvds_tx.
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35
Parameter Name
USE_EXTERNAL_PLL
No
Cyclone
Stratix GX
Stratix
Required
Description
v
[String] Values are ON or OFF. Specify ON to

prevent the ALTLVDS function from
instantiating a fast PLL automatically.
factor of two, the SERDES is bypassed and the
functionality is implemented in DDR registers.
You need at least a deserialization factor of four
to use the external PLL option.
OUTCLOCK_DIVIDE_BY
No
[Integer] Specifies the period of the

tx_outclock port as INCLOCK_PERIOD
OUTCLOCK_DIVIDE_BY and the
frequency of tx_outclock port as
INCLOCK PERIOD /
OUTCLOCK_DIVIDE_BY. The default value
for this parameter is
DESERIALIZATION_FACTOR.
So the OUTCLOCK_DUTY_CYCLE of 50 is
not supported when
DESERIALIZATION_FACTOR is 5, 7 or 9
and OUTCLOCK_DIVIDE_BY is equal to
DESERIALIZATION_FACTOR and
OUTCLOCK_MULTIPLY_BY is 2. This is for
Cyclone II/Cyclone III (always) and Stratix/II
and III when IMPLEMENT_IN_LES is ON.
CORECLOCK_DIVIDE_BY
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Altera Corporation
No
[Integer] Values are 1 or 2. Specifies the

CORECLOCK output frequency to either be
CORECLOCK or CORECLOCK divided by two.
This is only available when using odd SERDES
factors. When using a divide-by factor of 1,
fewer device resources are used, but you may
not be able to achieve timing at higher data
rates. Altera recommends using a divide by
factor of two for higher data rates.
36
Parameter Name
OUTCLOCK_ALIGNMENT
Yes
Cyclone
Stratix GX
Stratix
Required
Description
v
Refer to Figure 31.
[String] Specifies the alignment of

tx_outclock with respect to the rising edge
of tx_inclock. Figure 31 shows the
relationship between tx_inclock and
tx_outclock for three different values of
OUTCLOCK_ALIGNMENT. Values are
EDGE_ALIGNED, 45_DEGREES,
90_DEGREES, 135_DEGREES,
CENTER_ALIGNED, 235_DEGREES,
270_DEGREES, and 315_DEGREES. If
omitted, the default value is EDGE_ALIGNED.
INCLOCK_PERIOD
Yes
[Integer] Specifies the input clock either by

frequency (MHz in the wizard) or period (ps in
HDL code). This parameter is required when the
external PLL option is not used.
OUTPUT_DATA_RATE
Yes
[Integer] Specifies the data rate out of the PLL.

The multiplication value for the PLL is
OUTPUT_DATA_RATE /
INCLOCK_PERIOD.
INCLOCK_DATA_ALIGNMENT
Yes
[String] Specifies the alignment of input data

with respect to the rising edge of the
rx_inclock port. Figure 32 shows the
relationship between input data and the clock
for three different values of
INCLOCK_DATA_ALIGNMENT. Supported
values are EDGE_ALIGNED, 45_DEGREES,
omitted, the default is EDGE_ALIGNED.
Refer to Figure 32.
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37
Parameter Name
REGISTERED_INPUT
No
Cyclone
Stratix GX
Stratix
Required
Description
v
[String] Indicates whether the tx_in[]ports

should be registered and the clock that
registers the parallel data. Values are ON, OFF,
TX_INCLK, and TX_CORECLK. The default
value is OFF.
TX_INCLK must be used when the parallel
data rate is equal to TX_INCLK frequency, but
not equal to TX_CORECLOCK frequency.
TX_CORECLK must be used when the parallel
data rate is not equal to tx_inclk frequency.
When tx_inclk frequency is equal to
tx_coreclk frequency, either can be used to
register the inputs. The frequency of the
tx_coreclk is equal to
OUTPUT_DATA_RATE or
DESERIALIZATION_FACTOR.
COMMON_RX_TX_PLL
No
[String] Specifies whether the compiler may

use the same PLL for both the LVDS receiver
and the LVDS transmitter, provided they have
the same input clock frequency. Values are ON
and OFF. If omitted, the default value is ON.
OUTCLOCK_RESOURCE
No
[String] Specifies the resource used for the

output clock. Values are AUTO, GLOBAL
CLOCK, or REGIONAL CLOCK.
IMPLEMENT_IN_LES
No
[String] Specifies whether to implement

serializer/deserializer circuitry in logic cells,
which allows the circuitry to behave similar to
Stratix LVDS circuitry. The
IMPLEMENT_IN_LES parameter should be
used for SERDES functions that require data
rates that are lower than the dedicated circuitry.
Values are ON and OFF. This parameter is
available for Stratix IV, Stratix III, Stratix II,
Stratix II GX, Stratix, and Stratix GX devices
only. This parameter is always enabled for
Cyclone III, Cyclone II, and Cyclone devices
only.
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38
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
MULTI_CLOCK
No
[String] Indicates whether the

sync_inclock port is used for input
registering. Values are ON and OFF. If omitted,
the default value is OFF. This parameter is
available for APEX 20KC, APEX 20KE, Mercury,
and APEX II devices only.
INCLOCK_BOOST
No
[Integer] The effective clock period used to

sample output data. Values are 1, 2, and 4-10.
This parameter is available for APEX II and
Mercury devices only.
CENTER_ALIGN_MSB
No
[String] Indicates whether the most significant

bit center alignment is used for data bit
alignment. Values are ON and OFF. If omitted,
the default value is OFF. This parameter is
available for APEX II devices only.
OUTCLOCK_DUTY_CYCLE
No
[Integer] Duty cycle (% of the clock cycle

during which the clock signal is high) for the
external clock. A value of 50 is not supported
when all of the following conditions hold:
DESERIALIZATION_FACTOR value is 5,
7, or 9
OUTLCLOCK_DIVIDE_BY value is same

as value of
OUTCLOCK_MULTIPLY_BY value is 2
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39
Port Name
Cyclone
Stratix GX
Stratix
Required
Table 34. Receiver Input Ports (Part 1 of 3)
Description
rx_in[]
Yes
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. After deserialization, rx_out[n-1] is
the first bit received and rx_out[0] is the
last bit received for channel one; for channel
two, rx_out[2n-1] is the first bit received
and rx_out[n] is the last bit received.
rx_inclock
Yes
LVDS reference input clock.
rx_pll_enable
No
Enable control for the LVDS PLL. This port is

not available in Cyclone III.
rx_data_align
No
Controls byte alignment circuitry by delaying

the data on all channels by one bit when
asserted. You can register this port using the
rx_outclock port. For Stratix GX devices,
this port is available in non-DPA mode.
rx_data_align port (as in Stratix) for
SERDES that are implemented in LEs
supports rx_data_align port
implementation. It also has the same option to
register the rx_data_align port (as in
Stratix series devices).
The port skips a bit when it is asserted long
enough to be captured by the fast clock edge.
rx_data_align is slightly different from
the Stratix behavior in that, each pulse has to
be long enough for one slow clock cycle
(instead of two in Stratix).
rx_channel_data_align[]
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Altera Corporation
No
Input port
wide. Controls byte alignment circuitry. A
pulse to this input causes the data alignment
circuitry to remove one bit of latency from the
serial data stream in Stratix GX devices, or
add one bit of latency into the serial data
stream for Stratix IV, Stratix III, Stratix II, and
Stratix II GX devices. You can register this
port using the rx_outclock port. For
Stratix GX devices, this port is available in
DPA mode.
310
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_dpll_enable[] (1)
No
Input port
wide. Enables the path through DPA circuitry.
rx_dpll_hold[] (1)
No
Input port
wide. Prevents the DPA from switching to a
new phase.
rx_reset[] (1)
No
Input port
wide. Synchronizes all channels and resets
the DPA circuitry. This port must be
connected if the ENABLE_DPA_MODE
parameter is turned on in Stratix GX.
rx_dpll_reset[] (1)
No
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. Asynchronous reset for all channels.
rx_fifo_reset[] (1)
No
Input port
wide. Resets the FIFO between DPA and data
alignment circuits.
rx_cda_reset[]
No
Input port
wide. Resets the data alignment circuitry.
rx_coreclk[] (1)
No
Input port
wide. LVDS reference input clock used to
synchronize the output of the receiver to a
clock used in the core. One clock is used for
each channel.
pll_areset
No
Asynchronously resets all counters to initial

values.
The PLL must be reset in order for the output
clock phase relationships to be set correctly
when the PLL loses lock or if the PLL input
reference clock is not stable when the device
completes the configuration process.
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311
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_enable
No
This port is used only when

USE_EXTERNAL_PLL is selected and must
connect to the enable0 or enable1
output port of an ALTPLL megafunction
configured in LVDS mode.
rx_deskew
No
Specifies whether to activate calibration

mode. This port is available for APEX 20KE
and APEX 20KC devices only.
rx_data_align_reset
No
If enabled, creates the reset port for the

bit-slip circuitry. This port is available if the
SERDES is implemented in LEs.
rx_syncclock
No
ALTLVDS_RX needs rx_syncclock for

external PLL mode for even deserialization
factors in 8.0. This is to guarantee the bit
alignment even if the PLL loses lock.
Note to Table 34:

(1) These functions are only available when using DPA mode in Stratix III, Stratix II, Stratix II GX, and Stratix GX devices.
Port Name
Cyclone
Stratix GX
Stratix
Required
Table 35. Receiver Output Ports (Part 1 of 2)
Description
rx_out[]
Yes
Output port
[DESERIALIZATION_FACTOR NUMBER_OF_CH
ANNELS - 1..0] wide. Deserialized data signal.
rx_outclock
No
Internal reference clock.
November 2008
Altera Corporation
312
Port Name
Cyclone
Stratix GX
Stratix
Required
Table 35. Receiver Output Ports (Part 2 of 2)
Description
rx_locked
No
Provides the status of the LVDS PLL. When the PLL is

locked, this signal is VCC. When the PLL fails to lock, this
signal is GND.
rx_dpa_locked[]
No
Output port [NUMBER_OF_CHANNELS - 1..0] wide.

Indicates whether the channel is locked to the phase of
rx_in[] when in DPA mode.
Take note that RX_DPA_LOCKED may continue to toggle
when RX_DPA_HOLD is asserted. rx_dpa_Locked
will be de-asserted for at least one parallel clock cycle
rx_cda_max[]
No
Output port [NUMBER_OF_CHANNELS - 1..0] wide.

Indicates when the next
rx_channel_data_align[] pulse restores the
serial data latency back to 0.
rx_divfwdclk[]
No
Recovered clock output from the DPA block and sent to the
core via the PCLK network. The DPA output clock selected
by the DPA block is divided by the deserialization factor.
This divided clock is the recovered clock.
November 2008
Altera Corporation
313
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Table 36. Receiver Parameters (Part 1 of 7)
Description
INTENDED_DEVICE_FAMILY
Yes
[String] Select from Stratix IV, Stratix III,

Stratix II GX, Stratix II, Stratix, Stratix GX,
Cyclone III, Cyclone II, or Cyclone. The ports
and parameters that are available in the
MegaWizard Plug-In Manager change
depending on this selection, since some
features are device-dependent.
NUMBER_OF_CHANNELS
Yes
[Integer] Specifies the number of LVDS

channels.
Yes
[Integer] Specifies the number of bits per

channel.
ENABLE_DPA_MODE
No
[String] Turns on DPA mode. Values are ON

and OFF; if omitted, the default value is
OFF.
USE_EXTERNAL_PLL
No
[String] Values are ON or OFF. Specify ON

to prevent the ALTLVDS function from
instantiating a fast PLL automatically.
This option is not available when using odd
J factors in Cyclone III, Cyclone II, and
Cyclone devices.
COMMON_RX_TX_PLL
No
[String] Specifies whether the compiler may

use the same PLL for both the LVDS receiver
and the LVDS transmitter, provided they
have the same input clock frequency. Values
are ON and OFF. If omitted, the default value
is ON.
the functionality is implemented in DDR
factor of four to use the external PLL option.
OUTCLOCK_RESOURCE
No
[String] Specifies the resource used for the

output clock. Values are AUTO,GLOBAL
CLOCK, or REGIONAL CLOCK.
INCLOCK_PERIOD
Yes
[Integer] Specifies the input clock either by

frequency (MHz) or period (ns in the
MegaWizard Plug-In Manager or ps in HDL
code).
November 2008
Altera Corporation
314
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
INPUT_DATA_RATE
Yes
[Integer] Specifies the data rate into the

PLL. The multiplication value for the PLL is
INPUT_DATA_RATE /
INCLOCK_PERIOD.
INCLOCK_DATA_ALIGNMENT
Yes
[String] Specifies the alignment of input

data with respect to the rising edge of the
rx_inclock port. Values are
EDGE_ALIGNED, 45_DEGREES,
omitted, the default value is
EDGE_ALIGNED.
[String] Values are ON or OFF. Indicates

whether the DPA FIFO buffer is enabled for
this channel. If omitted, the default value is
ON.

whether the rx_coreclk port or the clock
from PLL is used as the non-peripheral
clock. The rx_coreclk port must be
connected if you turn on this parameter. If
omitted, the default value is OFF.
(1)
ENABLE_DPA_FIFO
No
v
(2)
USE_CORECLOCK_INPUT
No
v
(2)
RESET_FIFO_AT_FIRST_LOCK
No
LOSE_LOCK_ON_ONE_CHANGE
No
REGISTERED_OUTPUT
No
[String] Values are ON to automatically reset

the bit serial FIFO when rx_dpa_locked
rises for the first time or OFF to explicitly
reset the FIFO through rx_reset. Resets
the FIFO between the DPA and the
deserializer.
[String] Values are ON if phase alignment
circuitry switches to a new phase or OFF if
there are two phase changes in the same
direction. Indicates when the DPA circuit has
lost phase lock.
whether the rx_out[] port should be
registered.
November 2008
Altera Corporation
315
REGISTERED_DATA_ALIGN_
INPUT
No
DATA_ALIGN_ROLLOVER
No
[String] Values are ON or OFF. Specifies

whether the rx_data_align port is
registered, which controls the enabling of
the synchronization register in the receiver.
[Integer] Values are 1 through 11, which

indicate the number of pulses it takes for the
data alignment circuitry to restore the serial
data latency back to 0. This parameter is
only available if the
rx_channel_data_align input port
is used.
Cyclone
Parameter Name
Stratix GX
Stratix
Required
Description
(1)
The value selected should be equal to or

greater than the deserialization factor
allowing you to roll through an entire word.
By default, it is set to 4.
INCLOCK_BOOST
No
[Integer] The effective clock period used to

sample output data. Values are 1, 2, and
4-10. This parameter is available for APEX II
and Mercury devices only.
CDS_MODE
No
[String] Values are SINGLE_BIT,

MULTIPLE_BIT, and UNUSED. If omitted,
the default is UNUSED. When this parameter
is set to SINGLE_BIT, the deskew
circuitry will expect a bit pattern like
00001111, which can correct for clock
skew up to 50% of one clock edge. When
this parameter is set to MULTIPLE_BIT,
the deskew circuitry will expect a pattern like
01010101, which can correct for any clock
skew but requires user circuitry to align
data. This parameter is available for APEX II
devices only.
November 2008
Altera Corporation
316
[String] Specifies whether to implement

serializer/deserializer circuitry in logic cells,
which allows the circuitry to behave similar
to Stratix LVDS circuitry. The
IMPLEMENT_IN_LES parameter should be
used for SERDES functions that require data
rates that are lower than the dedicated
circuitry. Values are ON and OFF. This
parameter is available for Stratix IV,
Stratix III, Stratix II, Stratix, and Stratix GX
devices only.
BUFFER_IMPLEMENTATION
No
[String] Specifies where to implement the

buffer.
Parameter Name
Cyclone
Stratix GX
No
Stratix
IMPLEMENT_IN_LES
Required
Description
BUFFER_IMPLEMENTATION applies
only to Cyclone III, Cyclone II, and Cyclone,
and Stratix IV, Stratix III, Stratix II, and
Stratix (LE implementations only for Stratix
series) for Odd deserialization factors.
To use the BUFFER_IMPLEMENTATION
parameter, the IMPLEMENT_IN_LES
parameter must be turned on. Also, the
BUFFER_IMPLEMENTATION parameter can
be used with deserialization factors of 5, 7,
or 9 only.
Values are:
Parameter Value: MUX
Description: Uses mux implementation
instead of buffer implementation.
Parameter Value: RAM
Description: Buffer is implemented in RAM
blocks.
Parameter Value: LES
Description: Buffer is implemented in logic
elements.
If omitted, the default value is RAM.
ENABLE_SOFT_CDR
No
Enables soft-CDR mode. Applies to

Stratix IV and Stratix III devices only.
November 2008
Altera Corporation
317
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
IS_NEGATIVE_PPM_DRIFT
No
Simulation-only parameter. Determines

whether the PPM drift of the recovered clock
is negative (receiver is faster than
transmitter) or positive (transmitter is faster
than receiver). Applies to Stratix IV and
Stratix III devices only.
NET_PPM_VARIATION
No
Simulation-only parameter. User-specified

PPM drift for the recovered clock. Applies to
ENABLE_DPA_INITIAL_PHASE
_SELECTION
No
Enables the user-specified initial DPA phase

setting. Applies to Stratix IV and Stratix III
devices only.
DPA_INITIAL_PHASE_
VALUE
No
User-specified choice of the initial DPA

phase (out of 8 possible DPA phases).
Available phases are 0, 45, 90, 135, 180,
225, 270, and 315. Applies to Stratix IV and
ENABLE_DPA_ALIGN_TO_
RISING_EDGE_ONLY
No
If TRUE, DPA clock aligns to rising edge of

data only. If FALSE, DPA clock aligns to
both rising and falling data edges. Default
value is FALSE. Applies to Stratix IV and
November 2008
Altera Corporation
318
Parameter Name
PLL_OPERATION_MODE
No
Cyclone
Stratix GX
Stratix
Required
Description
PLL_OPERATION_MODE has choices

being NORMAL and
SOURCE_SYNCHRONOUS. NORMAL is the
default. The parameter is used only for
Cyclone II, Cyclone III and Stratix II,
Stratix III, and Stratix IV LE version cases.If
enabled, the phase relationship between
data and clock at the pin is maintained at the
data-capture point.
Selecting this option forces the
megafunction instantiation to make the
required phase adjustments to guarantee a
consistent relationship between the clock
and data at the capture register and at the
pin. This option should always be selected,
unless you have already performed all of the
necessary phase adjustments manually.
Altera recommends that you enable this
option when using flexible LVDS schemes.
This option is available only if the SERDES is
implemented in LEs.
November 2008
Altera Corporation
319
Parameter Name
USE_NO_PHASE_SHIFT
No
Cyclone
Stratix GX
Stratix
Required
Description
This parameter has values ON and OFF.

Defaults to ON. The parameter is useful only
in SOURCE_SYNCHRONOUS mode of the
PLL for Cyclone II and Stratix II LE version.
When USE_NO_PHASE_SHIFT is OFF,
the megafunction adds a phase shift of 90
to the clock (in other words, subtracts it
from the clock a la Stratix II), so that clock is
centered in the data.When enabled, a phase
shift of 90 is added to the clock to center
the clock in the data. This option is available
only for Arria GX, Stratix II GX, Stratix II,
and HardCopy II devices when SERDES is
implemented in logic cells, and for
Cyclone II devices.
For Cyclone III devices, Stratix IV, and
Stratix III (LE Implementation) devices, this
option is not available.
Notes to Table 36:

(1) This parameter is not available for Stratix IV, Stratix III, Stratix II, and Stratix GX devices when using DPA mode.
(2) This parameter is available only for Stratix IV, Stratix III, Stratix II, and Stratix GX devices when using DPA mode.
November 2008
Altera Corporation
320
Figure 31. OUTCLOCK_ALIGNMENT

Edge
180
Reference Edge
tx_inclock
tx_outclock
tx_outclock
tx_outclock
Figure 32. INCLOCK_DATA_ALIGNMENT

Edge
180
Input Clock
Edge Aligned
45 Phase
180o Phase
November 2008
Altera Corporation
Additional Information
UG-MF9504-4.0
Revision History
The following table shows the revision history for this user guide.
Date
Version
December 2008
v4.0
Changes Made
Updated for the Quartus II software 8.1:
Removed figures.
Added Stratix IV to Device Family Support
Updated Table 21, Table 22, Table 23, Table 24, Table 25, Table 27, Table 29,
Table 211, Table 212, Table 31, Table 32, Table 33,Table 34, and Table 36.
Added Enable bitslip control, Enable independent bitslip controls for each channel, and
Register the bitslip control input using 'rx_outclock' parameters and descriptions to
Table 28
Updated steps in Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design

in the ModelSim-Altera Simulator, Functional ResultsSimulate the ALTLVDS
Receiver/Transmitter Design in the Quartus II Software,Functional ResultsSimulate the
ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Simulator, Functional
ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera
Simulator.
Added tx_syncclock and descriptions in Table 31
Added rx_data_align and rx_syncclock in Table 34
Updated descriptions in Table 36
May 2008
v3.4
Small changes to Table 27 on page 227 and Table 29 on page 232.
November 2007
v3.3
Updated for the Quartus II software v7.2, including:
Added soft-CDR mode.
Added description of new receiver output port rx_divfwdclk[].
Added description of new receiver parameters ENABLE_SOFT_CDR,

IS_NEGATIVE_PPM_DRIFT,NET_PPM_VARIATION,
ENABLE_DPA_ALIGN_TO_ RISING_EDGE_ONLY,
DPA_INITIAL_PHASE_ VALUE, and ENABLE_DPA_INITIAL_PHASE

_SELECTION.
Updated two design examples.
Added third design example using soft-CDR mode.
March 2007
v3.2
Updated for Quartus II software 7.0, including Cyclone III information.
December 2006
v3.1
Updated Table 1-1 to include Stratix III information.
November 2006
v3.0
Updated for the Quartus II software 6.1.
June 2006
v2.0
Updated for the Quartus II software 6.0.
August 2005
v1.1
Minor content changes.
December 2004
v1.0
Initial release.
December 2008
Altera Corporation
About2
Referenced Documents
Referenced Documents
This user guide references the following documents:
ALTPLL Megafunction User Guide
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices
AN 409: Design Example Using the ALTLVDS Megafunction & the External PLL Option
in Stratix II Devices
Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III
Device Handbook
Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in

volume 3 of the Quartus II Handbook
Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook
Simulation section in volume 3 of the Quartus II Handbook
Synthesis section in volume 1 of the Quartus II Handbook
How to Contact Altera

For the most up-to-date information about Altera products, see the following table.
Contact (Note 1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
custrain@altera.com
Altera literature services
Email
literature@altera.com
Non-technical support (General)
Email
nacomp@altera.com
(Software Licensing)
Email
authorization@altera.com
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue
Meaning
Bold Type with Initial Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names, file
names, file name extensions, and software utility names are shown in bold type.
Examples: fMAX , \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
December 2008
Altera Corporation
About3
Typographic Conventions
Visual Cue
Italic type
Meaning
Internal timing parameters and variables are shown in italic type.
Examples: tPIA , n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
Subheading Title
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: Typographic Conventions.
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1 , tdi ,
input. Active-low signals are denoted by suffix n , e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file,
such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN ), as well as logic function names (e.g., TRI ) are shown in Courier.
1., 2., 3., and

a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
A caution calls attention to a condition or possible situation that can damage or

destroy the product or the users work.
A warning calls attention to a condition or possible situation that can cause injury to
the user.
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December 2008
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SERDES Transmitter/Receiver (ALTLVDS)

Megafunction User Guide

101 Innovation Drive

Chapter 1. About This Megafunction

Chapter 2. Getting Started

November 2008 Altera Corporation

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Design Example 3: Stratix III Soft Clock Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

November 2008 Altera Corporation

1. About This Megafunction

Device Family Support

Parameterizable data channel widths.

Parameterizable serializer/deserializer (SERDES) factors.

Registered inputs and outputs.

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 1: About This Megafunction

PLL control signals.

Flexibility to implement in dedicated circuitry or in logic cells. This varies

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 1: About This Megafunction

Soft CDR Mode

Soft CDR Recovered Clock Simulation

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 1: About This Megafunction

Resource Utilization and Performance

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 1: About This Megafunction

Slow Clock (outclock)

Slow Clock (outclock)

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 1: About This Megafunction

Software and System Requirements

MegaWizard Plug-In Manager Customization

On the Tools menu, click MegaWizard Plug-In Manager.

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 2: Getting Started

MegaWizard Plug-In Manager Page Options and Descriptions

MegaWizard Plug-In Manager Pages for the LVDS Transmitter

LVDS Transmitter Using a Dedicated SERDES Block or SERDES in LEs

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 2: Getting Started

If not enabled, the megafunction takes

If enabled, the transmitter starts its

What is the number of channels?

Number of output channels available for

For example, if the number of channels is

What is the deserialization factor? This value determines the number of

Altera recommends you to use the

For further details, refer to the I/O Buffer

For example, if the deserialization factor is

Use External PLL

This determines whether to use an

If not enabled, the next page displays the

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

Chapter 2: Getting Started

Specify the input clock rate by

The value specifies the data rate

This value determines the allowed input clock rate

The value specifies the

tx_inclock frequency to the

internal PLL. The allowed values