K. N.

Toosi University of Technology

Digital Electronics
Chapter 8. NMOS Logic
By:
B
y: FARHAD
FARHAD FARADJI,
FA
ARA
ADJI, Ph.D.
Ph.D.
Assistant Professor,,
Electrical and Computer Engineering,
Engineering
K. N. Toosi University of Technology
http://wp.kntu.ac.ir/faradji/DigitalElectronics.htm
Reference:
DIGITAL INTEGRATED CIRCUITS: ANALYSIS and DESIGN, 2005,
John E. Ayers
1

8.1. Introduction

KNTU

NMOS logic circuits use only n-channel MOSFETs.

Because of small size of MOSFETs, NMOS ICs can be made with highest
possible packing density.
Only disadvantage of NMOS is high standby power, which can be
comparable to
o that for bipolar circuits.
CMOS has replaced
NMOS
placed
dN
MOSS in most
mostt of
of applications
application
ns today.
tod
day.

Digital Electronics

Chapter 8. NMOS Logic

8.2. Circuit Evolution

KNTU

Simplest NMOS circuit has an NMOS switch and

a resistor as pull-up device.
Other circuit designs use pull-up transistors
for improved circuit density.
An NMOS inverter
pull-up
erter with an R pull
up is essentially
a MOSFET common
overdriven
mmon source amplifier
amp
plifiier ov
verrdriven
between cutoff
off and
an
nd ohmic
ohmic operation.
operation.
With a logic-zero
zero
o input:
in
n p u t:
MOSFET iss cut off.
off
Output rises to VDD.
With a logic-one input:
MOSFET is driven to ohmic (linear) operation.
Output voltage is less than VT for switch MOSFETs in next stage.

Digital Electronics

Chapter 8. NMOS Logic

8.2. Circuit Evolution

KNTU

Primary disadvantage is low packing density.

Typically, resistors take up far more chip area
than switch transistors.
Packing density can be greatly improved by replacing
pull-up resistor
or with a MOSFET.
If pull-up is an
enhancement
device,
n enhan
nceme
ent ttype
ype de
evice,
switch
witch
h ttransistors.
ranssistors.
riccated w
ith ssame
ame VT ass sw
it may be fabricated
with
e type
tyype of
of transistor
traansistor minimizes
minimizes
Using a single
b i i process steps and
d cost.
number of fabrication
A disadvantage relative to resistor pull-up is
reduced voltage swing.
Maximum output voltage is VDD - VT
rather than VDD.
Digital Electronics

Chapter 8. NMOS Logic

8.2. Circuit Evolution

KNTU

9 An improved NMOS circuit uses a depletion type

pull-up transistor to achieve:
High packing density,
Maximum voltage swing.

Digital Electronics

Chapter 8. NMOS Logic

8.3. Voltage Transfer Characteristic

KNTU

With a logic-zero input:

For switch transistor (MNO):
VGSO = 0 < VT
MNO is cut off.
IDO = 0
(MNNLL):
For load device (M
VGSL = 0 > VP = VT
MNL iss no
not
ot ccut
ut o
off.
ff.
IDO = 0.
IDL = 0.
MNL is in ohmic region.
VDSL = 0.

Digital Electronics

Chapter 8. NMOS Logic

8.3. Voltage Transfer Characteristic

KNTU

With a logic-one input:

For switch transistor (MNO):
VGSO = VDD > VT : MNO is not cut off.
IDO can be nonzero if there is a path.
VGDO = VDD - (VDD - VDSL) = VDSL > VT
MNO iss linear (in ohmic region).
devicce (M
(MNNLL))::
For load device
-||VP||== VP = VT : MNL is n
not
ot cut
cut off.
offf.
VGSL = 0 > -|V
n be
be nonzero
no
onzero iiff tthere
heree iss a path.
path.
IDL can
0
There is a path for IDO and IDL : IDO = IDL 0.
VGDL = VSDL= -VDSL < -|VP|= VP = VT
MNL is saturated.

Digital Electronics

Chapter 8. NMOS Logic

8.3. Voltage Transfer Characteristic

KNTU

With a logic-one input:

MNO is linear.
MNL is saturated.
IDO = IDL:

Digital Electronics

Chapter 8. NMOS Logic

8.3. Voltage Transfer Characteristic

KNTU

9 With a logic-one input:

MNO is linear.
MNL is saturated.
IDO = IDL:

fo
orm
mula pr
redicts 2 solutions.
solutio
ons.
Quadraticc formula
predicts
Solution with plus sign is nonphysical and must be discarded.
VOL depends on ratio of device transconductance parameters but not
their absolute values.
Both devices can be scaled up or down in size without affecting VOL.

Digital Electronics

Chapter 8. NMOS Logic

8.3. Voltage Transfer Characteristic

KNTU

At input low voltage:

MNO is saturated.
MNL is linear.
IDO = IDL:

Digital Electronics

Chapter 8. NMOS Logic

10

8.3. Voltage Transfer Characteristic

KNTU

At input high voltage:

MNO is linear.
MNL is saturated.
IDO = IDL:

Digital Electronics

Chapter 8. NMOS Logic

11

8.3. Voltage Transfer Characteristic

KNTU

VTC may be determined point by point by

equating ID of transistors and solving for VOUT.
This requires knowledge of operating modes
for transistors at each point.
This can be determined
etermined with rules of Table 8.2.
0.5
.5
5 V::
9 For VIN VTO = 0
offf.
MNO is cutt off.
MNL is linear.

Digital Electronics

Chapter 8. NMOS Logic

12

8.3. Voltage Transfer Characteristic

KNTU

9 For 0.5 V VIN VOUT + 0.5 V and VOUT s:

MNO is saturated.
MNL is linear.

Digital Electronics

Chapter 8. NMOS Logic

13

8.3. Voltage Transfer Characteristic

KNTU

9 For VIN VOUT + 0.5 V and VOUT s:

MNO is linear.
MNL is saturated.

Digital Electronics

Chapter 8. NMOS Logic

14

8.3. Voltage Transfer Characteristic

Digital Electronics

Chapter 8. NMOS Logic

KNTU

15

8.3. Voltage Transfer Characteristic

Digital Electronics

Chapter 8. NMOS Logic

KNTU

16

Dissipation

KNTU

2 contributions to dissipation in an NMOS gate are:

DC (static) and
AC (dynamic) components.
Usually, static dissipation dominates in NMOS logic, but this depends on
switching frequency.
que cy.
Dissipation should
hould bee minimized
min
nimizzed to:
to:
extend battery
atttery life
liife aand
nd
simplify chip
hip
p ccooling
ooling requirements.
requirements.
There is always a trade-off between speed and power.

Digital Electronics

Chapter 8. NMOS Logic

17

Dissipation

KNTU

DC or static dissipation depends on output state of gate.

Consider depletion load NMOS inverter with output high.
Input is grounded.
one output:
With a logic-one
Switch transistor
anssissto
or is
is cut
cut off.
off.
Supply current
rrent (I
(IDDDH
approximately
pproximatelyy 0.
DH) is ap
Neglectingg small leakage current.
current

Digital Electronics

Chapter 8. NMOS Logic

18

Dissipation

KNTU

With a logic-zero output:

Switch transistor is linear.
Load transistor is saturated.

Average static dissipation depends on output duty cycle.

It is common practice to assume a 50% duty cycle:

Digital Electronics

Chapter 8. NMOS Logic

19

Dissipation

KNTU

9 DC dissipation can be reduced by:

a reduction of supply voltage or
by scaling down K values.
9 KO does not appear explicitly in power equation.
9 2 K values aree scaled up or down together to preserve
VTC.
prese
erve
e desired
des
9 Scaling down K va
values
alues degrades
degrades switching
switching speed
speed
d unless
unle
ess load
lo capacitances
siimilarrly.
can be scaled similarly.

Digital Electronics

Chapter 8. NMOS Logic

20

Dissipation

KNTU

AC or dynamic dissipation is associated

with output switching.
Consider NMOS inverter with a lumped capacitive load.
A switching cycle is a low-to-high transition at output,
followed by a high
high-to-low
to low transition at output.
Energy associated
with
ated w
ith 1 sswitching
witcching ccycle
ycle is:
iss:

If current that flows in MNO during low-to-high transition is neglected:

Digital Electronics

Chapter 8. NMOS Logic

21

Dissipation

KNTU

9 f is switching frequency.
fre
eque
ency.
9 fCLK is clock frequency.
equency.
9 is switching activity: (<1)
9 Actual switching frequency for any particular gate will be less than fCLK .
Overall dissipation is:

Digital Electronics

Chapter 8. NMOS Logic

22

8.5. Propagation Delays

KNTU

Real loads involve distributed C, R, and L.

Lumped capacitive load is an approximation.
tPLH:
9 Assume that fall time at input is negligible.
9 At t = 0, inputt voltage decreases
abruptly
decreasees abrup
ptlyy
to cut off MNOO.
ted and drain current is:
9 MNL is saturated

9 VOUT reaches VDD/2 at t = tPLH:

Digital Electronics

Chapter 8. NMOS Logic

23

8.5. Propagation Delays

KNTU

tPHL:
Assume that rise time at input is negligible.
At t = 0+:
MNO will be saturated.
MNL will be linear.
rentss aare:
re:
Drain currents

IDL depends on VOUT2, resulting in a nonlinear differential equation.

Analysis can be greatly simplified by neglecting IDL.
Very little accuracy is lost:

Digital Electronics

Chapter 8. NMOS Logic

24

8.5. Propagation Delays

KNTU

9 tPLH is:
proportional to CL ,
inversely proportional to current driving
capability of MNL.

9 tPHL is:
directly proportional to CL,
inversely proportional to current driving capability of MNO.
As a first approximation, is also inversely proportional to VDD.

Digital Electronics

Chapter 8. NMOS Logic

25

8.6. Logic Design

KNTU

NMOS NOR gates are realized by placing switch transistors in parallel.

If voltage representing logic 1
is applied to any input:
associated switch MOSFET operates
in linear region,
output will
ill go low.
If logic 0 is applied
pliied to
to all
alll inputs:
inputs:
all switch transistors
traansiistors operate
operate in
in cutoff
cuto
off region,
region,
output will
ill go high.
hi h

Digital Electronics

Chapter 8. NMOS Logic

26

8.6. Logic Design

KNTU

NMOS NAND gates are made by putting switch transistors in series.

If voltage representing logic 0
is applied to any input:
output will go high.
If logic 1 is applied
plied to all inputs:
ill go low.
lo
ow.
output will

Digital Electronics

Chapter 8. NMOS Logic

27

8.6. Logic Design

KNTU

XOR function can be implemented in NMOS.

If VINB is logic 1, but VINA is logic 0:
MNXB is linear
MNXB brings voltage low at gate of MNOI.
With MNOI
OI cut off, output goes high.
but
ut VIN
s log
logic
gic 1:
1:
If VINB is logic 0, bu
INA
NA is
neaar.
MNXA is linear.
gs voltage
volttage lo
low
ow at
at gate
gatte o
off MNNOI
MNXA brings
OI.
off output goes high
high.
With MNOI cut off,
If inputs are same (both logic 0 or both logic 1):
MNXA and MNXB are cut off.
Voltage at gate of MNOI goes high.
Output voltage goes low.

Digital Electronics

Chapter 8. NMOS Logic

28

8.6. Logic Design

KNTU

9 ANDORINVERT gates can be implemented by parallel connection of

series combinations of switch transistors.

Digital Electronics

Chapter 8. NMOS Logic

29

8.6. Logic Design

KNTU

More complex logic functions can be realized by combining parallel and

series branches of switch transistors.

Digital Electronics

Chapter 8. NMOS Logic

30