Plessey LinearIntegratedCircuitHandbook Text

LINEAR
INTEGRATED
n
CIRCUIT
HANDBOOK
PLESSEY
W Semiconductors
LINEAR
INTEGRATED
CIRCUIT
HANDBOOK
PLESSEY
V Semiconductors
'yiA/wwi/|
Designed and produced by Peter Wigens Consultants
The
Plessey
Company
pic
March 1983
Publication No. P.S. 1973
This publication is issued to provide outline information only and (unless

specifically agreed to
the contrary by the Company in writing) is not to form part of any order
or contract or be
regarded as a representation relating to the products or services concerned. We
reserve the right
to alter without notice the specification, design, price or conditions
of supply of any product or
The name Plessey and the Plessey logo are
registered trademarks of
The Plessey Company pic.
Contents
Page
Product index
Product list
Quality data
Ordering information
Screening to MIL-STD-883
Semi-custom
Technical data
Package outlines
Plessey Semiconductors World Wide
5
8
10
11
13
14
17
193
203
Product index
Page
OPERATIONAL AMPLIFIERS
SL541B
TAB1042
TAB1043
81
High slew rate operational amplifier
Quad programmable operational

Quad programmable operational
185
189
amplifier
amplifier
LINEAR RF AMPLIFIERS
SL541B
Low noise wideband amplifier with external
SL550D & G
low noise amplifier
300MHz
SL560C
SL561B,C
Ultra low noise preamplifiers
PHASE LOCKED LOOP CIRCUITS

Modulator/phase
SL650B C
SL651B,C
SL652C
locked loop circuits for

Modulator/phase locked loop circuits for
Modulator/phase locked loop
LIMITING WIDEBAND AMPLIFIERS

140MHz wideband log amplifier
SL521A,B & C
120MHz dual wideband log amplifier
SL523B,C & HB
Wideband log IF strip amplifier
SL525C
SL531C
SL532C
SL565C
SL1521A,C
SL1523C
81
gain control
250MHz true log IF amplifier

Low phase shift limiter
1GHz wideband amplifier
300MHz wideband amplifier
300MHz dual wideband amplifier
modems
modems
85
91
95
115
115
119
63
67
71
75
79
99
129
133
MATCHED TRANSISTOR AND ARRAYS

SL301KX
SL360C,G
SL362C
SL2363C
SL2364C
SL3045C
SL3046C
SL3127C
SL3145C.E
Dual NPN transistors

High performance NPN dual transistor arrays
High performance NPN dual transistor arrays
Very high performance transistor array
General purpose NPN transistor array
High frequency NPN transistor array
1.2GHz high frequency NPN transistor arrays
19
27
27
145
145
147
147
149
153
RADIO-COMMUNICATIONS
SL610C
SL611C
SL612C
SL621C
SL623C
SL640C
SL641C
SL1613C
SL1621C
SL6270C
SL6310C
SL6601C
SL6440A.C
SL6691C
SL6700A
SL6700C
RF
RF
amplifier
103
103
103
107
amplifier
IF amplifier
AGC generator
AM detector/AGC amplifier/SSB
demodulator
111
Double balanced modulators

Wideband
AGC
113
113
137
log IF strip amplifier
generator
141
Gain controlled preamplifier

Switchable audio amplifier
Low power IF/AF PLL circuit for narrow band
High level mixer
Monolithic circuit for paging receivers
IF amplifier
IF amplifier
and
and
AM
AM
detector
detector
157
161
FM
169
165
173
177
181
POWER CONTROL CIRCUITS

SL440
Power
SL441A
SL441C
SL443A
SL445A
SL446A
Zero
Zero
Zero
Zero
Zero
control circuit
voltage switch
voltage switch
voltage switch
voltage switch
voltage switch
29
33
37
41
5
55
Product
SL301K
SL301L
SL303L
SL360CG
SL362C
SL440
SL441A
SL441C
SL443A
SL445A
SL446A
SL521A,B & C
SL523B.C & HB
SL525C
SL531C
SL532C
SL541B
SL550D & G
SL560C
SL561B,C
SL565C
SL610C
SL611C
SL612C
SL621C
SL623C
SL640C
SL641C
SL650B,C
SL651B,C
SL652C
SL1521A,C
SL1523C
SL1613C
SL1621C
Dual
Dual
list
Page
NPN
NPN
400MHz
transistors
transistors
tripple
NPN transistors
NPN dual transistor
NPN dual transistor
High performance
High performance
Power
Zero
Zero
Zero
Zero
Zero
arrays
arrays
control circuit
voltage switch
33
37
voltage switch
voltage switch
41
voltage switch
voltage switch
140MHz wideband log amplifier

120MHz dual wideband log amplifier
Wideband
19
19
23
27
27
29
250MHz true log IF amplifier

Low phase shift limiter
45
55
63
67
71
75
79
81
Low noise wideband amplifier

300MHz low noise amplifier
91
Ultra
1
low noise preamplifiers
GHz wideband
RF
RF
with external gain control
amplifier
amplifier
amplifier
IF amplifier
AGC generator
AM detector/AGC
amplifier/SSB demodulator
Modulator/phase locked loop circuits for modems
Modulator/phase locked loop circuits for modems
Modulator/phase locked loop
300MHz wideband amplifier
300MHz dual wideband amplifier
Wideband
AGC
generator
85
95
99
103
103
103
107
111
113
113
115
115
119
129
133
137
141
SL2363C
SL2364C
SL3045C
SL3046C
SL3127C
SL3145C,E
SL6270C
SL6310C
SL6440A,C
SL6601C
SL6691C
SL6700A
SL6700C
TAB1042
TAB1043

High frequency NPN transistor array
1 .2GHz high frequency NPN transistor arrays
Gain controlled preamplifier
Switchable audio amplifier
High level mixer
Low power IF/AF PLL circuit for narrow band
Monolithic circuit for paging receivers
145
145
147
147
149
153
157
161
IF amplifier
165
169
173
177
IF amplifier
181
and AM detector
and AM detector
Quad programmable operational amplifier
Quad programmable operational amplifier
FM
185
189
Quality data
Plessey Semiconductors has Factory Approval to:BS9300 for semiconductor devices of Assessed Quality (BSI Certificate
1053/M)
BS9400
for integrated circuits of Assessed Quality (BSI Certificate

1053/M)
CECC 50000 Inspection Organisation to document level 1 (BS9300)
M0020/CECC
DEF STAN 05
AQAP
refers
21 QC System requirements for Industry (Equivalent to
1) Certificate 65752/1/01
refers
Devices are also manufactured and tested in accordance with the methods of MILSTD-833, the US Military Standard; Test Methods and Procedures for Microcircuits,
and MIL-M-38510, US Military Specification, Micro-electronics; General
Specifications
10
for.
Ordering information
Plessey Semiconductors integrated circuits are allocated type numbers which
must be quoted when ordering. This number may or may not have a suffix (A, B, C,
etc.) which denotes the precise electrical specification or temperature grade. When
there is a choice of packages the two-digit Pro-Electron code is used to identify the
All
style required, according to the following table:
CM -
Multilead
DC DG GC -
Ceramic Dual-in-Line (metal

Ceramic Dual-in-Line
Ceramic Chip Cover
TO-5
lid)
Within the UK, orders for quantities up to 99 will be referred to your local Distributor.
Quantities of 1000 and over must be ordered from:
Plessey Semiconductors Limited
Cheney Manor
Swindon, Wiltshire
SN2 2QW
United Kingdom
Telephone: Swindon (0793) 36251
Telex: 449637
reciprocal arrangement exists with all Distributors, but it will expedite delivery of
the UK, irrespective of
if buyers can direct orders as indicated above. Outside
order
you are invited to contact your nearest Plessey Semiconductors Sales

Outlet (see pages 203-207).
quantity,
11
DELIVERED PRODUCT QUALITY

our policy to deliver a
product and to achieve this end all devices

every relevant AC and DC parameter prior to
shipment. The devices are tested under conditions of level and frequency closely
simulating those of the typical application. Fully automatic Teradyne integrated
circuit test machines, acknowledged to be among the best computer controlled test
It
is
undergo 100%
machines
reliable quality
electrical testing of
available, are
employed.
Each and every stage of processing, assembly and testing is carefully audited by
Plessey Semiconductors' independent Quality Assurance department.
Therefore
all
we are able to guarantee the following Acceptable Quality Level
(A.Q.L.)
on
deliveries.
MECHANICAL
Defects of a mechanical nature including coding not being legible, deformed leads,
dimensional tolerances being exceeded, wrong identification of pin 1 and pins not
being solderable.
0.65% AQL.I.LII
ELECTRICAL
Defects of an electrical nature including device parameters being outside the
acceptance specification limits, or those only stated as typical being grossly in error.
0.4% AQL.I.LII
The average delivered product
of imperfect devices being
12
is considerably better than this, the population

smaller than that indicated by the AQL values.
quality
much
Screening to MIL-STD-883
The
following Screening Procedures are available from Plessey Semiconductors
CLASS
CLASS
PRE CAP
PRE CAP
VISUAL
VISUAL
* STANDARD
PRODUCTS
PRE CAP
VISUAL
STABILIZATION
STABILIZATION
BAKE
BAKE
TEMPERATURE
TEMPERATURE
CYCLING
CYCLING
CENTRIFUGE
CENTRIFUGE
VISUAL
INSPECTION
VISUAL
INSPECTION
VISUAL
INSPECTION
HERMETICITY
HERMETICITY
HERMETICITY
(SAMPLE)
P.I.N. D.
SERIALIZATION
RADIOGRAPHIC
INTERIM
INTERIM
ELECTRICAL TEST
ELECTRICAL TEST
BURN-IN
BURN-IN
FINAL
FINAL
FINAL
ELECTRICAL TEST
ELECTRICAL TEST
ELECTRICAL TEST
QUALIFICATION
OR CONFORMANCE
TESTING AS REQUIRED
Screening Procedure for Standard

'Plessey Semiconductors reserve the right to change the
Products.
13
Semi-custom design
The table outlines the essential parameters of our Semi-custom design
techniques, including typical timescales for the design and production of a
Semi-custom
IC.
NAME
PART
LOGIC
ELEMENTS
TECHNOLOGY
NUMBER
NMOS
MJ 1XXX
Up
to 3000
equiv.gates
(Std)
Microcell
Microgate-C
1000 Series
(CMOS Gate Array)
NMOS
MJ 1XXX
Up
to
3000
SYSTEM
TYP.GATE
DELAY/POWER
SPEED
2MHz
50ns at
250a/W
200ns
CLOCK
2MHz
at
(low power)
equiv.gates
4QuW
MV 1XXX
CMOS
Up to 2000
equiv.gates
20ns at
12a/W/MHz
8MHz
CLA 10XX
CMOS
560
6ns at
6*/W/MHz
8MHz
CLA 12XX
CMOS
960
6ns
8MHz
at
6*/W/MHz
CMOS
CLA 15XX
1440
6ns
8MHz
at
QuW/MHz
CLA
CMOS
21 XX
840
4ns
14MHz
at
tyW/MHz
Microgate-C
2000 Series
(CMOS Gate Array)
Microgate-E
(ECL Gate
CMOS
CLA 23XX
1440
4ns
CLA 25XX
CMOS
SCD 1XXX
SCD 2XXXH
SCD 2XXXM
SCD 2XXXL
PART
NUMBER
14MHz
2400
4ns at
3//W/MHZ
ECL
75
550ps/900mW
300MHz
ECL
300
550ps/3.5W
300MHz
ECL
300
1.5ns/1W
250MHz
ECL
300
2ns/750mW
100MHz
Array)
NAME
14MHz
at
3*/W/MHz
COMPONENT COUNT
TECHNOLOGY
TRANSISTORS
PNP
RESISTANCE
NPN
MicroNn
(Analogue Array)
BAA1XXX
BAA2XXX
'Design and test times given are

circuit.
14
typical.
Bipolar
1219kO
81
28
Bipolar
2757kO
163
58
Actual times
will
depend on the complexity
of the particular
INPUT/
COMPATI-
MAX.
OF
No.
BILITY
COUNT
CUSTOM
MASKS
required
TTL/CMOS
64
As required
TTL/CMOS
64
As
TTL/CMOS
64
38lorO
TTL/CMOS
40
50lorO
TTL/CMOS
64
60lorO
TTL/CMOS
64
40lorO
TTL/CMOS
44
OUTPUT
ELEMENTS
As
required
52
60
25
PIN
or
TTL/CMOS
56
or
TTL/CMOS
64
or
ECL 10K
28
ECL 10K
64
ECL 10K
64
ECL 10K
64
361
TYPICAL TIME
FOR
1st
SAMPLES
19 weeks*
16 weeks*
13 weeks*
20lorO
361
16 weeks*
20lorO
361
20lorO
It
(1mA 5V Vcc)
STANDARD NPN
LVcco/
BVcco
MAX.
OF
No.
COUNT
CUSTOM
MASKS
PIN
470MHz
20V/30V
24
470MHz
20V/30V
24
TYPICAL TIME
FOR
1st
SAMPLES
15 weeks*
15
16
Technical Data
17
18
SL301K/SL301L
^^P' Semiconductors
SL301K, SL301L
400MHz DUAL NPN TRANSISTOR
The SL301K and SL301L are
dual
monolithic
NPN
transistors with close parameter matching and high ft. The

SL301K and SL301L have identical electrical specification.
FEATURES
Close
Vbe MatchingOmV
Closehfe Matching>0.9
CM8
Good Frequency Response>400MHz

Good Thermal Tracking
Wide Operating Current Range
APPLICATIONS
Differential Amplifier to
Very High Frequencies
Comparators
Current Sources
Instrumentation
CM8
SL301K
ABSOLUTE MAXIMUM RATINGS
Fig.1 Pin
connections
apply to individual transistors.

Thermal ratings apply to the total package.
All electrical ratings
The absolute maximum ratings are limiting values above

which operating life may be shortened or specified parameters may be degraded.
The isolation pin (substrate) must be connected to the
most negative point of the circuit to maintain electrical
isolation between transistors.
Storage temperature -55 C to +175C (CM8)
Maximum junction temperature +175 C
Thermal resistance: see Note 1
Chip-to-case 265 C/W (CM8)
Chip-to-ambient 425 C/W (CM8)
Vcb = 20V Veb = 4.0V Vcer = 20V (see Fig.7)
Vce = 12V Vci = 25V Ic = 20mA
NOTE:
These figures are worst case, assuming all the power is
dissipated in one transistor. If the power is equally shared
between the two transistors, both thermal resistance figures
can be reduced by 50C/watt.
19
SL301K/SL301L
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 22C2C
Value
Symbol
Characteristic
Mfn.
Typ.
Max.
breakdown
breakdown
Collector emitter breakdown
BVcbo
BVceo
20
LVceo
12
Emitter base leakage current
Iebo
Iebo
10
Collector base
Collector emitter
Collector isolation breakdown
Forward current transfer
BVcio
Hfe
ratio
Vbe(SAT)
Collector base leakage current
Collector isolation leakage current
40
70
100
50
80
0.7
0.36
0.6
0.8
0.9
10
CIO
10
Collector capacitance
Cob
Base capacitance
Cib
Collector isolation capacitance
Cci
Transition frequency
fT
nA
V
400
= 10/yA
= 10//A
Ic = 5mA
Veb = 4V
Veb = 2V
Ic = 10/iA
Ic
Ic
<o
<o
<o
ICBO
I
25
Vce(SAT)
Saturation voltage
V
V
V
12
60
Conditions
Units
680
II
II
II
<
<
<
o"
o"
II
II
Ml
II
= 10mA, Ib = 1mA
= 10mA, Ib = 1mA
Vcb = 10V
Vci = 10V
Vcb = 5V
PF
pF
Vbe = 0V
Vci = +5V
PF
MHz Vce = 5V, Ic = 5mA, Freq = 100MHz
V
V
nA
nA
Ic
Ic
Matching
HFE1/HFE2
AVbe
|VBE1 - VbE2|
Temperature coefficient of AVbe
\
r =
1.1
Vce
0.9
1.1
Vce =5V,
Ic
Vce = 5V,
Vce =5V,
Ic
=5V,
Ic
0.45
0.45
10
mV
mV
A<V/C Vce
Ic
=
=
=
=
=
100M
1mA
100/l/A
1mA
100M
+25 e c\.
IjjA
20
5V, Ic
I=t10 c
COLLECTOR-BASE VOLTAGE
Fig.
0.9
2 Output capacitance (Cot,)
10>jA
100jiA
1nr
10mA
100mA
CURRENT
v.
voltage
Fig.
3 Typical variation of hp with collector current
SL301K/SL301L
800
I
v g.E
10V
VCE
5V
V CE
5V
CE
,V
V CE
IV
>.
01mA
07
10
10
20
ImA
7inV/'C
l-87mv/C
^^
70
30
CURRENT ImAI
TEMPERATURE
Fig.
("CI
4 fjv. collector curent(tj = fhfe .t= 100MHz

Fig.
Vbe
v temperature
-
IpA
V*
InA
V ,=20V
C
V ,,5V
C
v ,= iv
lOOpA
._
1
.
60
80
100
120
HO
3k
100k
160
TEMPERATURE CO
Fig.
6 Typical Iqio
v-
temperature
Fig.
7 Relationship between
VqER ancl R BE
21
SL301K/SL301L
22
,:
SL303L
^^F Semiconductors
SL303L
400MHz TRIPLE NPN TRANSISTORS
The SL303 is a silicon monolithic integrated circuit
which have
comprising three separate transistors, two of
transistor may be used
closely matched parameters; the third
The SL303 devices are
as, for example, a tail transistor.
5 (CM) package.
available in a 10-lead
TO
ORDERING CODES
- CM
SL303L
10
ISOLATION
y. y. y.
<
FEATURES
<L
Close Vbe Matching

High Gain
CM10
Good Frequency Response

Excellent Thermal Tracking
Fig. 1 Circuit
diagram
APPLICATIONS
Differential Amplifier
Comparator
QUICK REFERENCE DATA

12V
Max voltage
Operating temperature range
bb
to
20V
to
+175C

individual transistors
All electrical ratings apply to
thermal ratings apply to total package dissipation.
negative with respect
be
The isolation pin must always
to the collectors.
No one transistor may dissipate more than 75% of tne
power.
55C to
Storage temperature
Chip operating temperature +1 75C
Chip-to-ambient thermal resistance
total
TO-5 (CM)
425C/W
see Note
Chip-to-case thermal resistance
TO-5 (CM)
Vcbo
Vr
Vebo
Vc10
Icm
+175 C
265 C/W
20V
1
2V
to
20V
(see Figure 8)
9RV
A
20mA
the power is
figures are worst case, assuming all
is equally shared
dissipated in one transistor. If the power
resistance
thermal
both
between the three transistors,
figures can be reduced by 75 C/watt.
These
23
SL303L
lamb 25 C
Characteristic
Value
Symbol
Typ.
Collector base
breakdown
BVcbo
BVceo

V
V
12
Iebo
Collector isolation breakdown
BVcio
25
Hfe
30
50
40
70
60
100
ratio
50
Saturation voltage
Vce(SAT)
Vbe(SAT)
0.7
80
0.36
0.6
0.8
0.9
Base emitter saturation voltage

Collector base leakage current
ICBO
10
Collector isolation leakage current

Collector capacitance
CIO
10
Cob
10
Base capacitance
ClB

Ccio
fT
400
Conditions
= 10//A
= 5mA
//A
Veb = 4V
nA Veb = 2V
V
Ic = 10/uA
Vce = 5V, Ic = 1QmA
Vce = 5V, Ic = 100/uA
Vce = 5V, Ic = 1mA
Vce = 5V, Ic = 10mA
V
Ic = 10mA, Ib = 1mA
V
Ic = 10mA, Ib = 1mA
nA Vcb = 10V
nA Vcb = 10V
nA Vci = 10V
Vcb = 5V
PF
pF
Vbe = 0V
pF
Vci = +5V
MHz Vce = 5V, Ic = 5mA
20
Iebo
Units
Max.
680
Matching
lc
Ic
TR1 & TR2 only

HFE1/HFE2
Input offset voltage
AVbe
0.9
1.1
Vce
0.9
1.1
Vce
mV
mV
3
3
Temperature coefficient of
AVbe
5V, Ic
5V, Ic
5V, Ic
Vce =5V,
//V/C Vce = 5V,
10
of input offset voltage
Vce
=
=
=
Ic
Ic
= 10Ql/A
= 1mA
= 100/yA
= 1mA
= IOO/jA
Tamb
\
\
800
s
E
^,oo-c
OPER MING RE&t

"
,NG
> \ \\
400
?
MB,/,, R*
200
VOLTAGE
-2
[V|
0+2
10
18
220
TEMPERATURE CC)
Fig.
24
2 Output capacitance (CBb )
v.
voltage
Fig.
3 Power
dissipation derating curves
(TO-5 package)
SL303L
8UU
I
\
\
t
Va
07
03
1pA
IOjjA
10mA
1mA
IOOuA
10
10
2V
CE
IV
<;f
20
70
30
CURRENT ImA)
100mA
CURRENT
Fig.
Fig.
Typical variation of /) with collector current
fT
collector current (fr
v.
f\ht,\
.1= WO MHz)
IpA
S&-
^<f
vz V
5V
VCE
00
A 17m V/C
0-1 n *A
18 mV^C
V
v
100
C1
:5V
cr
1v
300
-60
-40
-20
+20
+40
+60
TEMPERATURE
Fig.
6 Vbe
v.
+60
+100
+120
+140
"6
+160
20
40
60
80
100
120
140
160
TEMPERATURE I'd
("CI
Fig.
temperature
7 Typical Icio
v.
temperature
R (OHMS)
Fig.8 Relationship
between Vcer and Rbe
25
SL303L
26
SL360/SL362
Semiconductors
SL360C & SL362C

HIGH PERFORMANCE NPN DUAL TRANSISTOR ARRAYS
The SL360C and SL362C are high performance NPN dual
transistor arrays fabricated as monolithic silicon devices.
feature accurate parameter matching and close

thermal tracking. They have high transition frequencies (typ.
2.2GHz) and low device capacitance. In addition the SL362C
offers good noise performance (1.6dB noise figure at
They
60MHz).
APPLICATIONS
Instrumentation
PCM
Fig. 1
Repeaters
Pin connections
FEATURES
Analogue Signal Processing

High Speed Switches
Digital
Accurate Parameter Matching.

HighfT (1.5GHzmin.,SL360}
and Analogue
Low
Noise
(1
.6dB
at
60MHz SL362)
Tamb =22C2C
Value
Type
BVcbo
All
10
BVcio
All
16
Emitter base leakage
Iebo
SL360/362C
Iebo
SL360C
Collector base
breakdown
Collector isolation
Conditions
Units
Symbol
Characteristic
Min. Typ. Max.
V
V
32
60
Ic
Ic
=
=
1QuA
10//
breakdown
current gain
LVceo
Hfe
fT
DC
Vbei
VBE2
All
14
SL360C
SL362C
SL360C
SL360E
SL360G
SL360C
SL362C
30
65
70
Input offset current
HFE1/HFE2
All
Saturation voltage
Vce(SAT)
SL360C
SL362C
SL360C
SL362C
SL360C
SL362C
SL360C
SL362C
SL360C
SL360C
SL360C
Noise figure
Collector base capacitance
Collector isolation
NF
Cob
Cci
capacitance
Emitter base capacitance
Forward base emitter voltage

Collector base leakage
Collector isolation leakage
Cte
Vbe(ON)
Icbo
I
CIO
30
1.5
2.2
1.6
3.2
1.4
2.2
3
0.9
Veb
nA
V
Veb
GHz
GHz
GHz
10
5
1.0
1.1
0.25
0.6
1.6
2.0
mV
mV
V
dB
pF
pF
pF
0.5
1.3
2.3
0.5
2.1
0.72
1
= lOmA.lB = 1mA
= 1mA,Rs = 200O,f = 60MHz
Vcb = 0V
Vcb = 0V
|
Ie
Vci
=0V
= 0V
= 0V
PF Vbe = 0V
Ie = 1mA,VcE = 2V
V
nA Vcb = 10V
nA Vci = 10V
PF
PF
3.8
= 4V
= 2V
Ic = 5mA
Vce = 2V,Ie = 5mA
Vce = 2V,Ie = 1mA
Vce = 2.5V, e = 5mA,f = 200MHz
Vce = 5V,Ie = 20mA
Vce = 5.0V,If = 5mA,f = 200MHz
Vce = 2V,If = 1mA
Vce = 2V,Ie = 1mA
Vce = 2V,Ie = 5mA
HlK
Vci
Vbe
27
SL360/SL362
COLLECTOR
jf
'
'
C CI
;h?
;<-te
600
200
F/g.2 Equivalent circuit for SL360,
SL362
F/g.
3 Typical noise figure emitter current for SL362
|
1
\\
l
E = !n
^^
Rs(
Fig.
4 Typical noise
SL362
SL360**
!**
JUNCTION TEMPERATURE
figure v source
impedance
for
SL362
(C)
Fig.5 Max. continuous collector current vs junction temperature

apply to individual transistors.
to the total package.
All electrical ratings
Thermal ratings apply
most negative point of the circuit

isolation between transistors.
The absolute maximum ratings are limiting values above

which life may be shortened or specified parameters may
be degraded.
to maintain electrical
Electrical ratings
VCB = 10V
Vfjl = 16V
lc
Veb = 4V VCE = 8V
= 20mA (SL360); 50mA
(SL362)
(see Figure 5)
Thermal ratings
CM8
Storage temperature
Operating junction temperature
Thermal resistance
-55Cto+150C
Chip-to-case
Chip-to-ambient
NOTES
1
The SL360G is also available to order. This meets RC5544
telecommunications requirements. SL360G has the SL360C
characteristics with an additional fr guarantee as shown.
These figures are worst case, assuming all power is

dissipated in one transistor. If the power is equally shared
between the two transistors, both thermal resistance figures
can be reduced by 50 C/watt.
2.
28
150C
(see Note 2)
265 C/W
425 C/W
SL440
SemicoiNluctors
SemicoiNluctoi
SL440
POWER CONTROL CIRCUIT
The SL440
is
to
a versatile integrated circuit designed
power
provide variable-phase control of triacs and other
switching devices
applications.
The
in
a variety of
basic elements of the
SL440
are
shown
in
ING CAPACITOR
0/P FIRING PULSE [
domestic and industrial

P TO
II
SERVO ERROR
SERVO ERROR "P
LIMIT
COMMON (NEUTRAL!
AC
CURRENT
3V STABILISED [
Fig.2.
An
discharged during positive
waveform
driving
which
is
to pin 14
C T connected
and negative half cycles of the
external timing capacitor,
50 Hz),
(typically
at
is
IIBIT t
CURRENT
CURRENT
LIMIT
t/f
constant rate
13).
When
passes through zero, at which point
CT
is
LIMIT
AC
l/P
01
proportional to the output of the servo amplifier
the charge reaches an internally-defined

generates a 50/is (typ.)
level, the conduction control circuit
triac. The crossover
firing pulse (pin 1) to trigger the
waveform
detector resets the timing cycle when the driving
(pin
0/P (CONDUCTION CONTROL!
CROSSOVER DETECTOR
tTERNAL CONNECTION. DO NOT USE
Fig.
DP14,
DG14
Pin connections (top)
recharged rapidly.
of
amplifier thus controls the conduction time
the load.
the triac, and hence the power delivered to
taken below +5V (e.g. to
If the Inhibit input (pin 4) is
action is over-ridden
pin 11) the conduction control circuit
can be used
the firing pulses are inhibited. This facility
The servo
and
current limit detector, by driving
in conjunction with the
from a current
the AC input terminals (pins 5 and 10)
FEATURES
transformer
in
series with the load.
connected from pin 4 to the

voltage,
inversely
proportional
appears on pin 4. This
is
If
load resistor
stabilised supply (pin 3), a
to
the
AC
is
DC
load current,
applied to the variable delay pulse
generator as soon as the internally defined threshold voltage

(approximately 5V) exceeds it, and so limits the load
current.
LOAD CURRCNT
UJ
Conduction Control
f^
-CD
o supply
Crossover Detector
Servo Amplifier
Internal Stabilised
Supply
(Available for External Circuitry)
Total Power
AC
Shut-Down
Facility
Load Current Limitation
APPLICATIONS
Lamp Dimmers
Automatic Lamp
Faders
Motor Speed Control
Fig.2
SL440
functional block diagram
29
SL440
ELECTRICAL CHARACTERISTICS @ Tamb
= +25C
Value
Characteristics
Min.
Typ.
Firing pulse width

Max. pulse current
60
50
120
Current to pin 3
15
Units
Max.
Conditions
AB
mA
mA
30
Rectified
AC
Voltage at pin 3
(internally stabilised)
+V
11.3
Inhibit operating voltage
(pin 4)
+V
Static gain of servo
amplifier
75
Current limit input threshold
0.7
Typical application, gain =
2k
x
T
r^
4^
*_db-
y
Lamp dimmer
Fig.3
using
minimum components
Fig.4
Automatic lamp fading circuit
APPLICATION NOTES
A
simple, manually-controlled,
shown
not
in
lamp dimmer
circuit
is
Fig.3. In this application, the servo amplifier
is
used;
proportional control of lamp brightness is

by the voltage applied via RV1 to the servo
amplifier output (pin 13) which is internally connected
to
the conduction control circuit.
effected
more sophisticated use of the SL440

an automatic lamp fading circuit
Fig.4
is
shown
in
which
has
applications in a variety of domestic environments.
The
circuit
is
used as follows: with S1 and S2 both open, the
of brightness
level
is directly controlled by the

setting of
closed, the positive voltage applied to pin
12 causes firing pulses to be produced at a conduction angle
R VI
When
S1
is
180
approaching
(fig.5)
maximum. When S2
is
and
the
closed and SI
lamp
is
brightness
is
opened, the servo
amplifier acts as an integrator due to the Miller action of C1

and the lamp brightness fades progressively to the level
previously set by RV1. The fade rate is determined by the
choice of CI
result
in
Fig-5
minutes.
Fig.6 shows the
SL440 used
in a
servo loop in which
current in the range
to 10A.
Triac conduction angle
v.
sinewava load power
motor speed control
The DC motor/tacho-generator is used in a velocity

motor velocity is linearly proportional
to the setting of RV1. RV2 controls the
maximum motor
circuit.
30
C0N0UCTKM ANGLE
for example, a 250 microfarad capacitor will

subjectively imperceptible fade rate of 20-30
OPERATING NOTES
In applications
recommended
where RF radiation
that the filter circuit
is
shown
problem,
in
Fig.7 be used.
it
is
SL440
TIMING
CAPACITOR
CHARGING 0
CURRENT
If At
Fig.9
Triac conduction time
v.
capacitor charging current
TACHOMETER GENERATOR
OC 0/P VOLTAGE PROPORTIONAL
TO SPEED
L
Fig.6
Servomotor control with motor current limiting
Where the SL440
is
used for domestic
light
dimming, or
in the
other applications where the power dissipated
considered excessive, the series
is
dropping resistor R
in
rectifier
shown
and dropping
impedance
AC
The
in Fig.8.
can be replaced by the circuit

with the low
resistor
series capacitor, together
at pin 3, provides a degree of
RF
filtering at the
supply terminals.
Fig.
Fig 7
RF
for loads lets than
filter
lOOWand above,
SOMI
KM
MHi
110V
Ilk
Cl
1 W
ISOV
Ilk
output
V]W
MS
HSli 120 *"*
Fig. 11
Fig.8
amplifier
0. 1\)F only.
K,
Cl
servo
v.
time
conduction
(demonstrating linear relationship)
Triac
lOOWor inductive. For loads of
use lOOfJH and
FOR 0V
10
Low lots power supply
featuring
Fully isolated supply operation of SL440,
full-wave crossover detection for -symmetrical timing.
Additional SL440s can be powered via separata 220\lfeed
pin 2
resistors, synchronizing being achieved by connecting
of each SL440 to the collector of the common sync,
transistor
TR1.
31
SL440
OH3V STABILISED
CURRENT CURRENT
TIMING
0/P
FIRING
CAPACITOR
put.se
Fig.

Storage temperature
Operating temperature
-55Cto+125C
-10Cto +65C
mW
Package dissipation
600
Supply current to pin 2
200mA DC
12
Circuit diagram of
NOTE
Where the SL440 is to be used in a device socket, care
should be taken to ensure that the reservoir capacitor on
pin
is
discharged before inserting the device. Failure to
observe this precaution
shunt
32
SL440
stabiliser.
may
result in
damage to the
internal
SL441A
ffl
^ r LEwwE
Semiconductors
^^F Senriconductoi
SL441A
ZERO VOLTAGE SWITCH
The SL441 A
is a symmetrical burst control integrated

an 8 pin DIL package. When used with a
triac, AC power may be regulated by varying the
number of mains cycles applied to the load in a fixed
timing period. The device is particularly suitable for
temperature control applications including hairdryers,
food warmers, soldering irons etc. Zero Voltage
Switching has the advantage of minimising radio
circuit in
COMMON(-VE) [ '
Vcc
CONTROL INPUT
AC INPUT [
TIMING COMPONENTS
SMOOTHING CAPACITOR [
6 ] PULSE DELAY CAPACITOR

] REGULATED OUTPUT
TRIAC GATE DRIVE [
frequency interference.
SPECIAL FEATURES
zero voltage point crossing detector,
1. Balanced
spike filter and pulse generator for reliable triggering
triac.
the
of
are
2. A period pulse generator and bistable which
arranged to provide symmetrical burst control and
1976)
BS5406,
(EN50.006,
firing.
eliminate wave
modify
3. A ramp generator whose output is used to
an internal reference voltage which is then compared

with the voltage appearing on the thermistor to form
a proportional control system. The period of the ramp

generator is defined externally and may be chosen to
lamp flicker' in accordance with EN50.006/
limit
BS5406, 1976.
4. The comparison
amplifier has inbuilt hysteresis to

eliminate switching jitter and a spike filter/sampling
and
circuit to provide high immunity to both spikes
coherent 50Hz/60Hz.
power
5. Thermistor malfunction may be sensed and
automatically removed.
inhibits
6. A supply voltage sensing circuit which
guaranfiring pulses when the supply is inadequate to
of
stressing
eliminates
tee proper circuit operation. This
the triac at switch-on.
Fig.
DP8
Fig.
Pin connections

Voltages
Voltage on pin 8
Voltage on pin 4
V 8 _, Max. 12V
V 4 _, Max. 10V
Currents
Supply current (pin 2) Peak value I2M 50mA.
Non-repetitive peak current (tp <250ns) + I2SM
200mA.
Output current (pin 5) Max.
5mA
Short circuit
protected.
Output current
Max 5mA
(pin 4) average value

Short circuit protected.
Temperature
Operating ambient temperature Tamb
U(AV)
10C
+75C
Storage temperature
2 Block schematic of SL441A
Tstg 30C
to
+125C
to
SL441A
Test conditions (unless otherwise stated)
Tamb = 25C
All voltages measured with respect to common
:
(pin
Value
Characteristics
Units
Min.
Shunt regulating voltage pin 3 @ 16mA
Supply voltage trip level pin 3
Supply current (less UAV, Is) (see Note
circuit
ON
circuit
OFF
Output current
Output current
Output current
14.7
8.0
130
80
800
(Ramp
(Ramp
start)
i/o
finish)J
w
Note
tf
Pulse width
Pulse finish
0.69
1
.09
360
420
V
V
V
4.5
mV
480
27
21.5
32.5
kO.
Vp-p
*"
^ ^ *'
R6C D us typical
R6C D M s minimum
Nominal (Co - 2.7nF) = 50us

Minimum (C D - 2.7nF)
63ms
0.85 0.1 5 x R T C T sec. See Application
t
**"*
after zero voltage point
R6
Pm
*""*
kQ. C D
in
in
'
'
the
"*
nF See Application
triac
gate
circuit
tf
period
'^
4.25
4.67
4.0
6)
Peak-to-peak amplitude of ramp

impedance (R6) (See Note 2)
ripple voltage pin 3
mV
mV
250
12
Pin 6 output
Tpt l^c'e^
20
200
150
at
Maximum
Ramp
O.
uA
Internal reference voltage

3.
mA
mA
mA
200
Sensor malfunction circuit operates

Input working voltage range
V
V
0.1
100
65
Bias current
Hysteresis
Triac firing pulse.
V
mV/C
8.5
2V
4V
Control input pin 8
cJe n
mA
7.5
9.0
8.5
+1
drain
into
drain
into short circuit
Internal drain resistance
2.
V
V
V
16
12.2
voltage
voltage
into
Max.
75C
@.
Regulated voltage pin 5

Regulated voltage temperature coefficient pin 5
Triac gate drive pin 4 (See Note 2)
Open
Open
Typ.
hj-o
circuit.
The actual value
of Rt
must
lie
between 500kn and
3MQ.
200 'CI*
CONTROL
VOLTAGE
(PIN SI
-RAMP
I
FINISH
* U-7VIV3I
CIRCUIT TRIP
UOmV
OPERATIONAL
25V
TYPICAL
RAMP START
Tamb cci
Fig.
34
3 Power
dissipation
Fig.
4 Control characteristic
-I2V ABSOLUTE
MAXIMUM RATING
SL441A
AC MAINS
"
WAVEFORM
OUTPUT OF
ZERO
CROSSING
PULSE
GENERATOR
R- Pa (OUTPUT
EXPANOEO
C.CO CAPACITOR
CONNECTED TO PIN C
Fig.
5 Pulse timing
APPLICATIONS
Setting up
With Re at zero
Rp to give the
temperature desired (eg 80C).
The value of Re will determine the minimum regulated
output air temperature (eg 40C).
maximum
output
resistance, adjust
air
SUGGESTED VALUES
8.2kO 5% 6W (less
Rd
Rc
Rp
TH
Rt
Ct
Cs
Fig
6 Application
circuit for
in air
stream)
22kQ linear control potentiometer

10kO Preset
NTCtypeR25 =47k20%; B^4000keg GM473.
VA341 etc.
2.2M QJ R am p period - 0.4 sec.
0.22uF
150uF16V
10%
Cd
2.2nF
Triac
TAG 225-400
temperature regulated hairdryer
35
SL441A
36
SL441C
MA Semiconductors
I^LEwvEY
Semiconductoi
^^F
SL441C
ZERO VOLTAGE SWITCH
an 8 pin DIL package. When used with a
varying the
triac, AC power may be regulated by
number of mains cycles applied to the load in a fixed
The SL441 C
circuit in
room
timing period. The device is especially suited to
temperature control applications including panel
has
heaters, fan heaters etc. Zero Voltage Switching
frequency
radio
minimising
of
advantage
the
COMMONI -VEI [ '
V.t
SMOOTHING CAPACITOR [
TRIAC GATE DRIVE
[_
CONTROL INPUT
] TIMING
AC INPUT [
3
COMPONENTS
6 ] PULSE DELAY CAPACITOR
] REGULATED OUTPUT
interference.
SPECIAL FEATURES
DP8
zero voltage point crossing detector,

1. Balanced
spike filter and pulse generator for reliable triggering
Fig.
Pin connections
of the triac.
are
2. A period pulse generator and bistable which
arranged to provide symmetrical burst control and
(EN50.006, BS5406, 1976)

modify
3. A ramp generator whose output is used to
an internal reference voltage which is then compared
form
to
thermistor
the
on
appearing
voltage
with the
eliminate i
wave
firing.
ramp
a proportional control system. The period of the
generator is defined externally and may be chosen to
EN50.006/
with
accordance
limit 'lamp flicker' in
BS5406, 1976.
4. The comparison amplifier has inbuilt hysteresis to
eliminate switching jitter and a spike filter/sampling
circuit to provide high immunity to both spikes and
coherent 50Hz/60Hz.
and power
5. Thermistor malfunction may be sensed
automatically removed.
inhibits
6. A supply voltage sensing circuit which
guaranfiring pulses when the supply is inadequate to
tee proper circuit operation. This eliminates stressing of
the triac at switch-on.
Fig.
Voltages
Voltage on pin 8
Voltage on pin 4
V 8 _, Max. 12V
V 4 _, Max. 10V
Currents
Supply current (pin 2) Peak value r I2M 50mA.
I2SM
Non-repetitive peak current (tp < 250ns)
:
200mA.
Output current (pin 5) Max.
5mA
Short circuit
protected.
Output current
Max 5mA
(pin 4) average value

Short circuit protected.
Temperature
Operating ambient temperature Tamb
U(AV)
10C
+75C
Storage temperature Tstg 30C to
2 Block schematic of SL441C
+125C
to
SL441C
Tamb = 25C
All voltages measured with respect to common (pin
:
1)
Value
Characteristics
Units
Min.
Supply voltage trip level pin 3
Supply current (less UAV, U) (see Note
14.7
8.0
+1
130
80
800
(Ramp
(Ramp
start)
,~
1
4.25
4.35
4.0
te dJ
70
100
27
21.5
RMS
CUrfent f6d m,
0.69
tf
Nominal (Co
mV
130
kO
32.5
Vp-p
c y C| e
p Pulse width
tf
Pulse finish
V
V
V
4.5
ripple voltage pin 3
ZZ7::?U
period
HA
mV
mV
250
12
finish))
Peak-to-peak amplitude of ramp

impedance (R6) (See Note 2)
Ramp
20
200
150
at
Pin 6 output
3.
Q
1

firing pulse.
mA
mA
mA
200
Sensor malfunction circuit operates

Tnac
V
V
0.1
100
65
Bias current
Hysteresis
2.
V
mV/C
8.5
Control input pin 8
cu Jem
mA
7.5
9.0
8.5
-1
voltage
circuit OFF voltage
Output current into 2V drain
Output current into short circuit
Maximum
V
V
V
16
12.2
ON
circuit
Max.
@ 75C

Regulated voltage temperature coefficient pin 5
Triac gate drive pin 4 (See Note 2)
Open
Open
Typ.
1
-
.09
^ 2K
R6C d ms typical
R6C D M s minimum
2.7nF) = 50ps
2.7nF)
63ms
sec. See Application
'
5 S ,He
CUrrem dra ned

'
ff
'
after zero voltage point
m P n 5
-"V-
'
R6
in
kfi,
CD
in
'"
lS
* **
nF See Application
0.85 0.1 5
RtCt
circuit.
The
actual value of R,
must
lie
between 500kn and 3Mii.
50
T
AMB
38
Fig.
circuit
Minimum (Co -
3 Power
no
(C)
dissipation
ISO
Fig.
4 Control characteristic of pin 8
SL441C
OUTPUT OF
ZERO
CROSSING
EXPANOEO
EXPANOEO
ZERO
CROSSING
C'CO CAPACITOR
CONNECTED TO PIN t
Fig.
5 Pulse timing
APPLICATIONS
Electronic thermostat for room heater
The circuit in Fig. 6 has a sensitivity of nominally
control band
1 00mV/C. The width of the proportional
compromise
is nominally 1.0C and offers a good
between temperature stability and regulation performance.
Figs.
For potentiometer control
7 and
characteristics
see
8.
SUGGESTED VALUES
8.2kfi 5% 6W (less
Rd
22kQ
Re
27 M
^ . .,-r
4.7UF10VTANT
Rt
Ct
Cf
Cs
linear control
> Ramp period
TAG 250-400
B
6.2k
thermistor.
4200.
e.g.
is
required, omit
Rj and Cj and
link pin
sees.'
5% fixed
R25 = 10kO
ITTKQ103
resistor or
See control characteristics
on-off control
1 1
10%
2.2nF
Triac
TH1 NTC
If
47nF (filter if required)

150uF 16V
Cd
Rx
in air stream)
potentiometer
0k
preset.
Figs. 7
and 8
7 to
pin 1.
Fig.
6 Application
circuit for proportional
temperature control system*
39
SL441C
)
/
/
//
TYPICAL CHARACTERISTICS
R25 *20%
-5%
-*"
R25 -20%
POT DISPLACEMENT (Re)

Fig.
7 Control characteristics of electronic
room thermostat (mechanical calibration)
30
E
ITT
Z>
KQ103CY
TH1
R25
=4200*5%
10k 110%
20
o
z
^/|
R25
10%
B
Re
-10%
-5%
10
10k (SET AT25C)
R25 -10%
B
Re
.5%
10%
POT DISPLACEMENT (Re)

Fig.
40
8 Control characteristics of electronic room thermostat
(electrical calibration)
SL443A
!Y
Semicomluctoi
^^F Semicomluctors
SL443A
ZERO VOLTAGE SWITCH
an 8-pin DIL plastic package and is mainly
intended for manual heat control applications, for
example cooker hot plates and powerful hair dryers.
The SL443A
circuit in
COMMON
8 ]
POT. SLIOER
7]
C,
PULSE DELAY CAPACITOR
TRIAC FIRING PULSE [
fc(+7V)
SPECIAL FEATURES
power/potentiometer disload
Well defined
placement characteristics
High immunity against spurious triac firing under
2.
noisy mains environment (automatic spike filtration)
Enables compliance with Cenelec EN50,006/
3.
AC INPUT [
1.
DP8
Fig.
BS5406-1976
Switching rate controlled
symmetrical burst control
(A)
(B)
Very low external component count
Triac firing pulses inhibited whilst the ICIs power
5.
supply is being established.
4.
COMMON I
'
APPLICATIONS
Cooker hotplates
Powerful hairdryers
1|
CT
Fig.
2 SL443A block diagram
41
SL443A
CIRCUIT DESCRIPTION
The externally current limited AC supply is applied
to the device, and rectification followed by shunt
regulation provides a 14V DC supply. This is externally
smoothed before application to the 7.0V series stabiliser
which feeds the resistance bridge. The stabiliser must
be within regulation, or operation of the 'Low Vcc
electrolytic capacitors.
The zero voltage crossing detector controls a pulse

generator that has a delayed output. The delay is
necessary since, with loads that are slightly inductive
or low power resistive, the triac load current may not
reach its required holding level at zero voltage point.
Both delay and pulse duration are defined by an
external capacitor and this further serves the purpose of
filtering out spikes which occur in the zero crossing
region. Automatic rejection takes place of spikes
having a duration of up to 50 per cent of the normal
width of the triac firing pulse.
The comparator amplifier has differential linputs and
these are used to compare the potential appearing on
the slider of the control potentiometer with that of the
ramp waveform. The output of this amplifier controls
the logic circuitry and the potentiometer setting defines
the fraction of the ramp period for which the triac is in
conduction so controlling the power in the load.
Inhibit' circuit will result. This circuit overrides all

other circuitry and prevents unsuitable firing pulses
from being supplied to the triac at 'switch-on'. The
current limited AC supply also drives the Period Pulse
Generator (PPG) and zero voltage crossing circuits.
The PPG produces a single short duration pulse for
each completed mains cycle and serves two purposes.
Firstly it is used to clock logic information such that the
circuit behaves in a symmetrical manner and only
complete mains cycles are applied to the load. Secondly
the pulse is used to switch timing components in the
ramp generator and this enables long time constants to
be achieved without having to resort to the use of
Test Conditions (unless otherwise stated)
Tamb -- 25 C,
All voltages measured with respect to common (pin
1)
Value
Characteristic
Min.
Shunt regulating voltage pin 3
Supply voltage
Supply current
trip level pin
(less
Typ.
Max.
16
3
Is)
See Note
7.2
7.6
6.8
7.0
18
circuit
ON
circuit
OFF
140
voltage
voltage
8.5
0.1

80
50
100
70
200
Internal reference
- ramp
- ramp
start
finish
Period of ramp generator -
Pin 6 output
impedance R6
0.3
0.5
Vs- 0.5
27
Vs-0.3
21.5
mA
v
kQ
v
V
mA
mA
mA
HA
0.7
30
Vs- 0.1
33
27
32.5
kQ
(Rp =100K,C, =0.68u)

(RMS mains voltage=220v)
-
The supply
42
current
Period of ramp
is
=T
0.45 x
(RMS
current fed into Pin 2)
2xC T xR P
x (RMS mains voltage) seconds
= 16mA
= 16mA,
Tamb = +75C
800
Control input pin 8

Bias current
l3
12.2
U AV, 2x
Triac gate drive pin 4
Open
Open
V
V
14.7
Potentiometer supply pin 5, Vs

Potentiometer resistance range
Conditions
Units
SL443A

Voltages
Max
Max
ys-
Voltage on pin 8,
Voltage on pin 4,
v*-
Currents
Supply current, pin 2 peak value Um

Non-repetitive peak current (tp ^ 250nS) I2SM
Is
Output current, pin 5
Output current, pin 4, average value U (AV)
10v
10v
50mA
200mA
Max
Max
Short
circuit protected
10mA
Max
Short
circuit protected
Temperatures
Operating ambient temperature
Storage temperature
Tamb
Power
See
1 to 75C
55to+125C
Tstg
Dissipation
Fig.
EXPANDED
EXPANDED
ZERO
CROSSING
CCD CAPACITOR
R- Pint OUTPUT
CONNECTED TO PIN
Fig.
4 Method of control
43
SL443A
Control is effected by varying the number of complete

mains cycles applied to the load in the fixed timing
period T.
v/VVWVl
V*
INTERMEDIATE POWER
Fig.
MAXIMUM POWER
5 Method of control
220V10V.
PERCENTAGE POWER
Component values
Rd 8.2kO 5%
Ftp
7W
100kfl (Control characteristic of linear potentiometer

is
shown
in Fig.
C s 220uF16V
0.47uF (Ramp
Ct
7)
period
This
20 seconds nominal)
Cd 1.5nF10%
TRIAC TAG.255 - 400
Fig.
44
6 Cooker hotplate control
characteristic applies to a linear potentiometer.

Different control characteristics are easily obtained
by
using a non-linear potentiometer and/or offset resistors
in the potentiometer circuit.
Fig.
7 Output power
v.
potentiometer displacement
SL445A
SL445A
ZERO VOLTAGE SWITCH
a triac controller providing a complete
temperature controlled electric panel
heaters, cookers, film processing baths etc.
Switching occurs at the zero voltage point in order
to minimise radio frequency interference.
The device is suitable for mains -on-line operation
The SL445
solution
is
for
SERVO AMP. INPUT (SENSOR]
PROPORTIONAL BAND RESISTOR
AC INPUT [
TIMING CAPACITOR
SERVO AMP. INPUT (REF| [
COMMON
and requires minimal external components.
Vc
SPECIAL FEATURES
TRIAC GATE DRIVE [

INHIBIT
Choice of proportional or on/off temperature control.
Controlled switching rate in order to limit 'lamp

(as per EN50,006). A pulse integration
flicker'
technique eliminates the problems associated with
electrolytic timing capacitors.
3. Very accurate temperature control is possible since
switching jitter has been eliminated without introducing
hysteresis to the servo amplifier.
4. Symmetrical burst control i.e. no half-wave firing (as
INHIBIT INPUT
] TIMING RESISTOR
] ZERO CROSSING DELAY CAPACITOR
] STABILISED BRIOGE SUPPLY
]
POT. EXPANSION INPUTv
] POT. EXPANSION OUTPUT
DP16
Fig.
LED/Buzzer drive circuit controlled by 6 above.

High immunity against spurious triac trigger pulses
under noisy mains environment.
7.
which responds
directly to the
temperature setting.
6. Over-temperature protection circuit using aTail-safe'
PTC thermistor and having the option of automatic or
manual
OUTPUT [
SERVO OUTPUT [
2.
per EN50,006).
5. LED drive circuit
[-
reset.
Fig.
8.
Spurious triac trigger pulses inhibited at 'switch-on'.

0. Potentiometer expansion circuit to improve resolution/reduce component count.
9.
1
2 SL445 block diagram
SL445A
CIRCUIT DESCRIPTION
AC
The externally current limited

supply
to the device and rectification followed
regulation produces a 14V DC supply.
This
is
externally
8.5V series
latter
applied
by shunt
smoothed before application to the

which must be within regulation
'Low Vcc Inhibit' circuit will result.
overrides all other circuitry and
stabiliser
or operation of the
This
is
circuit
prevents unsuitable firing pulses from being supplied

to the triac at 'switch-on'. The current limited
supply also drives the Period Pulse Generator (PPG)
AC
be used to control an LED so indicating whether or not

the appliance is consuming electricity .The output from
the NOR gate is also applied to an active spike filter
before application to the S input of the R/S Bistable.
Since this bistable can only be reset once every ramp
generator cycle, it follows that a definite limitation is
imposed on the switching rate of the system and this
enables compliance with the requirements of the
EN50-006 regarding 'lamp-flicker'.
An externally defined proportion of the ramp
waveform may be applied to the 'offset' of the Servo
Amplifier such that the amplifier has an offset which
varies linearly with time. This has the effect - as the
bridge approaches balance - of varying the power
output in proportion to the difference between the set
temperature and the actual temperature i.e. Propor-
and Zero Voltage Crossing circuits.

each completed mains cycle and serves two purposes.
Firstly it is used to clock logic information such that
the circuit behaves in a symmetrical manner and only
complete mains cycles are applied to the load. Secondly
the pulse is used to switch timing components in the
ramp generator and this enables long time constants
tional Control. The advantage of this arrangement is

that the approach of bridge balance is anticipated and
to be achieved without having to resort to the use of

electrolytic capacitors.
overshoot is avoided.
The potentiometer expansion
The Zero Voltage Crossing Detector
controls a pulse
generator that has a delayed output. This delay is
necessary since with loads that are slightly inductive or
low power resistive, the triac load current may not
reach its required holding level at the zero voltage point.
external capacitor and this further serves the purpose
of filtering out spikes which occur in the zero crossing
region. Automatic rejection takes place of spikes having
a duration of up to 50 per cent of the normal width of
the triac firing pulse.
The Servo Amplifier has differential inputs and these
are used to sense the output of the bridge containing
the room temperature sensing thermistor. The output
of this amplifier is NOR-gated with the outputs of the
Inhibit Amplifier and the Low Vcc Amplifier.
The output of this gate is accessible such that it may
circuit
matches the
characteristics of a typical NTC thermistor to provide

good resolution and linear temperature control over the
normal domestic temperature range.

The Bridge is supplied with a stable 8.5V supply
from the series stabiliser and one ninth of this supply
is used as a reference voltage for the Inhibit Amplifier.
This reference is compared with the voltage appearing
across the PTC thermistor which is used to sense an
overtemperature condition. The output of the Inhibit
Amplifier is used to control the NOR gate which has
already been mentioned and is also made accessible
such that visual or audible warning may be provided.
In addition, a suitable resistor may be connected
between amplifier input and output to provide hysteresis
should this be required. Choice of resistor value will
determine whether the circuit works in an automatic
manual
or
reset
mode.

Pin
1
3.
3.
Rmj-o
='00 "c/w
V4
Peak Repetitive Current in

(l2M)
N on -repetitive peak current
(tp <250uS) I2sm
80
mA
7.
7.
Output Current
6.
Applied Voltage
Applied Voltage
10. Applied Voltage
1 1
Output Current
1 6. Applied Voltage
8.
9.
SS
'00
125
TAMB <*C)
Fig.
46
3 Power
dissipation
'
50
Units
Applied voltage
Applied voltage
Applied Voltage
Output Current
Applied Voltage
5.
6.
Max.
mA
200
10
10
10
V
V
10
10
V11
V11
mA
mA
V
V
V
10
mA
V4
SL445A
Operating temperature range 1 0C to + 85C
55C to +1 25C
Storage temperature range

Tamb = 25C
All potentials measured with respect to common
:
(pin 2)
Value
Min.
Characteristic
Shunt regulating voltage Pin 4

Max. regulating voltage on Pin 4 at 85C
Supply sensing amplifier -minimum
working voltage Pin 4
Quiescent current drain *
Max.
Typ
Units
vrr
Conditions
= 20mA average
= 20mA average
U
U
16
12.2
8.2
mA
Lessln,
l7, l6,
I5AV
Stabilised bridge supply voltage Pin
@2mA
8.0
Temperature coefficient Pin

Triac gate drive Pin 5
supply current
is
8.5
200
80
50
100
70
800
7 for
(RMS
10
6.0
10
0.9
6.5
25
0.95
7.0
60
1.0
1
10
5.8
6.4
12
6.8
16
mA
mA
mA
"A
V
V
kQ
V
HA
V
V
V11
-9
kQ
3.5
4
60
40
V
V
& 16
0.45 x
Fig.
pulse timing
Input bias current

Servo amp. output voltage drive Pin 7
Internal drain resistance Pin 7
Inhibit amp. input Pin 8
Trip voltage
Input bias current
Inhibit amp. output voltage drive Pin 6
Inhibit voltage Pin 6
Potentiometer expansion circuit input bias
current Pin 10
Potentiometer expansion circuit output
resistance Pin 9
Proportional control band (R15 =220k)
Ramp generator period T
* The
V
mV/C
See
Current drive into short circuit

Current drive into 2V drain
Current drive into 4V drain
1
+1
0.1
Open circuit OFF voltage

Open circuit ON voltage
Servo amp. Pins
9.0
8.5
-1
1 1
10
uA
See
Fig.
kQ
See
Fig.
100
44
140
48
mV
Ris=220kQ
Ri3=100k, Ri4 =
1.0uF,220VAC
NORMAL OPERATION
-iW
1*
Fig.
ASSUMED OUTPUT
OF SERVO
AMPLIFIER
IAAAA
4 Timed on/ off control
47
SL445A
WVy\AAAAA/WW\AAAAAA
5 Timed proportional control normal operation
Fig.
R
OV.
POWER
PROPORTIONAL
BAND
100V.
POWER
u"
LEO
CONNECTED
OFF
THE
NOT
SHORT DURATION INTERRUPTIONS

REGISTERED BY THE EYE
Fig.
48
IN
LIGHT OUTPUT
ARE
6 Timed proportional control (expanded)
TO PIN 7
SL445A
EXPANDED
ZERO
CROSSING
Jl
|f
24Cq pSEC MIN
PULSE WIDTH
CD
tp
N0M =19C D)jS
24CQ ySEC MIN
tf
PULSE WIDTH
EXTERNAL CAPACITOR (CD
Fig.
Fig.
IN
N0M
19c Df S
nFI
7 Pulse timing
8 Potentiometer expansion
characteristic
49
SL445A
It is desirable to minimise LED
drive current since
has a significant effect on the power rating of the
mains dropping resistor Rd. If the LED is for facility
'a' or 'b', a high intensity, wide viewing
angle LED will
be required and a current of 5mA nominal is suqqested
this
i.e.
Rl=1I<Q(Vled = 1.5V).
the LED is only intended
If
for facility
'c',
a small,
narrow viewing angle LED may be used and a current

of 0.5mA nominal is sufficient i.e. Rl
10kQ (Vled
v
These two components may be omitted

temperature trip
then be taken to
facility
is
common
if
the overnot required. Pin 8 should
ie.
Pin 2.
component may be omitted if proportional control

not required.! The circuit will then provide time on/off
t This
is
control. Pin
C May be
5 should be taken to Pin
1 1
required to integrate input noise e.g. 47nF.
MQ
given below.
SECURITY (OVERTEMPERATURE
TRIP) INDICATION
Indication
shown
Fig.
Electric
1.5V).
A small amount of positive feedback may be applied
to the servo amplifier by inclusion of resistor
Rf
(Fig. 106). This can ensure flicker free operation
of the
LED by increasing the immunity of the amplifier to
noise etc. on its input connections. However, the level
of feedback should be minimised since temperature
regulation will necessarily be impaired. A typical value
for Rf would be 4.7
and this results in a hysteresis
of 13mV (0.1 3C) if the bridge components are
as
may be
provided by
LED
or buzzer as
in Fig. 11.
panel heater control with room thermostat and

optional security thermostat
LED INDICATOR
Provides the following facilities
(a)
In the case of timed proportional control, the
LED will be lit continuously if any energy is supplied
during the timing cycle, i.e. the LED will only be
extinguished if the room temperature is being maintained without panel assistance.
(b)
In the case of timed on/off control, the LED will
be lit for the period that energy is being consumed,
i.e. the LED will flash on and off as the room
temperature
varies about the set point.
(c)
Room temperature may be ascertained by observing LED action whilst adjusting the temperature setting
i.e. the LED is a substitute for the sound
produced by
electromechanical thermostats.
The LED facility may be added as shown in Fig. 10.
Fig.
11a
LED
Ileo
(lLD
Fig.
Fig.
50
10
LED
indicator connections
0.5mA.
5mA. VL
Vi
1.5V. R L
1.5V. f\
10ka)
lb Buzzer (6V.
6mA)
Fig. 1 1 Security indicator circuits
UC1;
SL445A
SECURITY (OVERTEMPERATURE
Controlled Switching rate (Rt, Ct)
TRIP) RESET
The period of the ramp generator is dictated by the

lamp
requirements of Cenelec EN50.006 concerning
switched into circuit
flicker The load can only be
power is interrupted
at the start of a ramp cycle i.e. if
cycle, subsequent
to the load at any point in the
at the start of the
met
only
be
for power can
Inhibit
Hysteresis may be externally applied to the
Amplifier such that re-entry of the control circuit takes
place automatically
i.e.
when
the panel temperature
to a certain level below the trip point. Alternatively,

the trip circuit - when activated
it may be arranged that
can only be reset by manual intervention e.g. momeninterrupting the mains supply. It is desirable to
falls
tarily
some hysteresis to the system when

buzzer, in order to ensure positive on/off operation.
When the manual reset mode of operation is adopted,
an additional capacitor is required to eliminate the
possibility of a spurious spike tripping the circuit.
using a
introduce
demands
nsxt cvcIg.
The pulse integration technique employed in the
ramp generator accounts for the mains voltage term
in the formula
Period of ramp
=0.2 x Vrms x Ct seconds 10%
1 00k. Ct is in uF, and Vrms is in

.OuF capacitor will provide a ramp period
supply.
of 44 sec if the circuit is used with a 220V AC
The capacitor should be of polyester or similar
consideraconstruction. Because of leakage and other
tions, electrolytic capacitors are not suitable.
This assumes Rt
volts, e.g. a
Proportional Control (Rpb)

Resistance Rpb controls the proportion of the ramp
is applied internally to the offset
controls the
facility of the servo amplifier. Rpb therefore,
width of the proportional control band.
waveform which
220k, the peak offset will be 1 0OmV which is

If Rpb
equivalent to a proportional control band of 1 C if the
above bridge component values are used.
|fR PB
Rx = 1 20k reset occurs 1 C below the trip point.

Rx = 56k reset occurs 2C below the trip point.
(Above assumes that the PTC thermistor has a +15%/C
coefficient in the region of the trip temperature e.g. the
=100k,PB=2.2C
= 390k, PB =0.55Cetc.
Overtemperature Control (Security)

(Rs. TH2)
ITT positte range.)
Rs=15k
Fig.
Trip
12 Automatic reset
Temperature
Min. Max.
TH2
= ITT POSITTE PTC thermistor

82C
typeYC080TB

typeYC090TB
90C
92C 100C
102C 110C
type YC1 00TB
Thermistors of alternative manufacture may be used

although the value of Rs may then differ. Tripping takes
-=- 8.
place if the resistance of TH2 is greater than Rs
The value of Rs should be kept high to minimise power
loss in Rd.
Triac and Cd
maximum gate firing voltage (Vgt) of a

2.0V and the output stage of the IC has been
designed to deliver a minimum of 80mA into such a
load. The nominal current is 100mA and the triac is
supplied with positive gate current. A wide range of
suitable, low price triacs are available from several
manufacturers. In order to minimise RFI, a triac should
be chosen which has a low latching current II. The
triac cannot latch until the supply voltage Vl >
Generally, the
triac is
Fig.
13 Manual reset
COMPONENT VALUES
Room Temperature Sensing (Rr, TH1,
Rv = 22k or 25k linear control potentiometer.
RR=18k2%
THI = NTC thermistor, e.g. ITT type KQ223Y,
R25
Rv)
=22k 10%, B =4300 5%
Using these components, substantially linear temperature control is obtained over the range 5C to 35C.
This range is covered by 69% of the potentiometer track
when the I.C's expansion circuit is used as shown in
figure I. If the LED facility is used, calibration can be
both accurate and rapid.
(Vt
Vt
Rl
II
Rl)
where
= on -state voltage of the device

= resistance of the triac load
Therefore the triac requires a gate current
Vl x 106
=
Vrms x
V2
us
x 2nf
after the zero crossing point in the supply cycle where
51
SL445A
PIN
1
FUNCTION
SERVO AMPLIFIER INPUT IREF)
COMMON
I-VEI
AC INPUT
SUPPLY (+VEI
TRIAC GATE DRIVE
INHIBIT
OUTPUT
LEO DRIVE /SERVO AMPLIFIER OUTPUT
INHIBIT INPUT
POTENTIOMETER TRANSLATION OUTPUT

POTENTIOMETER TRANSLATION INPUT
STABILISED BRIDGE SUPPLY
ZERO CROSSING DELAY CAPACITOR
10
11
12
13
U
15
..
TIMING RESISTOR
TIMING CAPACITOR
PROPORTIONAL BAND RESISTOR

SERVO AMPLIFIER INPUT ISENSORI
Fig.
52
15 C
SL445A
53
SL445A
f
= the supply frequency.
380V supply to reduce power dissipation
380V 10%, 50HZ supply, 1 kW load

MAX. Vt of triac = 1 .2V (@ L )
MAX. lLoftriac =50mA
e.g. for a
the dropper
in
by introducing a series diode.
resistor
we get Rl
=380
-^- =
2
Rl
Vl
The
MAX =
II
44.4Q
= 0.05
x Rl + Vt
-N-
+ 5%
44.4
52Q
52
.2
= 8.8V Max
Fig.
trailing
edge of the
firing
14 Mains supply input
circuit
pulse (Tf) must occur
not sooner than
Vl x 106
Vrms x
Tf
V2
point.
Kz
.'.
Table
Room
Servo
LED
0.5mA
control
82k
0.4W
2.4 nF 1.9
82k
1W
nF
1.3
Rz
Sorvo
Security
trip
LED
buzzer
(security)
table may be reduced for rationalization purposes if

required (e.g. common value for 220/240V supplies) or
where additional external circuitry is fed by the 8.3V or
14V supplies. This may necessitate an appropriate
increase in the value of the smoothing capacitor Cs.
Furthermore, consideration should be given to the

possible increase in chip power dissipation particularly
the external load is dynamic.
if
SMOOTHING CAPACITOR
(Cs)
Capacitor should be used except when

dealing with the higher current applications i.e. 5mA
LED, 6mA buzzer etc. Cs should then be increased to
330uF. The ripple voltage should be kept below 1V
peak - to - peak.
5mA
(6V.
6mA)
Nominal
Maximum
Rd value
RD power
(5%)
3.0k
6.8k
7.5k
12k
3.0k
6.8k
7.5k
12k
3.0k
6.8k
7.5k
12k
*
Table
2.2k
5.1k
6.2k
9.1k
2.2k
4.7k
5.1k
8.2k
Value of
RD
dissipation
Maximum
Rd power
dissipation
Nominal
power supply
voltage
Nominal
CD
10%
(with diode)
12k
nF
for various supply voltages
used
Ovtr
temptratura
54
39k
0.3W
The diode bypass resistor Rz (see Table 2) is

necessary to provide proper operation of the zero
voltage crossing circuit. The values for Rd given in the
3.3k
7.5k
8.2k
Rz (max)
A 220uF 1 6V
(R D )
indicates the value of resistor Rd as a function

of mains supply voltage, facilities provided etc. It will
be apparent that it is desirable when dealing with a
temperature
in
Cd
Table 2 Max. value of
Facilities
value
x 50
The same triac could of course be used to control a

higher power load. The load resistance and hence
required Vl would fall, but for convenience the value of
Cd need not be altered. Similarly, if the above calculations are repeated for a 220V supply, it will be established that Cd must exceed 1.77 nF and a value of
2.7 nF is again suitable. It may be convenient to use
the same triac and value of Cd for 220, 240 and 380V
applications. However, Cd should be kept as low as
possible if power dissipation in the dropper resistor is
to be minimised.
MAINS DROPPING RESISTOR
dissipation
Minimum
n
110V 240V 380V
10%
Power
x 106
MIN.
0.9 x 380 x -\/2~x 2 x
= 57.91 ns=24x Cd
8.8
CdMIN. =57.91 =2.41 nF

C D =2.7nF10%
.-.
220/
us after the zero crossing
x 2nf
4.7W
8.2W
8.9W
15.3W
W
9.1 W
5.1
9.8VV
15.3VV
W
9.1 W
5.1
9.8W
15.3W
W
9.1 W
5.1
9.8W
15.3W
7.0VV
12.1W
2.3W
4.1W
4.4W
7.6W
2.5W
4.5W
4.9W
7.6W
2.SW
4.5W
4.9W
7.6W
2.5W
4.5W
4.9W
7.6W
3.5W
6.0W
8W
5.9VV
20.2W
7.0W
13.1W
14.4W
10.1W
3.5W
6.5W
22.4VV
11.
11.
(mains dropping resistor)
7.2VV
2W
110V
220V/
24ov y
380V)
110V
220V/
240V >
380V)
110V
220V/
24ov y
380V )
110V
220V/
24ov y
380V)
110V
220V/
240V y
380V)
110V
220V/
240V y
380V
)
4.7nF
2.7nF
4.7nF
2.7nF
4.7nF
2.7nF
4.7nF
2.7nF
4.7nF
2.7nF
4.7nF
2.7nF
SL446A
^W Semiconductors
SL446A
ZERO VOLTAGE SWITCH
in ON/OFF control of triacs, the

incorporates zero voltage point triggering in
order to minimise radio frequency interference. Main
application areas are in switching resistive loads and
replacing mechanical thermostats in, for example,
central heating systems, washing machine heaters,
water heaters and smoothing irons.
The SL446A is suitable for mains on-line operation
and requires minimal external components.
Intended for use
SL446A
] SERVO AMPLIFIER
] SERVO AMPLIFIER
POSITIVE LINE (Vcl [
] PULSE DELAY CAPACITOR
TRIAC GATE DRIVE [
]REGULATEO OUTPUT
Balanced zero voltage point crossing detector,

spike filter and pulse generator for reliable triggering of
the triac.
2. A period pulse generator and bistable which are
arranged to provide symmetrica/ burst control and
eliminate half-wave firing (EN50,006/BS5406, 1976).
3. A high input impedance differential amplifier to
form part of a servo system. An internally defined
level of hysteresis is incorporated in the amplifier
which can limit the rate of correction of the loop to
meet the requirements
of
EN50,006/BS5406-1976,
flicker.
Internal rectification and regulation of current

supply provides power for the IC and a
limited
suitable supply for the resistance bridge.
4.
AC
REGULATED OUTPUT
A/C
INPUT
l/P
-VE
IIP
DP8
FUNCTIONS
regarding
AC INPUT [
Fig.
1.
^VE
COMMON -VE)[
Pin connections
supply voltage sensing circuit which inhibits

pulses when the supply is inadequate to
guarantee proper circuit operation. This effectively
prevents firing pulses from being applied to the
triac which are incapable of causing complete bulk
conduction (possible failure mechanism at switch-on).
5.
firing
APPLICATIONS
Pan Temperature Control
Water Heaters
Refrigerators
Panel Heaters
<
COMMON -VE
Fig.
2 SL446A block diagram
55
SL446A
Tamb = 25 C,
All voltages measured with respect
to common (pin
1 )
Value
Characteristic
Min.
Typ.

Supply voltage
trip level pin
Supply
circuit
The supply current
is
0.45 x
12.2
l3
=16mA
=16mA,
= +75C
mA
8.0
8.5
80
50
mV/C
0.1
V
V
mA
mA
mA
100
70
200
800
20
25
15
mV
mV
35
+ 15
10
27
21.5
9.0
8.5
on supply pin 3
(RMS
l3
Tamb
ON
ripple voltage
V
V
16
voltage
circuit OFF voltage
Servo Amplifier input bias current
Servo Amplifier hysteresis
Servo Amplifier input offset voltage
Servo Amplifier input working voltage range
Pin 6 output impedance R6
Maximum
Conditions
Units
14.7
current (less U AV, Is

Regulated voltage temperature coefficient
pin 5
Triac gate drive pin 4
Open
Open
Max.
32.5
kO.
Vp-p
Triac Firing Pulse

tP
Pulse width
= 0.69
I NominaTSo = 2.7nF) 2 oO^s

tf
Minimum (Cd
R6 Co us
M ^ ""
= 2.7nF) = 63us
"^ ^
typical
**"
V ' tage P int (R6
OUTPUT OF
ZERO
CROSSING
fli
t-0MKC
If.lOtRC
R- Pint OUTPUT
OCD CAPACITOR
CONNECTED TO PIN
56
Fig.
Pulse timing
in
kQ Cd
in
nF - See
Fig.6.)
SL446A
CIRCUIT DESCRIPTION
AC
supply is applied
externally current limited
to the device, and rectification followed by shunt
regulation provides a 14V DC supply. This is externally
smoothed before application to the 8.5V series stabiliser
which feeds the resistance bridge. The stabiliser must
be within regulation, or operation of the 'Low Vcc
The
overrides all
Inhibit' circuit will result. This circuit
other circuitry and prevents unsuitable firing pulses
The
'switch-on'.
from being supplied to the triac at
current limited AC supply also drives the Period Pulse
Generator (PPG) and zero voltage crossing circuits.
each completed mains cycle. The pulse train is used to
clock logic information such that the circuit behaves
mains
in a symmetrical manner and only complete
cycles are applied to the load.
pulse
a
controls
The zero voltage crossing detector
generator that has a delayed output. The delay is
Fig.
3 Power
necessary since, with loads that are slightly inductive

may not
or low power resistive, the triac load current
point.
reach its required holding level at zero voltage
of
external capacitor and this further serves the purpose
zero crossing
filtering out spikes which occur in the
of spikes
region. Automatic rejection takes place
having a duration of up to 50 per cent of the normal
width of the
triac firing pulse.
amplifier has differential inputs and these

internally
are used to sense the output of the bridge. An
the
defined level of hysteresis is incorporated in
the
amplifier; this can limit the rate of correction of
of
requirements
servo loop in order to meet the
EN50,006/BS5406-1976. The output of the amplifier
The servo
on
controls the logic circuitry and the triac is triggered
if pin 8 is
at the appropriate point in the mains cycle
more positive than pin 7.
dissipation

Voltages
Voltage on pins 7, 8
Voltage on pin 4
V7
Va
Vs -
V3 (14V)
10V
Currents
Supply current (pin 2)
Peak value l2M
Non-repetitive peak current ( tp< 250ns) I2sm
Is
Output current (pin 5)
Output current (pin 4), average value U (AV)
Temperatures
Operating ambient temperature
Storage temperature
Power
Dissipation
10to75C
Tamb
55 to 125C
Tstg
See
Fig.
50mA
200mA
10mA
10mA
57
SL446A
DESIGN EXAMPLE
tr
(See application circuit Fig.5)
'
_!
V2 X
2 x n
x 50
=95 us
tf
Using tf Min.
21.5kQ)
RD
_J~
8.35
220 x 0.9 X
x Cd x R6
1.09
Min. (R6
v
Min
"B
;-
3 LOAD
( TH
95
Co
SL446A
nF
^
x 21.5
1.09
fi
\ks
MAINS SUPPLY
Co ^ 4.05nF
Specify
Hies
Cd
10%
4.7nF
(Preferred value)
Using an ITT type KQ223Y thermistor in a bridge

comprising Re
18kQ 2% and R
22kQ
20%
linear potentiometer, substantially linear
temperature
obtained over the domestic temperature
range + 5C to +35C. The output from the bridge
is
approximately 1 00mV/C and since the SL446A has a
hysteresis of 25mV in the servo amplifier, the
hysteresis
of the thermostat is typically 0.25C.
The maximum
bridge supply current occurs when Vs
equals 9.0V;
the thermistor is at the maximum temperature
and the
potentiometer resistance is at minimum.
control
Components
are to be standardised so that heating

in the range 400 to 1200W
may be used. The
to provide linear temperature control over
the
elements
circuit
is
domestic temperature range of
Fig.
5 Space
+5C
to
+ 35C.
heater application of the
SL446A
is
Triac selection
The minimum load resistance
V2rms
is
40.3312.
Assuming a manufacturing tolerance of
load resistance, the maximum load current
220 x
1.1
40.33 X 0.95
The peak
342V Max.
repetitive
2202
1200
+5%
_
~
Using Rti
1 0% and
OOA
632A
RMS
is
220 x 2 X
CD
This capacitor defines both the delay and width

of
triac firing pulse. The triac can not latch
until the
mams voltage exceeds the sum of the triac on-state
voltage Vt and Vh which is the voltage dropped
across
the load resistance by the triac holding
current Ih
(Vt
2.0, Ih
50mA for the TAG 245). The maximum
load resistance corresponds to the 400W element.
22Q2
\/2
400
Maximum
load resistance
= 6.35 +
+ Vt
can occur
= Rt2 x e u
6 = + 5%
Is
T:/
and inserting R25 =

found that the resistance of
35C (308K) is 1 2.1 k minimum
'
it
22 x 0.8
is
9 +
18 X 0.98
mA =
.
12.1
0.814mA Max.
Average gate drive current
(AV)
The maximum drive current is 200mA into a short

circuit and this occurs for a period 2
x tp every mains
cycle. It is acceptable to use the nominal value

of
the formula
R6
in
=2x tpXfx 200 mA and p =0.69 CdR6

= 2 X (0.69 X 4.7 X 10-9 x 27 X 103) 50 X
200 mA
= 1.75mA
Co has a +10% tolerance.
U (AV) = 1.75 x 1.1 = 1.925mA Max.
t
If
at the
=121 x
05
Using Rd
2 = 8.35V
Vl, i.e., triac latching
8.35V point in the supply cycle.
cycle.
tf
(Vm is the minimum

frequency.)
127Q
is
Using
Mains dropping resistor R D

The total supply current of the circuit is 7.0mA
(AV) = 7 + 0.81 4 + 1 .925 = 9.74mA Max.
I5
121Q
necessary, therefore, to ensure that the firing

pulse does not finish before this point in the supply
58
=4300 5%
It
=22K10%
U (AV)
the
Vh
R25
the thermistor at
A suitable triac is the TAG 245-400. This is an

isolated triac with ratings of 400V and
6.5A RMS at a
case temperature of +70C. The device is suitable for
positive gate pulse operation and requires an Igt
of
50mA at a Vgt of 2.5V for reliable triggering. These
triggering requirements are easily met since
the SL446A
delivers more than 50mA into a 4V drain.
The trigger
pulse width should be Ss 20 us (see below).
Capacitor
characteristics of the thermistor are
the
in
is
mains voltage
The
Rd
P eak mains voltage

n X I3AV
V 16,,^..
kQ Max.
220. 0.9 x
2
w 9.74
a-,A
n x
Rd
8.63
Specify Rd
kQ Max.
kQ
= 8.2
5%
(Preferred Value)
Vl
Vm x V2 X 2nf
V3 Max.
The power dissipated by Rd
is
V2 rms Max.
<
Rd Min.
RMS mains voltage, f is the supply

(220 x 1.1)2
8.2 x 0.95 x 103
Maximum power
dissipated
by Rd
is
7.5
W.
+U
SL446A
OPERATING NOTES
components are distant from the
If any of the bridge
found necessary.
IC additional spike filtering may be
An effective method is given below
Fig.
6 Mains supply input
circuit
dissipated by Rd is approximately halved

diode must be
a series diode is used. However, the
with a bypass resistor for proper operation of
The power
if
shunted
Suggested
the zero voltage crossing detector circuit.
220
values for the by-pass resistor are 39kQ for 110,
operation.
and 240V applications and 82kO for 380V
mains
The diode should be rated to withstand the peak
voltage
mains
peak
the
example,
voltage. In the design
device is
1.1 x 2 = 342V and a 400V
is 220 x
suggested.
Fig.
If
the mains dropping resistor
is
mounted on the main
can couple
printed circuit board, board capacitance
good practice,
spikes directly to the circuitry. It is
circuitry and
therefore, to place a guard ring around the
take this to the common line (neutral, pin 1 ).
Supply smoothing capacitor Cs

Using
13.
C>- x -X
C>
Specify
146
I3av
=3X
9.74x103
^n
uF.
220 nF 25%, +100%.
59
SL446A
PIN
FUNCTION
COMMON - VE
* C INPUT
POSITIVE LINE
TRIAC GATE DRIVE
REGULATED OUTPUT
PULSE DELAY CAPACITOR
SERVO AMP -VE WPUT
SERVO AMP + VE INPUT
6
7
B
Fig.
60
SL446A
61
SL446A
62
SL521A/B/C
Semiconcluctors
SL521A, B
&C
WIDEBAND LOG AMPLIFIER

The SL521 A, B and C
wideband
circuit
between
frequencies
centre
logarithmic
detection
successive
are bipolar monolithic integrated
amplifiers, intended primarily for use in
IF
BIAS
and
INPUT
decoupling.
in
^J
I
rectification, are
for direct coupling and incorporate supply line
typically 12
mainly
EARTH
operating at
10MHz and 100MHz. The
devices provide amplification, limiting

suitable
strips,
lo6
The mid-band voltage gain of the SL521

dB (4 times). The SL521A, B and C differ
2o|
SL521
3
\p
is
CASE
"^-2
INPUT
EARTH
+VE
SUPPLY
/
RF SUPPLY
DETECTEO
OUTPUT
the tolerance of voltage gain and upper cut-off
CM8
frequency.
Fig. 1
Pin connections
FEATURES
(Non-simultaneous)
Well-defined Gain
4dB Noise
-55C
Figure
+175C
+175 C
250 C/W
to
Chip operating temperature
High l/P Impedance
Low O/P Impedance

165MHz Bandwidth
80 C/W
Maximum
On-Chip Supply Decoupling

Low External Component Count
instantaneous voltage at
+12V
video output
+9V
Supply voltage
APPLICATIONS
Logarithmic
F strips with Gains up to

1 dB.
08 dB
and Linearity Better Than
T =
.25
/ -55-C
-V
V \
T
25
C
I
\\
\\
\1\
\
FREQUENCY IMHzl
Fig.
2 SL521
Circuit diagram
Fig.
Voltage gain
v.
frequency
63
SL521A/B/C
Temperature
= +22C 2C
Supply voltage
DC
+6V
connection between input and bias pins.
Value
Circuit
Characteristic
Typ.
Min.
Voltage gain,
Voltage gain,
Upper
30MHz
60MHz
cut-off frequency (Fig. 3)
Lower cut-off frequency
Maximum
rectified video
output
current (Fig. 4 and 5)
maximum
11.5
12.5
11.3
12.7
11.0
13.0
11.3
12.7
11.0
13.0
10.7
13.3
150
170
140
170
130
170
rectified
Conditions
dB
dB
dB
10 ohms source, 8pF load
dB
dB
dB
MHz
MHz
MHz
MHz
ns
1.00
1.10
mA)
0.95
1.15
mA
0.90
1.20
mA)
ABC
ABC
Variation of gain with supply voltage
Variation of
ABC
ABC
(Fig. 3)
Propagation delay
Units
Max.
0.7
db/V
25
%/V
10 ohms source, 8pF load
10
ohms
source,
8pF
load
= 60MHz, 0.5V rms input
output current with supply voltage
Maximum
ABC
input signal before overload
1.8
Supply current
Maxiumum RF output
Note: Overload occurs
5.25
dB
15.0
18.0
mA
imA
12.5
12.5
15.0
18.0
11.5
15.0
19.0
= 60MHz, Rs = 450 ohms
mA
Vp-p
1.2
the input signal reaches a level sufficient to forward bias the base-collector junction to
+^
"^ ""'""'
II
II
/)!
INPUT SIGNAL IVrms)

Fig.
64
rms See note below
voltage
when
1.9
Noise figure (Fig. 6)
Rectified output current
v.
input signal
TR1 on
peaks.
SL521A/B/C
The 500pF supply decoupling capacitor has
a resistance
10 ohms. It is a junction type having a low

breakdown voltage and consequently the positive supply
current will increase rapidly if the supply voltage exceeds
of, typically,
7.5V
30
(see
ABSOLUTE MAXIMUM RATINGS).
MHz.
6OMH2
rOMHi
L=
RMS
0-5V
Rs= 450a
AMBIENT TEMPERATURE
Fig.
S Maximum
rectified
TEMPERATURE
("CI
output currant
v.
Fig.
temperature
Typical noise figure
("CI
v.
temperature
OPERATING NOTES
ho
r the Ireque ncy ra 9'
The amplifiers are intended for use directly coupled, as

shown in Fig. 8.
The seventh stage in an untuned cascade will be giving
virtually fuli output on noise.
Noise may be reduced by inserting a single tuned circuit
in
the chain. As there
is
a large
mismatch between stages
1:-5$C
1
T=-2SC
T=-125C
simple shunt or series circuit cannot be used. The choice of

network is also controlled by the need to avoid distorting
FREQUENCY
the logarithmic law; the network must give unity voltage

transfer at resonance.
A suitable
network
is
MHz
7 Input admittance with open-circuit output
its
conductance across the

Resistor R1 may be introduced to improve
admittance equals the total

circuit.
Fig.
in Fig. 9.
at resonance
The value of C1 must be chosen so that

tuned
shown
loss
the symmetry of filter response, providing other values are

adjusted for unity gain at resonance.
simple capacitor may not be suitable for decoupling
^SUPPLY
the output
line
if
many
stages and fast rises times are
may
required. Alternative arrangements
on the
be derived, based
DC
CONNECTION
H6
;+ rr* 6
parasitic parameters given.
Values of
positive
supply
\,5
'
2
i
*t
,J j \ 5,
decoupling capacitor
line
required for untuned cascades are given below. Smaller

values can be used in high frequency tuned cascades.
ÔUTPUT
"T DECOUPLING
Fig.
Number
Minimum
The
30nF
10nF
3nF
1nF
amplifiers have been provided with
to avoid the introduction of
between input and output
common earth
circuits.
Direct coupled amplifiers
of stages
6 or more
capacitance
DECOUPLING
^TV^
^\.
two earth
TO In* l>th STAGE
DC BLOCKING
leads
lead inductance
The equipment designer
should take care to avoid the subsequent introduction of

such inductance.
Fig.
Suitable interstage tuned circuit
65
SL521A/B/C
Parasitic
Feedback Parameters (Approximate)
The quotation of
these parameters does not indicate that
decoupling
elaborate
amplifier
has
arrangements
are
required;
the
been designed specifically to avoid this
requirement. The parameters have been given so that the

necessity or otherwise of further decoupling,
may become
matter of calculation rather than guess-work.

I
RF
C7
V6
mmhos
current component from pin 4

= 20
7~- ~
rr^l
Voltage at pin 6
(This figure allows for detector being forward biased
noise signals)
Vg _
Effective voltage induced at pin 6
V4
l
V6
Voltage at pin 4
_ Current from pin 2
Voltage at pin 6
6mmhos(f= 10MHz)
Voltage induced at pin 6
Voltage at pin 2
[vaja
= 0.03(f= 10MHz)
Voltage at pin 2
6 joined to pin 7 and

fed from 300 ohms source)
(pin
~y
~|_
fi
Vjjb
Volta ge induced at pin 6

Voltage at pin 2
= 0.01
(f
= 10MHz)
Voltage at pin 2
(pin 7 decoupled)
V6
LVaJ a[v 2 J b decrease with frequency above

at 6 dB/octave.
66
10MHz
by
SL523B/SL523C/SL523H
SL523 B,C&H
DUAL WIDEBAND LOG AMPLIFIER
The SL523B and C are wideband amplifiers for use in
successive detection logarithmic IF strips operating at
centre frequencies between 10 and 100MHz. They are
pin-compatible with the SL521 series of logarithmic
amplifiers
and
comprise
two
amplifiers,
internally
cascade. Small signal voltage gain is

internal detector with an accurate
logarithmic characteristic over a 20dB range produces
a maximum output of 2.1mA. A strip of SL523s can be
directly coupled and decoupling is provided on each
amplifier. RF limiting occurs at an input voltage of
25mV RMS but the device will withstand input
voltages up to 1.8V RMS without damage.
The SL523H is supplied in matched sets of eight devices.
The gain at 60MHz of the devices in the set is matched to
0.75dB. In all other respects the device is identical to an
SL523B. This selection enables very precise log strips to
be produced.
connected
24dB and
in
an
INPUT
EARTH
VIDEO OUTPUT
FEATURES
CM8
Small Size/Weight
Lower Power Consumption
Fig.
Pin connections (view from beneath)
Readily Cascadable
Accurate Logarithmic Detector

Characteristic

24dB
2.1mA
4dB
Small Signal Voltage Gain

Detector Output Current
Noise Figure
Frequency Range
Supply Voltage
Supply Current
(Non simultaneous)
10- 100MHz
^6V
30mA
55 C to + 1 75 C
55C to +125 C
Maximum instantaneous voltage at video output
+ 12V
+9V
Supply voltage
^rr*tc=b>i
riri;
O EARTH
Fig.
Circuit
EARTH
diagram (one amplifier)
67
Ambient temperature 22C 2C
Supply voltage +6V
DC connection between pins 6 and 7
Characteristic
Type
Small signal voltage gain

Gain variation
(set of 8)
Upper cut off frequency

Propagation delay
Maximum
rectified
B
C
B
C
H
B
B
B
Value
Units
Min.
Typ.
Max.
22.6
22
22
24
24
24
24
25.4
26.6
0.5
0.75
dB
dB
dB
dB
dB
10
4
15
MHz
MHz
2.1
2.3
2.4
21.4
C &H
C & H
C & H
fi
120
26
26
150
Conditions
!
Freq.
30MHz
Freq.
60 MHz
/
1
Freq.
= 60MHz
ns
video
output current
Maximum

Source impedance 10
Load impedance 8pF
Frequency 60MHz
B H
C
1.9
1.8
B C & H
1.8
2.1
mA
mA
V in 0.5VRMS
input signal
before overload
Noise figure
BH
Supply current
Maximum RF
VRMS
1.9
5.25
dB
30
30
36
38
mA
mA
Source impedance
450 Q
25
23
output
voltage
B C & H
Vp-p
1.2
24
\>
22
3
8
< 16
o u
12
FREQUENCY MHz
Fig.
Vin
Fig.
Voltage gain
v.
frequency
mVrmj
3 Rectified output
current
v.
input signal
OPERATING NOTES
The
amplifier
is
designed to be directly coupled (see
Fig. 5)
The fourth stage in an untuned cascade will give full

output on the broad band noise generated by the first
stage.
Noise may be reduced by inserting a single tuned

circuit in the chain. As there is a large mismatch between
stages a simple shunt or series circuit cannot be used.
The network chosen must give unity voltage gain at
resonance to avoid distorting the log law. The typical
value for input impedance is 500 ohms in parallel with
5pF and the output impedance is typically 30 ohms.
Although a 1nF supply line decoupling capacitor is
included in the can an extra capacitor is required when
the amplifiers are cascaded. Minimum values for this
capacitor are 2 stages - 3nF, 3 or more stages - 30nF.
In cascades of 3 or more stages care must be taken to
avoid oscillations caused either by inductance common
to the input and output earths of the strip or by feedback
:
68
Frequency range
10
Log. range:
RF small signal gain
Video output
:
Fig.
5 Simple
to
100MHz
45dB
48dB
2Vpeak
log. IF strip
along the common video line. The use of a continuous

earth plane will avoid earth inductance problems and a
common base amplifier in the video line isolating the
first two stages as shown in Fig. 6 will eliminate feedback on the video line.
Frequency range
10to90MHz
80dB
72dB
Log.range:
RF
small signal gain
Video output
Log.accuracy
Fig.
6 Wide dynamic range
TYPICAL PERFORMANCE
Fig. 8 shows the dynamic range error curve and

frequency response obtained. The stage gains of the
SL523 devices used were as shown in Table 1
Max.
Stages
fo
(MHz)
60
60
60
60
2
3
Lift
Gain (dB) Deviation

(dB)
24.1
23
0.235
1
Table
Stage gains of SL523 used in performance
tests
The input v. output characteristic (Fig. 8a) is calibrated at 10dB/cm in the X axis and 1V/cm in the Y
Fig.
peak
0.5dB (Typ.)
of
of
error
0.5dB.
As
a comparison, the log amplifier of Fig. 7
was con-
randomly selected SL521 Bs (two

replacing each SL523B). Again, a dynamic
response of 80dB was obtained (Fig. 9a) with an
accuracy of +0.75dB (Fig. 9b).
Bandwidth curves are shown in Figs. 8c and 9c,
where the amplitude scale is 2dB/cm, with frequency
markers at 10MHz intervals from 20 to 100MHz. Using
SL523Bs (Fig. 8c), the frequency response at 90MHz is
4dB down on maximum and there is a fall-off in response
after 50MHz. Fig. 9c shows that the frequency response
of the amplifier falls off more gradually after 40MHz but
with
structed
SL521BS
again the response at
24.089
23.888
24.086
dynamic range was attained.

characteristic (Fig. 8b) is calibrated at
10dB/cm in the X axis and 1dB/cm in the Y axis; this
shows the error between the log. input v. output
characteristic and a mean straight line and shows that a
dynamic range of 80dB was obtained with an accuracy
80dB
The
oscilloscope.
8mA
log. IF strip
axis.
Unselected SL523B devices were tested in a wideband logarithmic amplifier, described in RSRE Memo.
No.3027 and shown in Fig. 7.
The amplifier consists of six logarithmic stages and two
range of greater
'lift' stages, giving an overall dynamic
than 80dB. The response and error curves were plotted
on an RHG Log Test Set and bandwidth measurements
were made with a Telonic Sweeper and Tektronix
90MHz is 4dB down on maximum.
tests show that the SL523 is a very successful

dual-stage log.amplifier element and, since it is pin-
These
compatible with the SL521, enables retrofit to be

carried out in existing log. amplifiers. It will be of greatest
benefit however, in the design of new log amplifiers,
enabling very compact units to be realised with a much
shorter
summation
7 Wideband logarithmic amplifier
line.
69
Fig.
Fig.
8a Input/output
Fig.9a Input/output
8b
Fig.
Error curve
Fig.
Fig.
70
Characteristics of circuit
shown
in Fig.
7 using
SL523Bs
Fig.
9b
Error curve
9c Frequency response, detected output
9 Characteristics of
circuit
shown
in Fig.
7 using SL521Bs
SL525C
Semiconductors
SL525C
T20MHZ WIDEBAND LOG
The SL525C
wideband
logarithmic
frequencies
monolithic integrated circuit
for
decoupling.
strips,
I.F.
operating
at
10MHz and 60MHz. The
between
amplification,
provide
STRIP AMPLIFIER
amplifier, intended primarily for use in successive
detection
suitable
a bipolar
is
IF
and rectification,
and incorporate supply
limiting
direct coupling
The mid-band
centre
devices
voltage gain of the
are
line
SL525C
is
typically 12dB.
CM8
Fig.
Pin connections
FEATURES
Well-defined Gain
4dB Noise
Figure
High l/P Impedance
Low 0/P Impedance

150
Operating Temperature range
Low
External
-55Cto+175C
-20Cto+100C
MHz Bandwidth
Maximum
+12V
9V
video output
Component Count
Supply voltage
APPLICATIONS
Logarithmic IF strips with Gains up to 108 dB
1 dB.
and Linearity Better Than
20-0
14
./*/'""
!["X
12
z
S,.
\\
\\
\\\
XI
T= t
M0C
2 .0
o
10
FUEQU ENC1
Fig.3 Voltage gain
Fig. 2 Circuit
diagram
u
1
10*
MHil
v.
frequency
71
SL525C
Test conditions (unless otherwise stated) :TA = +22C 2C
Supply voltage = +6V

DC connection between input and
bias pins
Value
Characteristic
Unit*
Min.
Voltage gain
Upper cut-off frequency

(Fig. 3)
Typ.
10.5
13.5
10.0
14.0
dB
dB
MHz
MHz
120
150
(Fig. 3)
Propagation delay
Max.
rectified video
Rs =
Rs =
10ft,
10ft,
10ft,
10ft,
maximum
mA
1.25
0.7
C L =8pF
C L =8pF
= 60MHz,
V jn
500mV
dB/V
rectified

l/P signal before overload
1.8
25
%/V
1.9
Vrms
Noise figure (Fig. 6)
Maximum RF
output voltage
Supply current
dB
5.25
1.2
Vp-p
15
mA
See note
f
= 60MHz, R = 450ft
s
,.
NOTE
1
Overload occurs when the input
signal reaches a level sufficient to forward-bias the

base-collector junction of
III
s*
^.
/s
10
JOMMi
-t-
M1
\'/s
Z3
0-
<\s
o
o
05
'i
i
tf
'i
'/
/
J
-*
INPUI
Fig.
72
C L =8pF
C L = 8pF
ns
0.85
Maximum
f= 30MHz, R s =
f = 60MHz, R
s =
output
current (Figs. 4 and 5)
Variation of
Conditions
Max.
SIGNAL
Vim.
v.
input signal
TR1 on
peak.
rms
SL525C
capacitor hat a resistance
The 500pF supply decoupling
10 ohms. It is a junction type hawing a low

breakdown voltage and consequently the positive supply
of, typically,
current will increase rapidly
if
the supply voltage exceeds
7.5V
(see
ABSOLUTE MAXIMUM RATINGS).
30MHj_
OMMi
INPUT
RMS
0'5V
AMBIENT TEMPERATURE
Fig.
5 Maximum
rectified
output current
TEMPERATURE I'd
I
v.
Fig.
temperature
~r~r
OPERATING NOTES
v.
temperature
ovr the frqu* ncy ror 9*
The amplifiers are intended for use directly -coupled, as

shown in Fig. 8
virtually full output on noise.
may be reduced by
Noise
in
the chain. As there
is
1,
tuned circuit
mismatch between stages a
A suitable
network
is
shown
1
I
K)
00
Fig.
7 Input admittance with open-circuit output
its
conductance across the

Resistor R1 may be introduced to improve
admittance equals the total
loss

A simple capacitor may not be suitable for decoupling
the output line
if
many
stages
fast rises times are
and
SZ
~T
OC
CONNECTION
^"V
f.v-TW^
positive
supply
line
decoupling capacitor
SUPPLY
DECOUPLING
O 1*6
required.
Values of
t0
70
FREQUENCY (MHz)
in Fig. 9.
at resonance
The value of C1 must be chosen so that

circuit.
JS'C,
inserting a single
a large
tuned

network is also controlled by the need to avoid distorting
transfer at resonance.
2+
5
/_
i_
*T
required for untuned cascades are given below. Smaller

\
Number
Minimum
The
6 or more
30nF
10nF
3nF
1nF
capacitance
amplifiers have been provided with
to avoid the introduction of
between input and output
Fig.
of stages
common
circuits.
two earth
tWA
PIN!
ILOCKIN
^DC
CAPACITOR
leads
designer

such inductance.
TO (n.lltHSTAGC
earth lead inductance
The equipment
DECOUPLING
Fig.
73
SL525C
Feedback Parameters (Approximate)
Parasitic
The quotation of
elaborate
these parameters does not indicate that
decoupling
arrangements are required; the

been designed specifically to avoid this
requirement. The parameters have been given so that the
amplifier
has
necessity or otherwise of further decoupling,
may become
matter of calculation rather than guess-work.

_
[4
RF
component from pin 4

= 20 mmhos
t
z
..,.__
voltage
current
'
at pin
(This figure allows for detector being forward biased

noise signals)
^6 _
Effective voltage ind uced at pin 6
V4
l
V6
Voltage at pin 4
_
= Current from pin 2 =
Voltage at pin 6
[%-=
6mmhos

Voltage at pin 2
(f
' 03
003
10MHz
(f
10MHz
>
Voltage at pin 2
6 joined to pin 7 and

from 300 ohms source)
(pin
fed
fV
6 "l
vfj b
o,tageatpin2
01
f
<
10MHz
>
Voltage at pin 2
(pin 7 decoupled)
Ve Lv d a\y 2 J b decrease with frequency above 10MHz

at
74
6 dB/octave.
by
SL531C
K ^ rLEwwC
^V Semiconductors
r
SL531C
TRUE LOG
IF
for use
is a wide band amplifier designed
logarithmic IF amplifiers of the true log type. The input
fresame
the
at
are
amplifier
and log output of a true log
quency e detection does not occur. In successive detthe log
ection log amplifiers (using SL521 SL1 521 types)
AMPLIFIER
The SL531C
INPUT EARTH
in
INPUT
\/"^~"\/
DECOUPLE
ILFONLYI
output
is
detected.
The small signal gain

500MHz. At high signal
is
10dB and bandwidth
is
over
BIAS
l-O
OH
OUTPUT
levels the gain of a single stage
drops tounity.Acascade of such stagesgiveacloseapproximation to a log characteristic at centre frequencies

between 10 and 200MHz.
An important feature of the device is that the phase shift
any phase inforis nearly constant with signal level. Thus
mation on the input signal is preserved through the strip.
CM8
Fig.
Pin connections
FEATURES
Low Phase
Shift
vs Amplitude

Low External Components Count
APPLICATIONS
True Log
Strips with:
Log Range
70 dB
Centre frequencies
10-200 MHz
0.5 degrees/
Phase
Shift
10
dB

Supply voltage
Max junction temperature

Junction
Junction
+ 15
volts
-55Cto+ 150C
-55Cto+125C
See operating notes
150C
ambient thermal resistance

case thermal resistance
Fig.
2 Circuit diagram
220C/Watt
80C/Watt
CIRCUIT DESCRIPTION
The SL531 transfer characteristic has two regions. For
large
small input signals it has a nominal gain of 10 dB, at
signals the gain falls to unity (see Fig 7). This is achieved by
in
amplifier
operating a limiting amplifier and a unity gain
tailed
parallel (see Fig 3). Tr1 and Tr4 comprise the long
Tr5,
pair limiting amplifier, the tail current being supplied by
see Fig 2. Tr2 and Tr3 form the unity gain amplifier the gain
of
outputs
The
of which is defined by the emitter resistors.
both stages are summed in the 300 ohm resistor and Tr7
Important
acts as an emitter follower output buffer.
unity
features are the amplitude and phase linearity of the
transistors
5GHz
of
the
use
gain stage which is achieved by
with carefully optimised geometries.
Fig.
3 Block diagram
75
SL531C
Test Conditions (unless otherwise stated):
Test circuit Fig (4)
Frequency 60 MHz
Supply voltage 9 volts
Ambient temperature 22 2C
Value
Characteristic
Units
Min
Typ

High level slope gain
10

Lower cut off frequency
Supply current
Phase change with input amplitude
Input impedance
Output impedance
250
12
-1
500
3
17
10
1.1
parallel
-3dBw.r.t.
1.
extra dissipation in this resistor remaximum ambient operating temperature to

100C. It is also possible to use a 6 volt supply connected
directly to pins 1 and 2. Problems with feedback on the
supply line etc may occur in this connection and RF chokes
may be required in the supply line between stages
Layout Precautions
The internal decoupling capacitors help prevent high frequency instability, however normal high frequency layout
precautions are still necessary. Coupling capacitors should
be physically small and be connected with short leads. It is
most important that the ground connections are made with
short leads to a continuous ground plane.
Fig.
4 Test circuit
-40
-75"
'
"t
Bn,
Zl
T= 25
T--55C
^
^
sC \
\
\V
\\
/
+ 1?.
j
\
\"
i\-
y;
\
tJMHz
K MHz
Fig.
76
dBm
The LF response is determined by the on chip capacitors.

can be extended by extra external decoupling on pins 5
and
The
V| N
Low Frequency Response
3.
It
2.
60 MHz
30 dBm to +
10- 200MHz
An on chip resistor is provided which can be used to drop

the supply voltage instead of the external 1 80 ohms shown
circuit.
= -30dBm
Vin
with 1k
Supply Voltage Options
the test
duces the
MHz
degrees
15Dseries with 25nh
OPERATING NOTES
in
Vin
MHz
dB
dB
+1
2. 5pf
Conditions
Max
100MHz
5 Small signal frequency response
SL531C
60 MHz
VCC =9V
LOW LEVEL
GAIN
10 dB
Vin (dBm)
6 Phase
v.
input
//
;
/
Fig.
/
/
//
l/
TYPICAL APPLICATION
STAGE LOG
STIP
.
Input log range OdBm to -70dBm

Low level gain 60dB (-70dBm in)
Vin VOLTS (rms)
Output dynamic range 20dB

Phase shift (over log range) 3
Frequency range 10 200MHz
Fig.
7 Transfer characteristics linear plot
The circuit shown in Fig 9 is designed to illustrate the use

SL531 in a complete strip. The supply voltage is fed
60 MHz
VCC 9 VOL TS
of the
to
each stage
via
an external 180Q resistor to allow oper-
125C ambient. If the ambient can be limited to

+ 1 00C then the internal resistor can be used to reduce
very
the external component count. Interstage coupling is
ation to
being
simple with just a capacitor to isolate bias levels
necessary. No connection is necessary to pin 5 unless operprovide
to
important
It
is
ation below 10MHz is required.
posiextra decoupling on pin 1 of the first stage to prevent
feedback occuring down the supply line. An SL560 is

used as a unity gain buffer, the output of the log strip being
attenuated before the SL560 to give a nominal OdBm out-
tive
put into 50D.
V IN IdBm]
scale
Fig. 8 Transfer characteristics logarithmic input
Fig.
9 Circuit diagram 6 stage
strip
SL531C
//
//
//
to
60 M
1
CO
0-6
0-2
-80
-60
-40
INPUT (dBm)
-^
<
X
O-
-2
-3
80
-f
-4
-2
INPUT (dBm)
Fig.
78
10 Transfer function' of log
strip
SL532C
Semiconductors
SL532C
LOW PHASE SHIFT LIMITER
is a monolithic integrated circuit designed
wide band limiting IF strips. It offers a bandwidth
amplitude.
of over 400 MHz and very low phase shift with
The small signal gain is 12dB and the limited output is
has
1volt peak to peak. The use of a 5GHz IC process
produced a circuit which gives less than 1 phase shift
internal
has
amplifier
The
12dB.
when overdriven by
decoupling capacitors to ease the construction of cascaded strips and the number of external components
required has been minimised.
The SL532C
for
use
INPUT GROUND
in
INPUT
_!_
DECOUPLE OF
0NW
OUTPUT GROUND
CM8
Fig.1 Pin
connections
FEATURES
Low Phase Shift v. Amplitude
Wide Bandwidth
FJt
"^rr
APPLICATIONS
Phase Recovery Strips
(e.g.
in
Radar and
*Ww*
ECM Systems
Doppler)
Limiting
Amps for SAW Pulse Compression Systems
Phase Monopulse Radars

Phased Array Radars
Low Noise
Oscillators
Fig.2 Circuit diagram

Temperature (Ambient) 25C
Frequency 60 MHz
Vcc = +9V
R L =1kffl/2.5pF
Value
Conditions
Characteristic
Min.

Limited output voltage

Lower cut off frequency
Supply current
Phase variation with signal
Input impedance
Output impedance
Max
level
Gain variation with temperature

Noise figure
Typ.
Max.
10
12
14
dB
0.9
1.2
1.55
Vp-p
200
400
7.5
10
MHz
MHz
8.5
11
The lower frequency cut off can be

extended by the use of external capacitors
-3dB.
mA
degree Vin
= -30dBm
to
+10dBm
1kQ//2.5pF
30O
+20
1
dBm
dB
dB
55Cto +125C
I400O source impedance
at
bUMHZ
79
SL532C
TYPICAL APPLICATION
Five stage strip
Input signal for
full
limiting
300>V rms
-57dBm
Limited output
Phase shift (V IN -57 --MOdBm)
1Vp-p
3typ.
The recommended output buffer amplifier to drive 50fi loads
is
the
SL560C
Fig.3 Five stage IF strip
CIRCUIT DESCRIPTION
The SL532 uses a long-tailed pair limiting amplifier
which combines low phase shift with a symmetrical limiting characteristic. This is followed by a simple emitter
follower output stage. Each stage of a strip is capable of
driving to full output a succeeding SL532 but a buffer
amplifier is needed to drive lower impedance loads. No
external decoupling capacitors are normally required but
for use below 10MHz extra decoupling can
be added on
pins 1 and 5. Bias for the long-tailed pair is provided by
connecting the bias (pin 2) to the decoupled supply (pin 1).
80

Supply voltage
+ 15V
-55Cto + 150C
-55Cto + 125C
SL541B
Semiconcluctors
SL541B
HIGH SLEW RATE OPERATIONAL AMPLIFIERS
The SL541 is a monolithic amplifier designed for optimum
rate
pulse response and applications requiring high slew
loop
with fast settling time to high accuracy. The high open
closed
gain is stable with temperature, allowing the desired
operational
loop gain to be achieved using standard
for
designed
been
has
device
The
amplifier techniques.
optimum response at a gain of 20dB when no compensation
guaranteed input offset
is required. The SL541B has a
voltage of
5mV
The SL541B
is
(BOTTOM VIEW)
Vce SUPPLY
CASE (-VE SUPPLY)
INPUT EMITTER DEGENERATION

(RESISTANCE COMPENSATION)
COMPENSATION
maximum and replaces the SL541C.

tested in two circuit applications (A and B).
+ V SUPPLY
TZ7-
*[1
FEATURES
NC[ 2
High Slew Rate:
75V/ ms
Fast Settling Time:
Open Loop
Very
in
DC
Low Thermal
to
Drift:
Temperature Coefficient
Guaranteed
Full Military
5mV
00MHz
-Vet
at
0dB Gain
13
]Rc
] MW-MV.I/P
I/P [ 3
].Vcc SUPPLY
SUPPIY [ 5
SUBSTRATE
0.02dB/C
of
]nc
EARTH[ *
50ns
70dB (SL541 B)
Gain:
Wide Bandwidth:
VERTING
CM10
14
COMPENSATION
]0UTPUT
KC[7
Gain
input offset
(TOP VIEW)
maximum
Temperature Range (DIL Only)
Fig.
DG14
Pin connections
Package: 10 Lead TO-5

1 4 Lead DIL Ceramic
APPLICATIONS
Wideband IF Amplification
Wideband Video Amplification
Fast Settling Pulse Amplifiers
High Speed Integrators

D/A and A/D Conversion
Fast Multiplier
Preamps

Supply voltage (V + to
24V
V -)
Input voltage (Inv. I/P to non inv. I/P)
Storage temperature
Thermal resistances
Chip-to-ambient TO-5
:
DIL
Chip-to-case:
TO-5
DIL
9V
55C to
+1 75C
TO-5: -55Cto +85'
DIL: -55Cto +125'
o
220C/W
125C/W
60C/W
40C/W
+175C
Fig.
SL541
circuit
diagram (TO-5 pin nos.)
81
SL541B
Tamb = 25 C
Rc =0fi
Test circuits: see Fig.8
Value
Characteristic
Circuit
Mln.
nominal supply current
Typ.
Max.
Units
A,B
16
21
mA
Input bias current
A,B
25
/"A
A,B
mV
Static
Dynamic open loop gain
Open
loop temperature coefficient

Closed loop bandwidth (-3dB)
Slew rate (4V peak)
Settling time to
Maximum
54
60
71
dB
dB
-0.02
dB/C
100
MHz
175
V///S
100
A,B
50
100
600O
load
X10 gain
X10 gain
ns
output voltage
(+ve)
(-We)
(-ve)
output current
A
A
5.5
B
B
2.5
A,B
A
A
-1
5.7
-1.9
-1.5
3.0
-3.0
-2.5
V
V
V
V
mA
6.5
input voltage
(-tve)
(-ve)
(-We)
B
B
(-ve)
Supply
45
A,B
A,B
A,B
(-ve)
Maximum
Maximum
Conditions
3
-3
V
V
V
V
Non-inverting
modes
line rejection
(-We)
AB
54
66
(-ve)
A,B
46
54
AB
Common mode
A,B
rejection
drift
dB
dB
9.85
l/A
dB
60.7
25
AV/C
OPERATING NOTES
The SL541 may be used as a normal, but non
saturating operational amplifier, in any of the usual
configurations (amplifiers, integrators etc.), provided
that the following points are observed
:
X3 NON
INVERTING
.
<
NX
Y3
^ -^
1
Positive supply line decoupling back to the output
load earth should always be provided close to the
device terminals.
2. Compensation capacitors should be connected
between pins 4 and 5. These may have any value
greater than that necessary for stability without
causing side offsets.
3. The circuit is generally intended to be fed from a
fairly low impedance (<1kQ), as seen from pins 6
and 9 - 100 Q or less results in optimum speed.
4. The circuit is designed to withstand a certain
degree of capacitive loading (up to 20pF) with
virtually no effect. However, very high capacitive
loads will cause loss of speed due to the extra compensation required and asymmetric output slew rates.
5. Pin 1
does not need to be connected to zero volts
except where the clipping levels need to be defined
accurately w.r.t. zero. If disconnected, an extra 0.5
volt uncertainty in the clipping levels results, but the
separation remains. However, the supply line rejection
is improved if pin 10can be left open-circuit (circuit Bonly).
FREQUENCY (MHz)
Fig.
3 Performance graphs - gain

2kCl/10pF)
82
v.
frequency (load
See operating note 2
"
SL541B
+-VE
OUT
\
'
\/
SLEW RATE O ER
10% T 3 85% PI
175
c c - pF
/\
J \
-VE
/
y
>
V|N
/
Fig.
4 Slew rate - X10 non-inverting mode

Input square wave 0.4V pip
t(20ns/DIV)
Fig.
a 4;
Output clipping
levels
- X10
non-inverting
mode
Input moderately overdriven, so that ouput goes into
_*
clipping both sides
INPUT SIIP
)pf
-VE
VE
\l
J
-VE
\i
VE
V
t
Fig.
Settling time
(20ns/ DIV)
- X10
non-inverting
mode
Fig.
Output clippings levels -X10 non inverting mode.

3V peak
Output goes from clipping to zero volts. V,
step, offset
+veor
ve.
CIRCUIT A
+MPUT
+INPUT
+1JV
+15V
SSiOp
ftn
rrn
rrn
DYNAMIC TEST CIRCUIT
RC>22n
Cc-0pF
c 'o. 8 Test circuits
83
SL541B
TEST CONDITIONS
AND
DEFINITIONS
Both slew rate and settling time are measures of an

speed of response to an input. Slew rate is an
inherent characteristic of the amplifier and is generally
less subject to misinterpretation than is settling time,
which is often more dependent upon the test circuit
than the amplifier's ability to perform.
Slew rate defines the maximum rate of change of
output voltage for a large step input change and is
related to the full power frequency response (fp) by the
amplifier's
relationship.
where E
is
2nfpE
the peak output voltage
Settling time is defined as the time elapsed from

the application of a fast input step to the time when the
amplifier output has entered and remained within a
specified error band that is symmetrical about the final
value. Settling time, therefore, is comprised of an initial
propagation delay, an additional time for the amplifier
to slew to the vincinity of some value of output voltage,
plus a period to recover from overload and settle within
Fig.
Non-saturating sense amplifier (30V/ \is for 5mV)

Note: the output may be caught at a pre-determined
level. (10-5 pin nos.J
the given error band.
The SL541
is
tested for slew rate
configuration.
"C
C
R|_
"
00
V*
TAMB
"
= 15
0^
2V
25 C
-^
<;
=
"^^^
cJr>C
cc 10
!
RC0
C=150n\ >**
III
COMP ENSATION
COMP ENSATION
, RC = 39
::-^5
lOpF
^s
;^
FREQUENCY
Fig. 10
84
SL541B open loop gain and phase
shift
v.
frequency
in
X10
gain
SL550D/G
SemlcoiMluctoi
^^.r Semlcomluctors
SL550 D
&G
LOW NOISE WIDEBAND AMPLIFIER

WITH EXTERNAL GAIN CONTROL
The SL550
is
a silicon integrated circuit designed for
use as a general -purpose wideband linear amplifier

with remote gain control. At a frequency of 60 MHz,
the SL550C noise figure is 1-8dB (typ.) from a 200 ohm
source, giving good noise performance directly from a
microwave mixer. The SL550 has an external gain
control facility which can be used to obtain a swept
gain function and makes the amplifier ideal for use
preamplifier
either in a linear IF strip or as a low noise
a logarithmic strip.
External gain control is performed in the feedback
loop of the main amplifier which is buffered on the
input and output, hence the noise figure and output
is
voltage swing are only slightly degraded as the gain
reduced. The external gain control characteristic is
wellenabling
a
specified with an accuracy of 1dB,
in
CAPACITIVE
output Voutput
vcc
DC16
Fig. 1 Pin
connections (top view)
APPLICATIONS
FEATURES
MHz
INPUT
jrf
defined gain versus time law to be obtained.

The input transistor can be connected in common
of
emitter or common base and the quiescent current
the output emitter follower can be increased to enable
driven.
to
be
loads
low impedance
200
INPUT
DECOUPLE
Bandwidth
Low
Noise Figure
Well- Defined Gain Control Characteristic
25dB Gain
40dB Gain
Low
Noise Preamplifiers
Swept Gain Radar
IFs
Control Range
Output Voltage 0.8Vp-p (Typ.)
VARIABLE ATTENUATOR
TRACKMG WITH VARIABLE

GAIN AMP
ALL CAPACITORS
R2
Fig.
2 Functional diagram
Mnf (WEECON TYPE CAPACITORS >
=30Q SEE OPERATING NOTE
Fig.
Test circuit
85
SL550D/G
f = 30Hz Vs = +6V, Rl = 2000, Ic = 0, Ri
= 7500, Tamb =
+25C
Value
Characteristic
Voltage gain
Gain control characteristic

Gain reduction at mid-point
Circuit
Min.
SL550G
SL550D
39
35
Both
SL550G
SL550D
SL550G
SL550D
SL550G
SL550G
SL550D
Max. gain reduction

Noise figure
Output voltage
Typ.
42
40
See note
10
44
45
25
25
2.0
3.5
3.0
2.7
0.15
0.3
11
SL550G
SL550G
SL550D
Ic
Ic
Vrms
Vrms
13
15
20
mA
mA
mA
Gain variation with supply voltage

Both
( 3dB
Both
125
MHz
Both
dB
30MHz)
dB/V
Gain variation with temperature

(see note 2)
= 0.24mA
= 0.2imA
Ic = 2.0mA
Ic = 2.0mA
Rs = 200O
Rs = 500
Rs 2000
Rl = oo
Ri = 750 o
Ri = oo
Ri = 750O
Ri = oo
Vs = 6 to 9V
dB
dB
dB
dB
dB
dB
dB
11
0.2
wrt
Conditions
dB
dB
20
Both
Both
Supply current
Max. Units
Tamb
= 55 to
+125C
NOTES
1
2.
The external gain control characteristic is specified in terms of the gain reduction obtained when the control
current (Ic)
from zero to the specified current.
This can be reduced by using an alternative input configuratio n (see operating note: 'Wide Temperature
Range').
OPERATING NOTES
Input Impedance
The input capacitance, which
60MHz,
is
increased
300 resistor in the emitter of the input transistor. This is

achieved by decoupling pin 13 and leaving pin 12
open-circuit. Gain variation is reduced from 3dB to
1dB over the temperature range 55C to +125C
(Figs. 6 and 7).
is
typically
12pF
at
independent of frequency. The input resistance, which is approximately 1 .5k at 1 0MHz, decreases
with frequency and is typically 500 ohms at 60MHz.
Low
Control Input
A low input impedance (=*25Q) can be obtained by

connecting the input transistor in common base. This is
achieved by decoupling pin 1 1 and applying the input
is
Gain control is normally achieved by a current into pin

2. Between pin 2 and ground is a forward biased diode
and so the voltage on pin 2 will vary between 600 mV
at Ic = 1 (iA to 800 mV at Ic = 2 mA. The amplifier gain
is varied by applying a voltage in this range
to pin 3.
To avoid problems associated with the
sensitivity of the
voltage and with operation over a wide
temperature range the diode should be used to convert
a control current to a voltage which is applied to pin 3
by linking pins 2 and 3.
control
Minimum Supply Current

If the full output swing is not required,
or if high
impedance loads are being driven, the current consumption can be reduced by omitting Ri (Fig. 3). The
function of Ri
is
to pin
Input Impedance
12 (pin 13 open-circuit).
High Frequency Stability

Care must be taken to keep all capacitor leads short
a ground plane should be used to prevent any earth
common between the input and output
circuits. The 30Q resistor (pin 14) shown in the test
circuit eliminates high frequency instabilities due to the
stray capacitances and inductances which are unavoidable in a plug-in test system. If the amplifier is
soldered directly into a printed circuit board then the
300 resistor can be reduced or omitted completely.
and
inductance
1 h-
to increase the quiescent current of the
vs <v
MINIMUM
output emitter follower.
NOISI E
CONFIGURATION
so
High Output Impedance
A high
impedance current output can be obtained by

taking the output from pin 6 (leaving pin 7 opencircuit). Maximum output current is 2 mA peak and the
output impedance is 350Q.
Wide Temperature Range
3
Z
<
'
so
10
I
86
rî v
i*
'C"2-0mA
30
40 50 SO
80
FREQUENCY (MHz)
The gain
variation with temperature can be reduced

at the expense of noise figure by including an internal
~>S^
:-om
30
Fig.
4 Frequency response
WO
SL550D/G
'
20dBm*n
FREO'SOMHz
CONTROL CURRENT
Fig.
K)mA
1mA
5 Gain
(l
c)
control characteristic
ic
FREC tUENCV- 60UHZ

OEFINEO GA M CONF GUfiATH
02 m A
c .VO.A
-55
-0
.20
-20
.40
TEMPERATURE
Fig.
Fig.
.80
.WW
.>*v
7 Voltage gain v. temperature (pin 13 decoupled for

improved gain variation with temperature - see operating
temperature (pin 12 decoupled,
Voltage gain v.
standard circuit configuration)
.60
CO
notes)
I
I
FREQUENCY ' SOMHl

SOURCE HWEDA NCE -2430 OHM!
-55
-40
-20
.20
Fig.
.60
.40
TEMPERATURE
.80
.100
.120
<C)
(SL550G)
87
SL550D/G
Fig.
9 Input and output impedances (Vs
0-
it
y_ 3
VD4
TR13
41
05/ i
Fig.
88
10 Circuit diagram
TR14
6V)
SL550D/G
APPLICATION NOTES
A wideband high gain configuration using two
The
SL550s connected in series is shown in Fig. 11.
first
stage
is
connected
in
common
emitter configura-
base circuit.
tion whilst the second stage is a common
achieved by the
Stable gains of up to 65 dB can be
is 5 to
proper choice of R1 and R2. The bandwidth
greater
130 MHz, with a noise figure only marginally
circuit.
than the 2.0 dB specified for a single stage
Fig.
13 Linear swept gain
circuit
K|4)
xt2)
LINEARISING
CIRCUIT
IW
(FIGI2I
HIFig.
M.L CAPACITORS WOOpF
Fig. 11
14 Square law swept gain
circuit
two-stage wide-band amplifier
A voltage gain control which is linear with control

shown in
voltage can be obtained using the circuit
which is negative
Fig 12 The input is a voltage ramp
the
drives
output
The
going with respect to ground.
(see Fig. 13).
control current pins 2 and 3 directly
strip are controlled as shown in
If two SL550s in the
linearising circuit,
Fig 14 with a linear ramp input to the
law (power gain v. time) will be obtained
a fourth power
over a 50 dB dynamic range.
Capacitors 1 0n
Gain 46dB
200Q)
Noise figure 2.0dB (RS
50Q)
Output power +5dBm (R1
Frequency response as SL550G
bandwidth)
Dynamic range 70dB (1 MHz
All
Fig.
12 Gain control linearising
circuit
Fig.
15 Applications example of wide dynamic range:

load amplifier with AGC using SL500 series
integrated
50Q
circuit.
89
SL550D/G

Storage temperature
Ambient operating temp.

Max. continuous supply
Voltage wrt pin 1
Max. continuous
AGC
Pin 2
Pin 3
90
55C to
40C to
+9v
current
1 0mA
1mA
+1 50C
+125C
SL560C
APLESSE
SL560C
300 MHz
LOW NOISE AMPUFIER
very
This monolithic integrated circuit contains three
biasing
high performance transistors and associated
components in an eight-lead TO-5 package forming a
300 MHz lownoise amplifier. The configuration employuse of
ed permits maximum flexibility with minimum
general-purpose
external components. The SL 560C is a
low noise, high frequency gain block.
0UIPUI CURRENT SET
CM8
FEATURES
(Non-simultaneous)
Gain up to 40 dB
Noise Figure Less Than 2 dB (Rs 200 ohm)
Bandwidth 300
EARTH
] INPUT
50APPllCATlONS
OUTPUT CURRENT SET
] INPUT
COMMON BASE CONFIGURATION
OUTPUT [
] INPUT
COMMON
MHz
Supply Voltage 2-1
xcct
5V (Depending on
EMIT! ER CONFIGURATION
] GAIN SET
^_
DP8
Configuration)
Low Power Consumption
Fig.
Pin connections (viewed from beneath)
APPLICATIONS
Radar
IF Preamplifiers
Infra-Red Systems
Amplifiers
in
Head
Amplifiers
Noise Measurement Systems
Low Power Wideband
Amplifiers
Instrumentation Preamplifiers
50 ohm Line Drivers

Wideband Power Amplifiers
Wide Dynamic Range RF Amplifiers
Aerial Preamplifiers for VHF TV and
FM
Radio
Fig.
2 SL560C circuit diagram
SU8VIS/BNC SOCKET
Fig.
3 PC layout for 50-
line driver (see Fig. 6)
91
SL560C
Frequency 30 MHz
Vcc6V
Rs
Ta
=
=
Rl = 50Q
25 C
Test Circuit
Fig.
Value
Characteristic
Units
Min.
Typ.
Max.
11
14
+1.5
250
17

Gain flatness

Output swing
Noise figure
(common
+5
emitter)
10
+7
dBm
+11
dBm
1.8
dB
dB
20
MHz -220 MHz
MHz
3.5
Supply current
dB
dB
Conditions
30
Vcc = 6V
Vcc = 9V J See
Rs = 200Q
1
Rs
F| 9-
= 50Q
mA
CIRCUIT DESCRIPTION
Three high performance transistors of identical geometry are employed. Advanced design and processing
techniques enable these devices to combine a low base
resistance (Rbb') of 1 7 ohms (for low noise operation)
with a small physical size
giving a transition frequency, fr, in excess of 1 GHz.
The input transistor (TR1) is normally operated in
Ta = +25-
common
PCjt
base, giving a well defined low input impedance. The full voltage gain is produced by this transis-
and the output voltage produced at its collector is

buffered by the two emitter followers (TR2 and TR3).
To obtain maximum bandwidth the capacitance at the
collector of TR1 must be minimised. Hence, to avoid
bonding pad and can capacitances, this point is not
brought out of the package. The collector load resistance
of TR1 is split, the tapping being accessible via pin 5. If
required, an external roll -off capacitor can be fixed to
(a)
b)
5dBm
tor
V"
FREQUENCY
Fig.
this point.
The large number of circuit nodes accessible from the

outside of the package affords great flexibility, enabling
the operating currents and circuit configuration to be
optimised for any application. In particular, the input
transistor (TR1) can be operated in common emitter
mode by decoupling pin 7 and using 6 as the input. In
this configuration, a 2dB noise figure (Rs= 200 Q.) can
be achieved. This configuration can give a gain of 35dB
with a bandwidth of 75 MHz (see Figs. 8 and 9)or, using
feedback, 1 4 dB with a bandwidth of 300 MHz (see Fiqs
S^C)
Ta = +25 C
Vcc
10and11).
(b)9V
Because the transistors used in the SL 560C exhibit a

high value of fr, care must be taken to avoid high
frequency instability. Capacitors of small physical size
should be used, the leads of which must be as short as
possible to avoid oscillation brought about by stray
inductance. The use of a ground plane is recommended.
FREQUENCY (MHz)
Fig.
Further
applications
information
is
avaiable
'Broadband Amplifier Applications' booklet.
92
(MHz)
4 Frequency response, small signal gain
in
the
5 Frequency response, output capability (loci of maximum

output power with frequency, for IdB gain compression)
SL560C
TYPICAL APPLICATIONS
Gain14dB
Bandwidth 220
200
Input
Fig.
SWR
MHz (P ut=1 mW, 50 Q)

MHz(P O ut=5mW,50n)
FREQUENCY
6 50 a line driver. The response
of this configuration
300 400
200
1.5:1
is
shown
Fig.
7 Input standing wave
ratio plot
(MHl)
of circuit
shown
in Fig.
in Fig. 4.
Vcc
Voltage gain
32dB at 6V
35dBat10V
Noise figure 1 .8dB (RS=200

Supply current 6mA at 6V
CI)
r-1
12mA at 10V
Bandwidth 75
Fig.
10
MHz (see Fig. 9)
FREQUENCY
Fig.
8 Low noise preamplifier
50
30
20
Mm
9 Frequency response of circuit shown in Fig. 8
,s
_-.
^
OUTPUT
1|
bl
...
\ \
U^
(al'
T4
SL
--
<
VCC
(al
6V
_-.
_.
_-.
Gain13dBatVcc=9V
1dB at 6 MHz and 300 MHz

Fig.
10 Wide bandwidth amplifier
Fig. 11
FREQUENCY
IMHi)
Frequency response of
circuit
shown
in Fig.
10
93
SL560C
Fig.
'
12 Three-stage directly-coupled high gain low noise amplifier
s^~~
^-""
^^
^
OUTPUT
V A'
TA= + 25 C
VCC
Irl
" ^bl\
*\\
Ibl
6V
Ic]
9V
Gain 13dB
Power supply current 3mA
Bandwidth 125
FREQUENCY
Fig.
13 Frequency response of circuit shown in
Fig.
12
o
!/>
300
T0
D p
60
70
60
90
100
TEMPERATURE
Fig.
110
120
(C>
15 Ambient operating temperature
v.
degrees centigrade

Supply voltage (Pin 4)
Storage temperature
-M5V
-55Cto150C(CM)
-55Cto125C(DP)
Junction temperature
Thermal resistance
Junction-case
Junction ambient
150C(TO5)125C(DIP)
60C/W (T05)
220C/W (T05) 230C/W (DIP)
Maximum power dissipation
See Fig. 1
-55C to +1 25C (TO5) at 100 mW
-55C to +100C (DIP) at 100 mW
94
MHz
Noise figure 2.5dB
(MHzl
Fig.
(RS=200n)
14 Low power consumption amplifier
SL561C
APLESSE
^W Semlcooducto
SL561C
ULTRA LOW NOISE PREAMPLIFIERS
noise
This integrated circuit is a high gain, low
preamplifier designed for use in audio and video systems
Hz. Operation at low frequencies
at frequencies up to
external components
is eased by the small size of the
6M
and the low 1// noise. Noise performance is optimised

impedances between 20Q and 1kQ making
the device suitable for use with a number of transducers
for source
tape
including photo-conductive IR detectors, magnetic
heads and dynamic microphones.
Fig. 1
APPLICATIONS
Audio Preamplifiers (low noise from low

impedance source)
Video Preamplifier
Preamplifier for use
in
Low
Cost
Infra-
Pin connections (viewed from the top)
FEATURES
60dB
0.8nV/VHz (Rs = 50Q)
High Gain
Low
Red
noise
6MHz
Bandwidth
Systems
0mW
(Vcc = 5V)

1 0V
Supply voltage
Storage temperature - 55C to + 1 25C
Operating temperature -55C to + 1 00C
5V
Vcc
Source impedance 50Q

Load impedance 10kQ
25C
Tamb
Units
Value
Characteristic
Min.
Typ.
Max.
57
60
63
Conditions
0/C
dB
Pin 6
0.8
nWHz
100Hz
kQ
Input capacitance
15
PF
Output impedance
50
Voltage gain
Equivalent input
noise voltage
Input resistance
Output voltage
Supply current
Bandwidth
Vp-p
3
2
to
6M Hz
See note 4
mA
3
|
MHz
95
SL561C
OPERATING NOTES
1.
Upper
cut-off frequency
The bandwidth of the amplifier can be reduced from
any desired value by a capacitor from pin 6 to
common
less
octave.
than
5m V.
ratings of the output transistor the resistor should not

less than200fi.
be
Noise performance
The equivalent input voltage for the amplifier is
in Fig. 7. From this the input noise voltage and
current generators can be derived. They are :5.
shown
=0.8nVA/Hz
in=2.0pA/VHz
en
Mf noise is not normally a problem, the knee

frequency being typically below 1 00Hz.
Flicker or
<
Fig.
Circuit diagram
su
8
III
10v
vcc
OUT
r-C
10k
; loon
"00n
f
Fig.
96
this
Driving low impedance loads

The quiescent current of the output emitter follower
is 0.5mA. If larger voltage swings are required into low
impedance loads this current can be increased by a
resistor from pin 8 to ground. To avoid exceeding the
The capacitors C2 and C3 (Fig. 4) determine the

lower cut-off frequency. C2 decouples an internal
feedback loop and if its value is close to that of 63 an
increase in gain at low frequencies can occur. For a
flat response either make C2 less than 0.05
C3 or make
C2 greater than 5 C1
3. Gain set facility
Provision is made to adjust the gain by means of a
resistor between pin 6 and the output. Gains as low as
10dB can be selected. This resistor increases the feedback around the output stage and stability problems can
result if the bandwidth of the amplifier is not reduced as
indicated in Note 1. Fig.6 shows recommended values
of C1 for each gain range. Since the input stage is a
40dB
4.
Low frequency reponse
than
input stage, rather than the output stage, determines

the maximum output voltage swing. For a distortion of
less than 10% the input voltage should be restricted to
ground. This is shown in Fig. 5. No degradation in

noise or output swing occurs when this capacitor is
used. The high frequency roll off is approximately 6dB/
2.
emitter stage without emitter degeneration
(for best noise) at values of gain less
6MHz to
Test circuit
Fig.
Typical application
SL561C
60
t
-LfiUIIopf
50
20pF
llllll
30
20
[H
100 k
FREQUENCY
Fig.
5 Gain
v.
(Hz|
frequency
AND BANOWIDTH (NOTE 3)_
10
ihiii
mum
I
1
II
llllll
"SET (Ohms)
Fig.
6 Gain
v. /?
20
40
60
80 100
2k
**t
0-6h 0-8k
SOURCE RESISTANCE Ul
Fig.
7 Noise
v.
source impedance
97
SL561C
98
SL565
^ A KLEwwE
Semiconductors
^V
ADVANCE INFORMATION
VO?.ocal Plessey Semiconductors Sales Office
oe?ee^^
for details of current status.
SL565C
1GHz WIDEBAND AMPLIFIER
The SL565
is
a low cost wide bandwidth amplifier featuring
and outputs and useful performance to

1GHz. Typical applications are in wideband amplifiers,
and communications.
ECM
instrumentation,
8]6MWW
differential inputs
MPUTC
7 ]
OUTPUT
<OV
MVEKTM6
5 ] INVERTING OUTPUT
INPUT [
DP 8
FEATURES
Fig. 1
Low Cost
Wide Bandwidth:
High Gain: 22dB
Differential Input
Pin connections
top view
GHz
and Output
+5V Supply
High Reverse Isolation

Supply voltage, Vcc +8V
Storage temperature -55C to +125C
Operating temperature -30C to +85C
Chip temperature +150C
Fig. 2
Test circuit
Tamb = +25 C. Test circuit Fig.2 except for differential gain measurements.
Vcc = 5.0V
Min.
Value
Typ.
Max.
Supply voltage
4.75
5.0
5.5
Supply current
30
50
70
mA
Characteristic
dB
dB
dB
16
Differential gain S21
21
16
Single ended gain
1dB gain compression

Noise figure
3rd order input intercept point
8
13
8
10
15
10
dBm
13
dB
-3.5
dBm
dBm
dBm
dBm
-9.5
2nd order input
intercept point
Reverse isolation pins 7 to 4
Reverse isolation pins 5 to 4
70
60
20
20
75
30
output
600
300
output power
1dB compression
-3
-2
Maximum
Maximum
for
+3.0
10-900MHZ
1GHz
1.3GHz
100MHz
500MHz
1GHz
12
17
12
-19
-7
Conditions
Units
dB
dB
dB
dB
dB
dB
Input
power
at
500MHz
500 source
50MHz
200MHz
500MHz
500 and 400MHz inputs
= 50MHz
= 50-100MHZ
f = 500MHz
f = 1GHz
f = 100MHz
f = 1GHz
f< 500MHz
f = 500MHz to 1 GHz
f
mV p-p
mV p-p
dBm 1GHz
dBm 500MHz
99
SL565
OPERATING NOTES
The SL565
a general purpose wideband gain block,

applications. The frequency response and
impedance plots are shown in Figs. 3 and 4
suitable for
input
is
many
respectively.
wideband high frequency circuits, the SL565

should be used with short leads to its associated
components, and a ground plane printed circuit board layout
is recommended. There are advantages in
using the top
surface of the PCB as the ground plane with cage jacks e.g.
Cambion 450-3750-01-06-00 or similar sockets for each
device pin, as then chip capacitors can be installed with
Like
all
minimum
lead lengths Ion top of the board. Resistors should

be miniature carbon composition types (metal oxide and
carbon
film
types often
have an appreciable parasitic
inductance).
The high reverse

driving High Speed
isolation
Divider
makes the SL565

integrated
ideal for
in both
5 shows a
circuits
frequency counters and synthesisers, and
Fig.
typical application in a 100MHz to 1000MHz -MOprescaler

for a frequency counter. This prescaler operates
with
inputs
as low as
70mV rms
over the whole frequency range of the
device.
Other applications for the SL565 include oscillators using

SAW devices as frequency determining elements, where the
wide bandwidth of the SL565 enables high frequency
oscillators to be produced at minimum cost.
FREQUENCY
Fig. 3
Fig.4 Single-ended input
100
Typical frequency response,
SL565C
impedance of SL565C, normalised to 5CK1. Vcc =5V, Tamb
+25" C, load
= 5CXI
frequencies in MHz.
SL565
Fig.5
1GHz
prescaler
INVERTING OUTPUT
INVERTING INPUT
Fig.6
SL565C
circuit
diagram
101
SL565
102
SL610/SL611/SL612C
M Wk rLEwwE
NQr Semiconductors
SL610C, SL611C
& SL612C
RF/IF AMPLIFIERS
ampThe SL61 OC, SL61 1 C and SL61 2C are RF voltage
lifierswithAGCfacilities. The voltage gains are 10, 20 and

50 times respectively and the upper frequency response
according to type.
varies from 1 5 MHz to 1 20
MHz
FEATURES
Wide
AGC
Range: 50dB
Easy Interfacing
Integral Power Supply RF Decoupling
CM8
Fig. 1 Pin
connections (bottom view)
APPLICATIONS
RF
Amplifiers
IF Amplifiers

Supply Voltage:
Voltage Gain.
Supply voltage: 1 2V
Storage temperature: -55Cto +125C
6V
20dB
to
34dB
"ffl
~in
CONDUCTANCE
SUSCEPTANCE
SL610C
II
jf
--X
rit
Jf
JT
it
TT
JT
TT
i
1
SL610C
/
\
TT
tt
~- ""
...
...
it
TT
if
if
if
"
\\
SL612C
II
'"^ r
s L611C
/
,
rSL6!2C
if
Fig.
IE
2 Block diagram
FREQUENCY (MHz)
Fig.
3 Input admittance with olc output (Gu)
103
SL610/SL611/SL612C
Test conditions (unless otherwise
stated):
Supply voltage Vcc: 6V

Ambient temperature: -30C to +85C
Test frequency: SL61 OC 30MHz
SL611C 30MHz
SL612C 1.75MHz
Characteristic
Circuit
(_
Mm.
Supply current
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
SL612C
SL610C
SL611C
Voltage gain
Cut-off frequency
( 3dB)
Noise figure
Value
Typ.
18
24
32
85
50
10
Max. output signal (max. AGC)
AGC current
SL610C
SL611C
SL612C
Max.
15
15
20
20
3.3
20
26
34
120
80
22
Conditions
mA
mA
28
36
40
40
60
}
'
MHz
MHz
MHz
dB
dB
dB
Rs=300fi)
Rr = 300O>
Vrms
250
50
50
mVrms
dB
dB
dB
0.15
open
circuit
attest
,
frequenc
y
RL = 150Q(SL610C/611C)
RL = 1.2kfi(SL612C)
mA
0.6
pin 3
RS = 50Q
R|_ = 500Q
Tamb = 22C
RS=800oj
1.0
70
No signal,
>
dB
dB
dB
15
4
4
3
SL612C
Max. input signal (max. AGC)
AGC range
Units
Pin 7
0V to 5.1V
J
Current into pin 7 at 5.1V
APPLICATION NOTES
increased there is a reduction in

gain as shown in Fig 6
This reduction varies a little
with temperature.
Input circuit
L611C
SL612C are norm ay *ed
with pins 5 and f
6 connected together and with the in D ut
P
connected via a capacitor as shown
in Fig 2
wTSin^S
f.
IOOMHzKK^^"
thV^rvnf^
c
the source is
69
6 between 30MHz a "d

S L61 1C only) and is shown in Fig. 3.
If
^F'
inductive
it should be
shunted by
V a 1kO ree
sistor to prevent oscillation

at einPUtCirCUitWithimprovednois
shSwn1n%
Typical applications
The circuit of Fig. 7 is a general purpose RF

preamplifier.
The voltage gain (from pin 5 to pin 3) is
shown in Fig 8
*3i/
9MHz
'?
it
the IF section of a sim P |e

has a gain of 100dB.
SSB
transceiver. At
"
e9êis
60
"111
Ill
--- .
!ESISTANC
J-M-
SL6
<-/
EACTANC
'.III
60
jSL&l'ocJ
"71
Jl
1
43
~TT
S16I2
..Jl"^
20
>
SC.6I2
T
'
J~n
'
If
"tr
11
SL611C
*% Ua: ...u
c!
UJ
<
Fig.
"""
""
-20
f
4 Alternative input circuit
Output circuit
The output stage is an emitter follower and has a negative output impedance at certain frequencies
as shown in
Fig. 5.
To prevent oscillation when the load is capacitive

resistor should be connected in series with
the
a 47fi
III
-,n
-60
-80
tro
tttt
TT"
tttt
ntt
-100
output.
III
fflt
JJJ
4T
111
AGC
TT
When pin 7 is open circuit or connected to a voltage less

than 2V the voltage gain is normal. As the AGC
voltage is
.1
II
_
1
t'
II
"IT
:
III
FREQUENCY (MHz)
Fig.
104
Tr
TT
"TT
ittt
Tt
Tr
Tr
5 Typical output impedance with s/c input{G22)
"
'
'
'
SL610/SL611/SL612C
SL6 2C
SL6I0C
AGC
Fig.
SIGNAL
Fig.
(V)
6 AGC characteristics
RF preamplifier
typical)
U)
III
Hi
SI612C
30
L_l
SL6KC
<
SL610
Hi
1000
Fig.
II
Fig.
FREQUENCY
9 IF amplifier using SL612
(MHz)
Typical voltage gain
{Rs=50Cl)
105
SL610/SL611/SL612C
106
SL621C
^^F Semiconductors
SL621C
AGC GENERATOR
The SL621C
for
use
SSB
in
is
an
AGC generator designed specifically
receivers
in
conjunction with the SL610C,
SL61 1C and SL61 2C RF and IF amplifiers. In common with

other advanced systems it generates a suitable AGC voltage
directly from the detected audio waveform, provides a 'hold'
period to maintain the AGC level during pauses in speech,
and is immune to noise interference. In addition it will
smoothly follow the fading signals characteristic of HF

communication.
When used in a receiver comprising one SL610C and
one SL61 2C amplifier and a suitable detector, the SL621
will maintain the output within a 4dB range for a 110dB
range of receiver input signal.
FEATURES
All
Time Constants Set
Externally
Easy Interfacing
Compatible with SL61 0/61 1 /61
APPLICATIONS
SSB
Receivers
Test Equipment

Supply voltage: 6V
Supply current:
Fig.
3mA
2 Block diagram
Storage temperature:

Supply voltage Vrx = 6V
Test frequency: 1kHz
Test circuit as Fig. 2
-55Cto+125C
Value
Min.
Supply current
Cut-off frequency ( 3dB)
Input for 2.2V
Input for 4.6V
DC output
DC output
Maximum output voltage
'Fast' rise
'Fast'
3
9
time
ti
'Slow' rise time t3
Hold collapse time

Hold time ts
Max.
3.1
4.3
11
11
16
12
20
700
230
55
150
150
65
0.75
500
70
20
200
200
mA
No signal
kHz
5.1
350
decay time t2
Typ.
AC ripple on output
Input resistance
Output resistance
Conditions
Units
Characteristic
mVrms
mVrms
V
mVpk-pk
1kHz, output open
circuit
Q
Q
100
330
300
150
ms
ms
ms
ms
1.0
1.25
to 50% full output

100% to 36% full output
Time to output transistion
point
107
SL621C
APPLICATION NOTES
The
The SL621 C consists of an input AF amplifier coupled to

DC output amplifier by means of two detectors having
short and long rise and fall times respectively. The time
more sensitive.
Input signals greater than approximately 4mV rms will
actuate a trigger circuit whose output pulses provide a
discharge current for C2.
By this means the voltage on C2 can decay at a maximum
rate, which corresponds to a rise in receiver gain of 20dB/s.
Therefore the AGC system will smoothly follow signals
which are fading at this rate or slower. However should the
receiver input signals fade faster than this, or disappear
completely as during pauses in speech, then the input to
the AGC generator will drop below the 4mV rms threshold
and the trigger will cease to operate. As C2 then has no
discharge path, it will hold its charge (and hence the output
AGC level) at the last attained value. The output of the short
time constant detector will drop to zero in time t2 after the
disappearance of the signal.
controls t3, t4;
C3 controls ts.
The supply must either have a source resistance of less

than 2Q at LF or be decoupled by at least SOOîF so that it is
not affected by the current surge resulting from a sudden
input on pin 1
In a receiver for both
and SSB using an SL623C
detector/carrier
generator, the AGC outputs of the
AM
AGC
SL621 C and SL623C may be connected together provided

that no audio reaches the SL621 C input while the SL623C
is
controlling the system.
AGC lines may require some RF decoupling but the total

capacitance on the output should not exceed
the impulse suppression will suffer.
SPEECH
NOISE BURST
AUDIO
OUTPUT
ENVELOPE
L
<f-X
AGC VOLTAGE
THE LARGER OUTPUT
CONTROLS THE SYSTEM
Fig.
3 Dynamic response of a system controlled by SL621C
H
SI 621
Fig.
108
4 SL621C used
c
i
to control
SSB
|l__
't1t
AGC generator
>
H>HSH>HEf
m*
the trigger
If signals reappear during

ts, then C3 will recharge and
normal operation will continue. The C3 recharge time is
made long enough to prevent prolongation of the hold time
by noise pulses.
Fig. 3 shows how a noise burst superimposed on speech
will initiate rapid AGC action via the short time constant
detector while the long time constant detector effectively
remembers the pre-noise AGC level.
The various time constants quoted are for C1 = 50uF and
C2 = C3 = 1 00 \iF. These time constants may be altered by
varying the appropriate capacitors. C-| controls t-| t2; C2
constants of these detectors are set externally by capacitors

on pins 5 (C| ) and 3 (C2).
The detected audio signal at the input will rapidly establish
an AGC level via the fast' detector time in ti (see Fig. 3).
Meanwhile the long time constant detector output will rise
and after t3 will control the output because this detector is
IN
When
PAUSE
trigger pulses also charge C3.
pulses cease, C3 discharges and after ts C2 is discharged

rapidly (in time U) and so full receiver gain is restored. The
hold time, ts is approximately one second with C3
1 0Op F.
c
;
receiver
5000pF
or
SL621C
NORMAL AGC
-
SL611 SL61 2C
INPUT (mVrms)
Fig.
5 Transfer characteristic of SL621C {typical)
of the AGC output may

a receiver. Possible solutions are shown in Figs.6
Under some conditions.overload

occur
and
in
7.
Fig.6
Fig.
109
SL621C
110
SL623C
SL623C
AM DETECTOR, AGC AMPLIFIER & SSB DEMODULATOR
The SL623C is a silicon integrated circuit combining the
detector and AGC
functions of low level, low distortion
generator with SSB demodulator. It is designed specially
for use in SSB/AM receivers in conjunction with SL610C,
AM
and is independent of the depth of modulation

used. Its response is fast enough to follow the most rapidly
fading signals. When used in a receiver comprising one
SL610C and one SL612C amplifier, the SL623C will
maintain the output within a 5dB range for a 90dB range of
receiver input signal.
The
detector, which will work with a carrier level
down to 1 0OmV, contributes negligible distortion up to 90%
modulation. The SSB demodulator is of single balanced
form. The SL623C is designed to operate at intermediate
frequencies up to 30MHz. In addition it functions at frequencies up to 1 20MHz with some degradation in detection
carrier signal
AM AUDIO OUTPUT
OV
\
SL61 1C and SL61 2C RF and IF amplifiers. It is complementary to the SL621C SSB AGC generator.
The AGC voltage is generated directly from the detected
INPUT
oc orr output
ID
2
[oe
SSB AUDIO OUTPUT
AGC PHASE CORRECTION
30
I
Vo
7
6
o
AGC OUTPUT
Vtc^
\\
AGC AMP INPUT
CARRIER INPUT
AM
CM10
Fig.
Pin connections (bottom view)
efficiencies.
FEATURES
Negligible Distortion
Supply Voltage: 6V
Easy Interfacing
Maximum
Fast
Frequency:
30MHz
Response Time
APPLICATIONS
AM SSB
Receivers
-55C to +125C
Test Equipment
Fig.
2 block diagram
111
SL623C
Supply voltage Vcc = 6V
Ambient temperature = -30C
to
+85C
Value
Characteristic
Min.
Supply current
Input
impedance
SSB
audio output
Typ.
Max.
Units
11
mA
Q
No signal,
mVrms
Signal input
800
22
30
47
Conditions
Pins
6,
open
Pin 4
20mV rms 8 1 .748

input 100mV
MHz. Ref. signal

@1.750 MHz
AM audio output
43
55
67
mV rms
Signal input
125mVrms@ 1.75MHz
modulated to 80%
AGC
range (Note
dB
1)
Initial
signal input
at
kHz
125mV rms
at
1.75MHz
modulated to 80% at 1 kHz. Output set to 2.0V with

10kQ potentiometer between Pins 2 & 5.
NOTES
1
The
AGC
range
is
the
change
in
input level to increase
AGC output voltage from
2.0V
to 4
6V
APPLICATION NOTES
AGC Generator
Pin 3, the AGC amplifier
phase correction point should

to ground by a 1 microfarad capacitor (C4),
keeping leads as short as possible. The value of C4 is quite
critical, and should not be altered: if it is increased the
increased phase shift in the AGC loop may cause the receiver to become unstable at LF and if it is reduced the
modulation level of the incoming signal will be reduced by
be decoupled
fast-acting
AGC.
The AGC output (Pin 4) will drive at least two SL61 0/1 1 /
2 amplifiers. The SL623AGC output is an emitter follower
similar to that of the SL621 C. Hence the outputs of the two
devices may be connected in parallel when constructing
1
AM/SSB systems.
Less signal is needed to drive the SSB demodulator than
the
detector. In a combined AM/SSB system, therefore,
the signal will automatically produce an SSB AGC voltage
via the SL621 C as long as a carrier (BFO) is present at the
input to the SSB demodulator of the SL623C. The AGC
generator of the SL623 will not contribute in such a con-
AM
figuration.
For AM operation the BFO must be disconnected from

the carrier input of the SSB demodulator. In the absence of
an input signal, the SL621C will then return to its quiescent

state. To switch over a receiver using the SL623C from
SSB to AM operation it is therefore necessary to turn off
the BFO and transfer the audio pick-off from the SSB to the
AM detector.
Neglecting to disconnect the SSB carrier input during

AM operation can result in heterodyning due to pick-up of
carrier on the input signal. In some sets different filters are
used for AM and SSB; these will also need to be switched.
The 10 kilohm gain-setting preset potentiometer is
112
adjusted so that a DC output of 2 volts is achieved for an

input of 1 25mV rms. There will then be full AGC output from
the SL623C for a 4dB increase in input. A fixed resistor of
1 .5 kilohms can often be used instead of the
potentiometer.
SSB
Demodulator
The carrier input
is applied to Pin 6, via a low-leakage

should have an amplitude of about 1 0OmV rms
and low second harmonic content to avoid disturbing the
DC level at the detector output.
Pin 8 is the SSB output and should be decoupled at RF
by a 0.01 microfarad capacitor. The output impedance of
the detector is 3 kilohm and the terminal is at a potential of
about + 2V which may be used to bias an emitter follower if
a lower output impedance is required. The input to the
audio stage of a receiver using an SL623C should be
switched between the AM and the SSB outputs - no
attempt should be made to mix them. Since the SL621C is
normally used in circumstances where low-level audio is
obtained from the detector, the relatively high SSB audio
output of the SL623C must be attenuated before being
applied to the SL621C. This is most easily done by connecting the SL623C to the SL621C via a 2 kilohm
resistor in series with a 0.5 microfarad capacitor.
capacitor.
It
Input Conditions
The input impedance is about 800 ohms in parallel with

5pF. Connection must be made to the input via a capacitor
to preserve the
bias. An input of about 1 25mV rms is
required for satisfactory carrier
performance and
DC
AGC
20mV rms for SSB detection. Normally, the

will cope
with this variation but in an extreme case a receiver
using
an SL623C and having the same gain to the detector in
AGC
both
to
AM and SSB modes will be some
AM.
0dB
less sensitive
SL640/SL641
iY
Semteonfliictoi
Semiconductors
SL640C & SL641C

DOUBLE BALANCED MODULATORS
modulators
The SL640C and SL641 C are double balanced
up to
intended for use in radio systems at frequencies
(Pin
75MHz The SL640 has an integral output load resistor
follower output (Pin 6) whereas
5) together with an emitter
drive
current
a
the SL641 has a single output designed as
to a tuned circuit.
CM8
FEATURES
No
External Bias
Networks Needed
Fig. 1 Pin
connections {bottom view)
Easy Interfacing
Choice
of Voltage or Current
Outputs
APPLICATIONS
Mixers
In
Radio Transceivers
Phase Comparators
Modulators
CARRIER O
SIGNAL O
\\^*f
|Mo
1
'

Supply Voltage: 6V
Conversion Gain:
OdB
Maximum
200mV rms
Inputs:
500
%
Fig.
2 Block diagram (SL640C)

Supply voltage 9V
Storage temperature: -55C to +1 25C
RL <
I
=
Fig.
10n
SOOn
|Z L |=BOOi
/777
3 Block diagram (SL641C)
113
SL640/SL641
Supply voltage Vo-: 6V
Characteristic
Value
Circuit
Units
Min.
Supply current
Conversion gain
Conversion transconductance
Noise figure
Carrier input
SL640C
SL641C
SL640C
SL641C
SL640C
SL640C
input voltage
Signal leak
Carrier leak
Max.
12
10
17
13
+3
dB
2.5
3.5
mmho
-3
1.75
impedance
Signal input impedance
Maximum
SL640C
SL641C
SL640C
SL641C
Typ.
Conditions
mA
mA
10
dB
kO
500
kO
mVrms
mVrms
210
250
-30
-18
-30
20
dB
dB
<
/
(
Signal leak
-18
-25
SL641C
SL641C
Carrier leak
-12
dB
dB
-12
>
<
/
(
Intermodulation products
SL640C
-45
-35
dB
SL641C
-45
-30
dB
70m V rms, 1.75MHz

100mV rms, 28.25 MHz
30MHz
Signal: 70m V rms, 30MHz
Carrier: 100mV rms, 28.25 MHz
Signal:
Carrier:
Output:
1.75MHz
Output:
Signal 1:42.5mV rms, 1.75MHz

Signal 2: 42.5mV rms, 2MHz
Carrier: 100mV rms, 28.25MHz
Output: 29.75MHz
{Signal 1 42.5mV rms,

:
Signal2:
42.5mV
30MHz
rms, 31
MHz
Carrier:100mV rms, 28.25MHz

Output:
APPLICATION NOTES
The SL640C and SL641C
and output
coupling capacitors which normally should be
chosen to
present a low reactance compared with the input
and output
impedances (see Electrical Characteristics). However for
minimum
require
input
carrier leak at high frequencies the signal

input
output should not be used to drive capacitive

loads as emitter
followers act as detectors under such
circumstances with
resultant distortion
Fig.
circuit.
114
ohms
to ground.
The
4 Signal and carrier leak adjustment
and carrier leak may be reduced by altering the bias

carrier and signal input pins, as shown in
Fig.4 With
Signal
is
a voltage
and the other

is the emitter of an emitter
follower connected to the first
output. The output on pin 6 requires
a discrete load resistor
of not less than 1500
and harmonic generation. Frequency-
shaping components may be connected to the

voltage
output and the shaped signal taken from the emitter
follower
The AC load should not be less than 250 ohms
should be driven from a low impedance source,

in which
case the signal input capacitor reactance
should be
comparable with the source impedance. Pin 2 must
be
decoupled to earth via a capacitor which presents the lowest
possible impedance at both carrier and signal
frequencies.
The presence of these frequencies at Pin 2 would give rise
to
poor rejection figures and to distortion.
The output of the SL641C is an open collector. If
both
sidebands are developed across the load its
dynamic
impedance must be less than 800 ohms. If only one
sideband
is significant this may be
raised to 1600 ohms and it may be
further raised if the maximum input
swing of 200mV rms is
not used. The DC resistance of the load
should not exceed
800 ohms. If the circuit is connected to a +6V supply and the
load impedance to +9V, the load may be
increased to 1 8
kilohms at AC or DC. This, of course increases the
gain of the
There are two outputs from the SL640C; one

source of output impedance 350 ohms and 8pF
3.75MHz
emitter follower
on the
earner but no signal R1
similar
signal
of R2.
is adjusted for minimum

carrier leak
is connected to the carrier input
and with
carrier present, signal leak is minimised by means
network
and
SL650/SL651B/C
APLESSEY
^W Semiconductors.
SL650B&C SL651B&C
MODULATOR/PHASE LOCKED LOOP CIRCUITS FOR MODEMS
are versatile integrated circuits capable of
The SL650/1
performing
modulation functions (AM,
PSK,
FSK,
FM,
SCAM,
PAM,
common
the
all
PWM,
SHSNAl
wide variety of phase-locked

SL650 or SL651, with all
to
parameters accurately controllable; they can also be used
generate precise waveforms at frequencies up to 0.2MHz.
delta-modulation, etc.).
SLMOWa
LOOP***
tone-burst,
loops can be realised using the
The
~xssr
'
~^
]
a
f
accurate and stable variable frequency

programmable over a wide range of frequency
highly
oscillator
is
direct
by voltage, current, resistor or capacitor. In addition
facilitated by
selection of one of four spot frequencies is
irdidj dj
EF
VFO VFO
EQO/P
rrn-rrrrcr
ill ill
"
Fj
MMI EAKTH
dj di dj
..
U||J
.4*1
f|
TIMING
tfl.
Iument
INPUT
DG24
standard
using the on-chip binary interface, whrch accepts
'1' input currents.
logic levels at very low logic
The
its
maintain lock range
in
input requiring only

a typical
ImV
input to
phase-locked loop. The
programmable from zero to over 2mA by

an external resistor or current input, and the gain is
voltage current or resistance programmable from
FEATURES
is
zero to greater than 10,000.

auxiliary amplifier with a voltage gain of, typically,
An
5000
to
is
incorpated
interface
auxiliary
25nA),
to
in
the
SL650
specified
amplifier
fast
features
for use
levels
and
low
bias
when
it is
required
impedances. The
current
(typically
recovery from overload, and a short-circuit
output current of 7.5mA.
The
Pin connections (top view)
input voltage range.
limiting amplifier at
current output
Fig. 1
input phase comparator has a wide

It has a high gain
differential
common mode
auxiliary
amplifier
VFO
Frequency Variable Over
With
Same Capacitor:
VFO
Temperature Coefficient:
Types 20 ppm/C Max.
B'
Linearity
00: 1
C Types 20 ppm/C Typ.

Supply
VFO
sensitivity
20 ppm/% Typ.
Phase-Continuous
at Transitions
Binary Interface
Phase Comparator O/P Can Swing

is
omitted from the SL651.
Range
02%
to
Supply
Voltages
On-Chip
Auxiliary Amplifier
(SL650)
APPLICATIONS
Modems
Modulators
Demodulators
Tone Decoders
Tracking Filters
Waveform Generators

6V
Supply Voltages
Operating Temperature Range -55C to +125C
115
SL650/SL651B/C
ELECTRICAL CHARACTERSTICS
Supply voltage 6V
Temperature Ta +22C 2C)

Value
Characteristics
Pins
Min.
Supply current Ice
Units
Max
Typ.
17,19
mA
%
Conditions
Variable frequency oscillator
frequency offset error

Normal mark/space ratio
Initial
Temp,
+3
1.00
1.02
coefficient of frequency
Frequency variation with supplies

Voltage at timing current inputs
VFO output,
VFO output,
Max.
-3
0.98
20
20
10
17, 19
6, 7, 8,
'low' state
'high' state
freq. of oscillation
See note
ppm/%
mV
See note 2
V
V
MHz
0.2
+ 1.1
_
ppm/C
+1.3
0.5
R L >10kS2
Binary inputs
V in
V in
to guarantee logic 'low'
10 11
to guarantee logic 'high'
10, 11
Input current
+0.6
V
V
0.25
mA
V in
mV
v out = 0V
V in =0V
+2.4
10, 11
0.05
See note 3
= +3.0V
Phase comparator
Differential l/P offset voltage
Input bias current

Differential input resistance
Common mode
l/P voltage range
Differential l/P to limit (AC)
Output current
Current gain (pin 22 to pin 21
Transconductance, O/P/diff.l/P
Output voltage,
Output current
23,24
23,24
23,24
23,24
23,24
21,22
21,22
2
0.05
100
kfi
V
1.0
10
+ 1.0
+2.0
5.0
10
+250
21,23,24 +100
linear range
HA
2.5
21
mV rms
mA
_
mA/V
V
MA
V
V
+5.5
21
Phase comparator l/P 'low'
-4
-0.2
Phase comparator l/P 'high'
+ 1.9
+5.3
See note 4
l
22 = 250/jA
See note 5
See note 5
22
=0
Auxiliary amplifier (SL650 only)

13,
14
+2
Input bias current
13,
14
0.025
Differential l/P resistance
13,
14
0.2
13,
14
Common mode
l/P voltage range

Voltage gain (13-14) to 15
13,14,15 1000
Output voltage range

Output current limit
15
15
4
4
r Lc^T^
iI
Wpi^lhr+0 6V
The
'low' state
is
eS f r timi " 9
CUrremS
in
the ranQe
Vout = 0V
;uA
Vin
=0V
Mfi
V
5000
4.8
6.5
R L >2k2
mA
12
*"
2(m tD 2mA and With the relevant
^cTrnXttf^hwT ^
SJ9n
'
~"" < **""* of
input selected ln the ""selected state the voltage

'
* *" transC " ductance *** when the signal

Supply voltages
7.5V
Storage temperature
-55to+175C
-55to+125C
Input voltages
116
mV
maintained when the inputs are open-circuited.

if the output (pin 21 ) voltage-limits first
Limiting will occur earlier

C
o u"put to?
SUPPlV VOlta96S
0.5
Not greater than
supplies
is
input
is
positive
and the
VFO
SL650/SL651B/C
Fig.
Circuit diagram
negative supply then the
OPERATING NOTES
Basic
VFO
of SL650/SL651
and the
VFO
frequency
Relationships
f
The VFO free-running frequency is inversely proportional

pins 4
to the value of the tuning capacitor C, connected to
and 5, and directly proportional to the VFO timing current
(see Fig. 3). Four current switches, controlled by TTLcompatible logic inputs on pins 10 and 11 select a
combination of external resistors (connected to pins 6, 7, 8
and 9) which determine the VFO timing current. When both
0V
logic inputs are low, open-circuit, or connected to
however, then only the current switch associated with pin 7 is

closed, the VFO timing current is then determined solely by
the value of one resistor (R2 in Fig.3), and by the negative
voltage connected to that resistor.
the
In this simplified configuration, as shown in Fig.4
frequency is determined by the relationship.
VFO
can be voltage-controlled,
will be:
V-
CR V c
supply
where V- is the chip and timing resistor negative
and V c is the control voltage connected to pin 3
J^L
fltRFl
CURRENT SWITCHES
VFO
IVjl
(hO-D-D
X
J_ Vr
CR'V 3
where
f
If
is
in
kHz,
Fig.
volts,
in
the timing resistor
is
in
fiF
and R
in
returned to the
3 VFO and binary
VE
interface
kI2.
VFO
VFO GAIN
INPUT = V R
negative supply (pin 3), then
and
CR
Pin 3 is normally connected to the chip negative

separate
supply; if however, pin 3 is connected to a
.
a
V3
Fig.4
= V- OR CONTROL WLTAGE Vc
VFO basic configuration
117
SL650/SL651B/C
The timing current should be between 2QuA and
2mA,
corresponding to a value for R between
3kJ2 and 300kJ2
with supplies of 6V. For accurate
timing, CR should be
greater than 5ps.
I
Phase Comparator
The phase comparator parameters are defined as
When the binary interface is used as shown in Fig.3 the

VFO free-running frequency is dependent on the logic input
states,
as
shown
Table
in
Overall transconductance
Pin 11
LO
LO
The input
Timing
VFO
Pins
Frequency
(V 24
HI
LO
HI
v24 - V 2
6&7
- V23
amplifier will limit
exceed
5mV
when the peak input

is recommended that
(typ.). It
R L is kept below 5kS2 to avoid saturating the output and

introducing de-saturation delays.
CRi
LO
1.
Overall voltage gain =
KnlO
CRj
CR]
1
CR 3
HI
HI
Table
8&9
CR 3
CR 4
connected between pins 1 6 and 1 5 will give compensation

down to a closed loop gam of unity. The output is short
protected but
less than
118
2k
Binary interface relationship!
Internal compensation provides stability down to

a
ctoeed loop gain of typically 20dB. A 30pF capacitor
circuit
is
follows
(see Fig.5):
not recommended for driving loads
Fig.
5 Phase comparator
SL652C
Semiconductors
SL652C
MODULATOR/PHASE LOCKED LOOP
The SL652C
performing
common
modulation functions 1AM,
PWM, tone-burst,
PSK,
wide variety of phase-locked
FSK,
FM,
SCAM,
PAM,
of
a versatile integrated circuit capable
is
the
all
delta-modulation, etc.).
all parameters
loops can be realised using this device, with
generate
accurately controllable; they can also be used to
waveforms
precise
The
highly
at frequencies
accurate
and
up to 0.2MHz.
stable
variable
TIMING CAPACITOR
of frequency
oscillator is programmable over a wide range
direct
voltage, current, resistor or capacitor. In addition
by
selection of one of four spot frequencies
is
LOOP GAIN CONTROL
facilitated
by
PHASE COMPARATOR OUTPUT

TIMING
CURRENT
INPUTS
differential
common mode
EARTH
standard
using the on-chip binary interface, which accepts
input currents.
logic levels at very low logic
The
([
frequency
input phase comparator has a wide

It has a high gain
BINARY INPUTS
input voltage range.
limiting amplifier at
maintain lock range
its
input requiring only
in
1mV
input to
a typical phase-locked loop.
The
programmable from zero to over 2mA by

voltage
an external resistor or current input, and the gain is
- current - or resistance - programmable from zero to
current output
is
DG 16
greater than 10,000.

Fig. 1 Pin
connections (top view)
FEATURES
APPLICATIONS
VFO
Frequency Variable Over 100:
Range
With Same Capacitor: Linearity 0.2%

VFO Temperature Coefficient: 20 ppm/C
Typ.
Supply sensitivity 20 ppm/% Typ.
Modems
VFO
Tracking Filters
Waveform Generators
Phase-Continuous
at Transitions
Binary Interface
Modulators
Demodulators
Tone Decoders
Stable Current-Controlled Oscillators

Supply Voltages
Operating Temperature
Range
Supply Currents
+6V
0Cto + 70C
1 .5mA typ.
+7.5V
-55 to+175C
-55 to +1 25 C
Input voltages
Not
Supply voltages
Storage temperature
greater than supplies
119
SL652C
Test Conditions (unless otherwise stated) :
Supply voltage: 6V
TA r+25C5C
Value
Characteristics
Pins
Units
Min.
Typ.
Conditions
Max.
Variable frequency oscillator

Initial
frequency offset error
Normal mark/space
ratio
-3
+1
+3
0.98
1.00
1.02
Temp,
coefficient of frequency
Frequency variation with supplies
11,12
Voltage at timing current inputs

Max. freq. of oscillation
4, 5, 6, 7
20
20
10
ppm/C
0.5
MHz
ppm/%
mV
Binary inputs
V in
V in
to guarantee logic 'low'

to guarantee logic 'high'
8,9
8,9
8,9
Input current
+0.6
V
V
0.25
mA
+2.4
0.05
See note 3
V in
= +3.0V
Phase comparator
15,
Input bias current
15,16
Differential input resistance
15,
16
Common mode
15,
16
l/P voltage range
Differential l/P to limit
(AC)
Output current
Current gain (pin 14 to pin 13)
Transconductance, O/P/diff.l/P
Output voltage,
Output current
16
15,16
13,14
13,14
13,15,16
13
linear range
2
0.05
2.5
100
mV
MA
Vin =
ov
0V
kJ2
+ 4
mV
mA
1.0
10
1.0
2.0
5.0
100
10
250
_
mA/V
5.5
13
ut
See note 4
1
14 = 250/iA
See note 5
mA
"'
=0
NOTES
1.
With a timing current of

"' GOfiA
'- and- f = 1kHz
(C - 001
'-'" t
Z .",.'
frequency of* the
SL652C is typically 2.5ppm/C over the
68 f r timin9 CUrrent$
il^p^lrT+o'eV
The
'low' state
Limiting will
'
(JiF, R = 100k 12, supply voltages = 6V), the

temperature coefficient of
range 0C to +40C
the ran9e 20iUA t0 2mA 8nd With the relevant input selected
ln the unselected state the voltage
-
maintained when the inputs are open-circuited.

occur earlier if the output (pin. 13) voltage-limits first
is
For a control current input to pin. 14 of 250/W.

The
output (or phase comparator input) is 'high'.
VFO
sign of the transconductance
-M~5^nU-l^^
113
QSK
1
CURRENT SWITCHES
II
Fig.
120
TIMING CURRENT
2 SL652C block diagram
ou
is
positive
when the
signal input
is
positive
and the
SL652C
Fig.
Circuit diagram
ofSL6S2
OPERATING NOTES
VFO
Basic
The
Relationships
oscillator
output
hundred
millivolts apart.
when
required
normally taken from the phase
is
by biasing the
comparator output
the
If
inputs a
signal
few
a direct oscillator output
comparator
phase
If
the timing resistor
supply (pin
used
of the
VFO
proportional
frequency
free-running
the
to
of
value
3,
the
inversely
is
tuning
capacitor C,
and directly proportional to the
timing current (see Fig.4l). Four current switches,
Pin
if,
pins 4,
5,
6 and
7)
When both
which determine the
VFO
is
normally connected to the chip negative supply;

1 is connected to a separate negative supply
can be voltage-controlled, and the
then the
VFO
frequency
will be:
resistor.
In this simplified configuration, as

is
shown
in Fig.
determined by the relationship.
5 the
V- is the chip and timing resistor negative

and Vc is the control voltage connected to pin 1
where
where
f is in
kHz,
CRV
in volts,
supply
The timing current should be between 20/LtA and 2mA,

corresponding to a value for R between 3kS2 and 300k2
with supplies of 6V. For accurate timing, CR should be
greater than
When
VFO
f
VFO
CRV C
timing
logic inputs are low, open-circuit, or
connected to OV however, then only the current switch

associated with pin 5 is closed. The VFO timing current is
then determined solely by the value of one resistor (R2 in
that
Fig. 4), and by the negative voltage connected to
VFO frequency
CR
however, pin
controlled by TTL-compatible logic inputs on pins 8 and 9

to
select a combination of external resistors (connected
current.
negative
andf
SL652C
connected to pins 2 and
VFO
VFO
it
in place
The
returned to the
Vr =V,
should be taken from pin 2 or 3 (which may

affect oscillator stability). Alternatively, an SL651Ccan be
employed,
is
is
otherwise
is
then
5fxs.
the binary interface
input states, as
shown
in
used as shown
is
free-running frequency
Table
is
in Fig. 4),
dependent on the
the
logic
in jliF
and R
in kfi.
121
SL652C
Pin
Pin 9
LO
Timing
VFO
Pins
Frequency
CR 2
LO
HI
4&5
HI
LO
HI
JL
LO
CURRENT SWITCHES
CR 3
6&7
HI
CR 3
CR 4
Fig.
Table
4 VFO and binary interface
Binary interface relationships
Phase Comparator
The phase comparator parameters
are defihed as follows
VFO GAIN (INPUT= Vr)
(see Fig. 6):
Overall transconductance
V 16
r^
-V ls
V 19
Overall voltage gain
The input
amplifier will limit
- V 1S (exceeds 5mV
kept
(typ.). It
below 5kS2 to
avoid
V 16
-V i5
'-OR CONTROL VOLTAGE Vc
when the peak input (Vj 6

recommended that R|_ is
is
saturating
the
output and
introducing de-saturation delays.
\foy T
CAN SWING
10 WITHIN
0.5V
OF SUPPLIES
Fig
122
6.
Phase comparator
Fig.
5 VFO basic configuration
SL1021A/SL1021B
Semiconductors
SL1021 A & B
CHANNEL AMPLIFIER
The SL1021
and B are bipolar monolithic integrated
circuit amplifiers designed for use as
channel amplifiers
in
telephone transmission equipment and satisfy the requirements of the British Post Office channel translating
1,~K
apparatus (RC5467).
two
The
variants
output
guaranteed
and
levels
of
distinguished
are
+13dBm,
+10dBm and
feature of these devices
temperature-stable
DC
is
AC FEEDBACK
by
respectively, other parameters being identical.
The main
OUTPUT
SUPPLY
DC FEEDBACK
NON-INVERTING -
'V^'
the provision of a
operated remote gain control
/
GAIN
facility
CONTROL
^X
COMPENSATION
CONTROL
REFERENCE
having an adjustable range of control.
The
connections
provided
allow
variety
of
CM10/S
uses,
including fixed gain amplification with various feedback

Fig.
configurations.
Pin connections
FEATURES
Up
to
+13dBm O/P
Temperature
into 600ft (Class A)
insensitive
remote
DC
gain
control
Non-interactive adjustment of:
Gain
Gain Range
Output Return Loss

Transformer output can be
600S2
optimized for low inductance using 2-element
1:1
filter
configuration
Bandwidth:
Power
150kHz
(fixed
gain.
Fig. 4)
Small
Signal
gain
Bandwidth:
3MHz
(see
Fig. 4)
Fig.
APPLICATIONS
2 SL1021
test circuit and typical application
Telephone Communications
Supply Voltage
-20V
Channel Group Translation Equipment
Supply Current
9mA
Gain Control Current
0.5mA
Temperature Range
25C
Radio
communications
Small Signal Processing
(via
to
400J2
+125C
123
SL1021A/SL1021B
Tamb 22C 2C
These characteristics are those obtained using the
test circuit of Fig.
2, the gain range and output impedance being
adjusted as indicated.
Value
Characteristics
Units
Gain (reference gain G)

Gain/R s
Min.
Typ.
Max.
24.5
26
27.5
28
Gain range
7.4
Conditions
dB
dB
dB
R s = 600J2 to 3kS2
Adjusted
Gain law
R A = 125J2
R A = 9kS2
3.9
4.1
4.3
-3.5
-3.3
-3.1
Gain/temperature
-0.1
0.1
dB
dB
dB
dB
-36
-45
dBmO
dBmO
-76
dBm
dBm
dBmP
+0.1
Gain/V s
Relative to
Relative to G,
VS
= 10C to 45C
-20V1V
Distortion
2nd harmonic
3rd harmonic
At 10dBm output
Overload
SL1021A
SL1021B
10
13
13
15
Noise
Output impedance
Return
Class
operation
Proportional to
600
20
dB
Input impedance
Gain at reduced Vs
10
kJ2
Variable with
25.5
dB
dBm
Vs
Vs
Overload at reduced
Vs
Adjusted
loss
250Hz to 3.4kHz
Ra and Rg
= -17.5V See Fig.2
= -17.5V
Gain control interaction between

channels (change in gain for
3.3
0.25
dB
mA current change)
Frequency response
240
3400
,00
Bandwidth
Hz
kHz
Equivalent to
Common R A
CONTROL
REFERENCE
INPUT
DC FEEDBACK
NON-INVERTI*
Fig.
124
channels.
0.05dB ref. 800Hz

C c = 50pF
AC FEEDBACK COMPENSATION
CONTROL
1 1
earth return
3SLW21 equivalent circuit
SL1021A/SL1021B
OPERATING CONDITIONS (see Fig. 2)

Value
Parameter
Min.
Typ.
Max.
11.0
Supply current
mA
mA
7.0
Supply voltage on chip

Supply
-23
V
V
V
0.3
mA
mA
mA
+125
-20
-17
Supply voltage
maximum
0.5
Control current
0.26
Control current change
-25
Operational temp.
Fixed
R A =0
R A = 11k2
Via 400S2
Pin 10
Pin 10
R A =0
R A = 10kft
R A =0to 11kfi
gain application (see Fig. 4)
Optimum
100
load
ft
mW
20
150
20
3
Power output
Power bandwidth
Gain
Frequency response
Fig.
4 Fixed gain
amplifier. Class
or
AB
10mW
Class
kHz
dB
Values as Fig. 4
MHz
Small signal
AB
125
SL1021A/SL1021B
OPERATING NOTES
The control decoupling
capacitors should be of a low
leakage type.
Other values of control
resistors are possible
if
other
gains/gain ranges are required. However, the parallel

resistance to earth
at
If
all
Because of temperature coefficient mismatch between R

c
and internal resistors, the gain stability may be degraded
with temperature.
6.
from pins 5 and 6 should be <8kl2
settings.
the
positive earth system, care should be taken to prevent
control
circuited,
The case is connected to pin 10 ( ve supply). To

avoid damage to the device when operating with a
resistance
is
increased
or
open
the amplifier gain will decrease to zero.
4 for fixed gain use).

The compensation capacitor can be increased to reduce
the frequency response and power bandwidth.
(See Fig.
the case from becoming earthed.
This device is also available with tin-dipped leads,

order as SL1 021 AM.
7.
The
gain may be increased from the value of Fig. 2

(26dB nominal) by increasing R c the gain increase
,
being given by:
R r + 8.5
8.5
where R~
126
is
in kfi.
20%
Supply voltage
(via
40012)
Storage temp, range
Free
air
operating temp, range
-30V
-55C
-40C
to + 1 75C
to +1 30C
SL1021A/SL1021B
127
SL1021A/SL1021B
128
SL1521
^^P' Semiconductors
SL1521A & C
300MHz WIDEBAND AMPLIFIERS
The SL1521A and C are wideband
amplifiers intended for

successive detection logarithmic IF strips operating at
centre frequencies of up to 200MHz. It is a plug in
replacement for the SL521 series of RF amplifiers. The midband voltage gain of the SL1521 is typically 12dB. The
SL1521 A and C differ mainly in the tolerance of voltage gain.
use
in
APPLICATIONS
Radar
CM8
IF Strips
Fig.
Pin connections
Wideband Amplification

-55C
-55C
Storage temperature
Test
circuits:
see
to
to
+150C
+125C
150C
Maximum chip operating temperature

Chip to ambient thermal resistance
250C/W
Fig. 8
Fig.2 Circuit
diagram
25
^
m
<
.'
S"
// k^
8
O
*
o
MHz
20 MHz
60 MHz
J If
f
/
SO
100
FREQUENCY (MHz)
Fig.3 Voltage gain
v.
frequency
200 300
500
O.i
0.2
0.3
0.4
0.5
0.7
0.6
0.6
0.9
INPUT SIGNAL (Vrmsl
Fig.4 Rectified output current
v.
input signal
129
1.0
SL1521
Temperature
= + 22C 2C
Supply voltage
=+ 5.2V
DC connection between input and bias pins.
Value
Characteristic
Circuit
Units
Min.
Voltage gain,
Voltage gain,
f=
120
MHz
SL1521
SL1521
SL1521
SL1521
SL1521
SL1521
SL1521
SL1521
SL1521
f= 160MHz
Lower
cut-off frequency
Propagation delay
Maximum rectified video output
All
All
A
B
A
B
A
B
C
12.8
13.0
13.4
dB
dB
dB
dB
dB
dB
10
MHz
MHz
MHz
MHz
12.5
12.8
13.1
350
350
350
6
types
types
SL1521 A
SL1521 B
SL1521 C
current
11.5
11.2
10.8
11.2
11.0
10.6
315
315
300
Conditions
Max.
Typ.
0.6
3mVrms input
50 ohms source
8pF load + 500 Q
50 ohms source
50 ohms source
ns
0.95
0.90
0.90
1.05
1.10
1.20
mA
mA
mA
f=120 MHz
0.5Vrms input
8pF
load,
500 ohms
parallel

Variation of maximum rectified
types
types
1.0
All

Maximum input signal before overload
Noise figure
All
types
1.5
Supply current
All
types
Maximum RF
All
types
All
output voltage
dB/V
%/V
30
10.0
4.5
V rms
dB
15.0
20.0
mA
See note below

120 MHz, source
f=
resistance optimised
f=120MHz
Vp-p
1.0,
........
MHz
'"^.l
^^
OMHx-
INP UT 05 V
RMS
i-.
-10
-20
20
10
TEMPERATURE
Fig.
130
5 Maximum
rectified
output current
v.
temperature
Fig.
60
20MHi
ISO*
tOO
("CI
v.
temperature
120
in
"
SL1521
Operating Notes
The
as
amplifiers are intended for use directly coupled,
shown
in Fig. 8.
in an untuned cascade will be
output on noise.
be reduced by inserting a single tuned
The seventh stage

giving virtually
Noise
may
full
As there is a large mismatch between stages a simple shunt or series circuit cannot be
used. The choice of network is also controlled by the
need to avoid distorting the logarithmic law; the network must give unity voltage transfer at resonance. A
suitable network is shown in Fig. 9. The value of C1
must be chosen so that at resonance its admittance
equals the total loss conductance across the tuned
circuit in the chain.
I=-55*C
T=
+12S*C
'
FREQUENCY IMHIl
circuit.

the output line if many stages and fast rise times are
Fig.
Input admittance with ooen-circuit output
required.
Values of positive supply line decoupling capacitor

for untuned cascades are given below.
Smaller values can be used in high frequency tuned
cascades.
The amplifiers have been provided with two earth
required
leads to avoid the introduction of common earth lead

inductance between input and output circuits. The
equipment designer should take care to avoid the
subsequent introduction of such inductance.
Number
6 or more
Minimum capacitance
30nF
of stages
10nF 3nF
3
1nF
Fig.
Direct coupled amplifier*
Ix
Fig.
9 Suimble
interstage
tuned circuit
131
SL1521
132
SL1523C
ffl
LEwwEY
Mr
Semiconductoi
^^P' Semiconductors
SL1523C
DUAL WIDEBAND LOGARITHMIC AMPLIFIER
The SL1523C consists of two SL1521's in series,
and is intended to reduce the package count and
density
improve the
packing
at frequencies
up to 200 MHz.
Absolute
(
Maximum
logarithmic
in
strips
Ratings
Non-Simultaneous)
The absolute maximum
ratings are limiting values
VIDEO OUTPUT
RF OUTPUT
above which operating life may be shortened or

satisfactory performance may be impaired.
Chip-to-ambient thermal
55C to
55C to
1
+175C
+125C
CM6
Pin connections (bottom view)
Fig. 1
50C
300C/W
resistance
Chip-to-case thermal
95
resistance
C/W
Maximum
video output
Supply voltage
+12V
+ 9V
VIDEO OUTPUT
Fig.
Fig.
SL1523 circuit diagram (each amp)
SL1523 block diagram
0MHz
S~
//,
"-
20
MHz
60MHz
r
r
1
/
FREQUENCE IMHil
Fig.
Voltage gain
v.
frequency
fig.
v.
Input aignal
133
SL1523C
Temperature = 22C 2C
Supply voltage = + 5.2V
SL1523
Characteristic
Voltage gain
Voltage gain
(Min)
21
27
dB
dB
(Min)
20
27
dB
dB
Upper cut-off
(Min)
frequency
(Typ)
cut-off
frequency
Propagation delay
Maximum
rectified
(Typ)
300
325
8
(max)
10
MHz
MHz
MHz
MHz
(Typ)
1.2
ns
(Min)
(Max)
1.6
2.0
mA
mA
(Typ)
2.0
dB/V
Variation of gain with

supply voltage
= 120MHz,3mVrms
50 ohms source
4 pF load + 500 ohms
input,
= 160MHz,3mVrms
input, 50 ohms source

4 pF load + 500 ohms
50 ohms source
50 ohms source
50 ohms source
50 ohms source
= 120 MHz,
input,
4 pF
0.5
Vrms
load.
maximum
rectified output current

with supply voltage
(Typ)
30
%/V
before overload
(Typ)
1.5
Noise figure
(Typ)
V rms
dB
Maximum
Test Conditions
video
output current
Variation of
Units
(Max)
(Max)
Lower
input signal
See
f
note below
=120 MHz,
source
resistance optimized
Supply current
20
30
40
(Min)
(Typ)
(Max)
Maximum
mA
mA
mA
R.F. output
voltage
(Min)
Note: Overload occurs
when
1.0
Vp-P
= 120MHz
the input signal reaches a level sufficient to forward bias the base-collector junction of
--.
TR1 on peaks.
OMHz
^^,'
INRUT05V
RMS
1
-0
134
20MHI
ISO*
_ __
-M>
-20
20
ui
TEMPERATURE
Fig.
Maximum rectified output current v.
temperature
Fig.
ao
so
no
no
<C|
v.
temperature
"
SL1523C
?"
IH
TO(n+Dh STAGE
BIAS AND INPUT
PINS LINKED)
I
X
T =
-5 5C "
5C
T = +t
Fig.
...
20
(0
60
100
120
U0
KO
WO
200
FREQUENCY (MHz]
Fig.
Input admittance with
open circuit output
135
SL1523C
136
SL1613C
APLESSEY
HP' Semiconductors
SL1613C
WIDEBAND LOG
IF
STRIP AMPLIFIER
circuit
is a bipolar monolithic integrated
amplifier intended primarily for use in succesfrecentre
at
operating
sive detection logarithmic IF strips,
10MHz and 60MHz. The devices pro-
The SL1613C
wideband
O/P EARTH [
are suitable for

vide amplification, limiting and rectification,
line decoupling.
direct coupling and incorporate supply
is typically
SL1613C
The mid-band voltage gain of the
O/P EARTH
8 ]
v[
] BIAS
RF OUTPUT [
] INPUT
quencies between
DET OUTPUT
Rl
(
l/P
EARTH
12dB.
DP8
Fig.
FEATURES
Well Defined Gain
4.5dB Noise Figure

High l/P Impedance
-55Cto+l25C
-30Cto+85C

instantaneous voltage
+12V
video output
9V
Supply voltage
Maximum
Low O/P Impedance

1 50MHz Bandwidth
at

APPLICATIONS
Logarithmic
Gains up to 108dB and
IF Strips with
Linearity Better than
2dB
_
18-0
_
ISO
1 /
U'O
l/jn
ttAr-
2 12-0
rJ iti
j.
ft"
ilSp
3 3k
2'
100
80
I-\V
> \\
\\\
\\
T=t1l0 L
"">
\\
_
_
_
"X
_
20
_
6C
10
Fig.
Circuit
100
FREQUENCY (MHz)
diagram
Fig.
Vortsge gain
v.
frequency
137
K
SL1613C
Ta = +22C 2C
Supply voltage = +6V
DC connection between
input
and bias pins

Value
Characteristic
Units
Min.
Voltage gain
10
Upper cut-off frequency (Fig.

Lower cut-off frequency (Fig.
12
dB
14
3)
150
3)
MHz
MHz
ns
Propagation delay
Max. rectified video output current (Figs. 4 and 5)
0.8
f=30MHz, R s =10Q.C L =8pF
Rs=10O,CL =8pF
R s =10O,C L =8pF
mA
1.3
0.7
dB/V
25
1.9
4.5
Maximum RF output voltage
%V
Vrms
dB
1.2
Vp-p
Supply current
15
Variation of
maximum
current with supply voltage

Note
=60MHz, Vin =500mV rms
output
rectified
Maximum
Noise figure
Conditions
Max
Typ.
(Fig. 6)
Overload occurs when the input signal reaches a
^~
-I
-I J*
level sufficient to
See Note 1
=60MHz, R =450Q
mA
20
forward bias the base collector junction of TR1 on peak
ii
10HN,
-X~"- jj "^
~iv
~\YlVl ts^- ~i.~MT
MMH.
A
xH
hi
I
i^j
ZjlJ
-J
w
r~T~"
30
MHz
60
MHz
DMHz
INPUT. 05V
INPUT
Fig.
'III
"T
"]
V-A
RM
SIGNAL (Vrmil
v.
input signal
-so
AMBIENT TEMPERATURE
Fig.
CONDUCTANCE =
-Jl9
JO
iO
TEMPERATURE
Fig.
138
-5S"C
-25 # C
temperature
Immko
..
CO
v.
60 MH 2
l<l
-4 9
("CI
Maximum rectified output current v.
temperature
FREQUENCY (MHz)
Fig.
Input admittance with
open circuit output
SL1613C
TO In. 1|l" STAGE
Fig.
Fig.
Su/iatofe interstage
tuned circuit
OPERATING NOTES
The amplifiers are intended for use directly coupled, as
shown in Fig. 8.
virtually full output on noise.
Noise may be reduced by inserting a single tuned circuit
stages a
in the chain. As there is a large mismatch between
distorting
avoid
to
need
the
controlled
by
also
is
network
transfer at resonance. A suitable network is shown in Fig. 9.
The value of C1 must be chosen so that at resonance its
admittance equals the total loss conductance across the
tuned circuit. Resistor R1 may be introduced to improve
the output line if many stages and fast rise times are re-
The amplifiers have been provided with two earth leads

to avoid the introduction of common earth lead inductance
between input and output circuits. The equipment designer
such inductance.
Number of stages
6 or more
30nf
10nF
3nF
1nF
Minimum capacitance
The 500pF supply decoupling capacitor has a resistance

10Q. It is a junction type having a low breakdown voltage and consequently the positive supply current
of, typically,
quired.
Values of positive supply line decoupling capacitor required for untuned cascades are given below. Smaller
will
increase rapidly
if
the supply voltage exceeds 7.5V
(See Absolute Maximum
Ratings).
Centre frequency
Dynamic Range
Video rise time
Bandwidth
Output voltage
Typical log accuracy
Fig.
60MHz
-75dBmto+15dBm
70nSec
20MHz
0-1.5V
2dB
approx.
10 Circuit diagram of low cost strip
139
SL1613C
140
SL1621C
SL1621C
AGC GENERATOR
is an AGC generator designedspecifically
use in SSB receivers in conjunction with the SL1610C,
with
SL1611C and SL161 2CRF and IF amplifiers.ln common
other advanced systems it generates a suitable AGC voltage
hold'
provides
a
waveform,
directly from the detected audio
speech,
period to maintain the AGC level during pauses in
The SL1621C
for
will
and is immune to noise interference. In addition it

HF
smoothly follow the fading signals characteristic of
communication.
When used in a receiver comprising one SL16lOCana
one SL1612C amplifier and a suitabledetector.the SL1621C
maintain the output within a 4dB range for a 110dB

range of receiver input signal.
will
FEATURES
All
Time Constants Set
Externally
Easy Interfacing
Compatible with SL161 0/161 1/1612
APPLICATIONS
SSB
Receivers
Test Equipment

Supply voltage: 6V
Supply current.
Fig.
3mA
2 Block diagram
Tost conditions (unless otherwise stated):

Supply voltage V<x = 6V
Test frequency. 1kHz
-55Cto+125C
Value
Min.
Maximum
output voltage
on output
ripple
Input resistance
Output resistance
Fast' rise time ti
Fast'
6
7
DC output
DC output
AC
decay time
t2
Slow' rise time t3

Hold collapse time t4
Hold time ts
Typ.
3.1
Supply current
Cut-off frequency ( 3dB)
Input for 2.2V
Input for 4.6V
Conditions
Units
Characteristic
11
4.5
12
500
70
20
200
200
100
1.0
Max.
5
mA
No signal
kHz
mVrms
mVrms
V
mV pk-pk
kHz, output open circuit
Q
D
ms
ms
ms
ms
to 50% full output

Time
to output transistion point
90% to 10%
full
output
141
SL1621C
APPLICATION NOTES
The SL1621C consistsof an input AF amplifier coupled to
a DC output amplifier by means of two detectors having
short and long rise and fall times respectively. The time
constants of these detectors are set externally by capacitors
on pins 5 (Ci ) and 3 (C2).
The detected audio signal at the input will rapidly establish
an AGC level via the 'fast' detector time in ti (see Fig. 3).
Meanwhile the long time constant detector output will rise
and after t3 will control the output because this detector is
more sensitive.
Input signals greater than approximately 4mV rms will
actuate a trigger circuit whose output pulses provide a
discharge current for C2.
By this means the voltage on C2 can decay at a maximum
rate, which corresponds to a rise in receiver gain of 20dB/s.
Therefore the AGC system will smoothly follow signals
which are fading at this rate or slower. However should the
receiver input signals fade faster than this, or disappear
completely as during pauses in speech, then the input to
the AGC generator will drop below the 4mV rms threshold
and the trigger will cease to operate. As C2 then has no
discharge path, it will hold its charge (and hence the output
AGC level ) at the last attained value. The output of the short
time constant detector will drop to zero in time t2 after the
disappearance of the signal.
The trigger pulses also charge C3. When the trigger

pulses cease, C3 discharges and after ts C2 is discharged
rapidly (in time U) and so full receiver gain is restored. The
hold time, ts is approximately one second with C3 = 1 OOuF.
If signals reappear during
ts, then C3 will recharge and
normal operation will continue. The C3 recharge time is
made long enough to prevent prolongation of the hold time
by noise pulses.
Fig. 3 shows how a noise burst superimposed on speech
will initiate rapid AGC action via the short time constant
detector while the long time constant detector effectively
remembers the pre-noise AGC level.
The various time constants quoted are for C-| = 50(iF and
C2 = C3 = 1 0OuF. These time constants may be altered by
varying the appropriate capacitors. C1 controls ti t2; C2
,
controls t3, t4;
C3 controls
ts.
The supply must either have a source resistance of less

than 2Q at LF or be decoupled by at least 500>F so that it is
not affected by the current surge resulting from a sudden
input on pin 1
In a receiver for both AM and SSB using an
SL1623C
detector/carrier
AGC
generator, the
is
controlling the system.
capacitance on the output should not exceed

the impulse suppression will suffer.
AUDIO
OUTPUT
ENVELOPE
L
_ SHORT TIME CONSTANT
DETECTOR OUTPUT (Cll
_ LONG TIME CONSTANT

DETECTOR OUTPUT IC2)
3 Dynamic response of a system controlled by SL1621C
Fig.
142
outputs of the
AGC lines may require some RF decoupling but the total
NOISE BURST
Fig.
AGC
SL1621CandSL1623Cmay be connected together provided

that no audio reaches the SL1621C input while the
SL1623C
4 SL1621C used to control SSB receiver
AGC generator
5000pF or
SL1621C
._.
NORMAL AGC
Bi
51161
.SLW 12
...
INPUT (mVcms)
Fig.
5 Transfer characteristic of SL1 621 C {typical)
Under some conditions, overload

occur
and
in
of the
AGC output may
a receiver. Possible solutions are shown
in Figs.6
7.
Fig.6
Fig.7
143
SL1621C
144
SL2363/SL2364
ffl
A r LCwwC
Semiconductoi
*^P Semiconductors
SL2363C & SL2364C

VERY HIGH PERFORMANCE TRANSISTOR ARRAYS
of transistors
The SL2363C and SL2364C are arrays

internally connected to form
a dual long-tailed pair with tail
They are monolithic integrated circuits manuhas a

factured on a very high speed bipolar process which
minimum useable fr of 2.5 GHz, (typically 5GHz).
The SL2363 is in a 10 lead TO5 encapsulation.
The SL2364 is in a 14 lead DIL plastic encapsulation.
transistors.
FEATURES
Complete Dual Long-Tailed
Pair in
One Package.
CM10
SL2363C
Very High f t - Typically 5 GHz

Very Good Matching Including Thermal Matching
APPLICATIONS
Wide Band Amplification Stages
1 40 and 560 MBit PCM Systems
Fibre Optic Systems
High Performance Instrumentation
Radio and
Satellite
Communications
SL2364C
Fig. 1
DP14
Tamb = 22C 2C
Value
Characteristics
Min.
Typ.
10
6
20
9
bvebo
2.5
5.0
BVciO
hFE
16
20
40
80
BVCBO
LVCEO
AVbe (See note

avbe/tamb
CcB
1)
AVBE applies
GHz
mV
mV/C
-1.7
0.5
1.0
CCI
NOTE
V
V
V
V
5
2
2.5
fT
to)
VBEQ3 - VBEQ4J and VBEQ5 - VBEQ6

|
Conditions
Units
Max.
0.8
1.5
PF
PF
Iq= 10uA
=
=
IC=
IC =
IC
IE
5mA
10uA
10uA
8mA, VcE = 2V
= 8mA, VCE=2V
(Tail)
IC
IC (Tail) = 8 mA, Vqe = 2V
IC (Tail) = 8 mA, VcE = 2V
VCB =
VCI
=0
145
SL2363/SL2364
T NORMALISED AT .JOC
IV
CE
IC - 4-5mA
IC(mA)
Fig.
2 Collector current
TEMPERATURE

Maximum
individual transistor dissipation
Storage temperature
55C to
Maximum junction temperature
Package thermal resistance (C/W):
Chip to case
65 (CM 10)
Chip to ambient 225(CM10) 175(DP14)
VCBO =
10V.
VEBO =
2.5V.
VQEO =
6V.
Fig.
200mW
+ 1 50C
+ 1 50C
VciO =
15V,
The substrate should be connected to the most negative

point of the circuit to maintain electrical isolation between
the transistors.
146
IC (any one transistor)
(C)
3 Chip temperature
= 20mA
SL3045/SL3046
SL3045C SL3046C
GENERAL PURPOSE NPN TRANSISTOR ARRAY
The SL3045C and SL3046C are monolithic arrays of five
general purpose transistors arranged as a differential pair
and three isolated transistors. The arrays are available in
ceramic (SL3045C) or plastic (SL3046C) 14 lead DIL
14
12
13
11
10
r-i
r-i
qi
packages.
r-tf
FEATURES
5 General Purpose Monolithic Transistors
Good Thermal
DG14
DP14
Tracking
Wide Operating Current Range

Suitable for Operation from
Fig. 1
Pin connections
DC to VHF
Low Noise Performance 35dB
at
kHz.
vce
3v
VK^/
tE"3V
-/
4V BE
Fig.
C (mA)
IC<m*)
2 Typical small signal currant gain {common emitter vs.

Fig.
collector current)
4 Typical base emitter voltage and base emitter volt

matching
vs.
collector current
VCC-3V
*CE
3V
100
125
lc(mA)
Fig.
3 Base current matching
vs.
collector current
FiQ.
5 Typical baaa emitter volt matching vs. chip temperature
147
SL3045/SL3046
Tamb =22C2C
Value
Symbol
Characteristic
Min.
Typ.
Max.
0.1
Units
Conditions
Static characteristics
Iebo
breakdown
Collector-base breakdown
Collector-subtrate breakdown
Collector emitter
LVceo
15
20
BVcbo
20
50
BVcio
20
70
Collector cut off current
Base emitter voltage

Collector-emitter saturation
V
V
V
ICEO
0.5
ICBO
40
Vbe(ON)
0.71
Vce(SAT)
0.23
UK
M
nA
V
V
= 6V
= 1mA
Ic = 10/yA
Ic = 1C|uA
Vce = 10V, Ib =
Vcb = 10V, Ib =
Vce = 3V, Ic = 1mA
Ib = 1mA, Ic = 10mA
Veb
Ic
Static forward current-transistor
Hfe
ratio
40
120
Vce
100
Vce =3V,
50
Vce
3V, Ic
Ic
3V, Ic
Input offset current differential pair
ho
0.2
/iA
Vce =3V,
Ic
Input offset voltage differential pair
AVbei
0.35
mV
Vce =3V,
Ic
AVBE2
0.45
=
=
=
=
=
10mA
1mA
1QuA
1mA
1mA
Input offset voltage isolated

transistors
Temperature coefficient of input

Temperature
dT
coefficient of base
mV
Vce =3V,
Ic
= 1mA
/uVC
Vce =3V,
Ic
= 1mA
-1.8
mWC
Vce =3V,
Ic
= 1mA
3.25
dB
dAVBE
offset voltage
dVBE(ON)
emitter voltage
dT
Dynamic characteristics
Wideband noise figure
NF
Vce
10Hz
to
3V, Ic
10kHz
= IOQuA
Source resistance
Forward transfer admittance
Input admittance
Yfe
Yie
0.3-J0.04
Output admittance
Reverse transfer admittance
Yoe
Yre
0.001 +J0.03
O.OOO-jO.003
ratio
hfe
110
impedance
hie
3.5
kO.
hoe
15.6
A<mho
Short
circuit input
Open
Open
circuit
output admittance
31-J1.5
mmho
mmho
mmho
mmho
circuit reverse voltage
= 1 MHz
Vce =3V,
hre
500
MHz
Vce
Ceb
1.2
Veb
Cob
0.65
Collector substrate capacitance
Cci
2.55
pF
pF
pF
1.
300
fT
Typical values are for design guidance only

above
which operating life may be shortened or specified performance may be impaired.

All electrical ratings apply to individual transistors; thermal
ratings apply to total package dissipation.
The isolation pin must always be negative with respect to

the collectors.
Storage temperature
Junction operating temperature
20V
15V
148
6V
20V
40C/W(DG14)
125C/W(DG14)
175C/W(DP14)
-55Cto +175C(DG14)
-55Cto +125C (DP14)
+175C(DG14)
= 15mA
= 15mA
= 1mA
Ic
= 1mA
1.8x10-"
Gain bandwidth product

NOTE
Ic
= 1kHz
Vce =3V,
transfer ratio
+ 125C(DP14)
= 10mA
Vcb
Vcs
= 3V,
= 3V,
= 3V,
= 3V,
Ic
Ie
Ic
Ic
= 3mA
=
=
=
kfi
SL3127
Semiconductors
SL3127C
HIGH FREQUENCY NPN TRANSISTOR ARRAY
The SL3127C
is
NPN
a monolithic array of five high frequency

a 16 lead DIL package. The
transistors in
transistors exhibit typical frs of
low current
figures of 3.6dB.
1.6GHz and wideband noise
The SL3127C
is
pin compatible with the
CA3127.
FEATURES
fT Typically
GHz
.6
Figure 3.6dB
Wideband Noise
V BE Matching
Better
Than
DP16
5mV
Fig.1 Pin
connections SL3127
APPLICATIONS
Wide Band Amplifiers
PCM
Regenerators
High Speed Interface Circuits

High Performance Instrumentation Amplifiers
High Speed
Modems
10
X
9.
in
^ ^_
0-'
COLLECTOR CURRENT (mA)

Fig.
3 Transition frequency
(rT ) v.
collector current (VCB =2V,
t=200MHz)
149
SL3127
Test cotfHIom (unless otrierwte* stated):
T* =22C2C
Characteristic
Value
Symbol
MHn.
Typ.
BVcbo
LVceo
20
30
15
18
55
20
Max.
Units
Conditions
SMic characteristics
Collector base
breakdown
breakdown
Collector substrate breakdown
Base to isolation breakdown
Collector emitter
(isolation)
Collector emitter saturation voltage


Base emitter voltage difference,
BVcra
20
BVbio
10
Vbe
0.64
0.74
0.84
Vce(SAT)
0.26
0.5
Iebo
0.1
Vbe(SAT)
0.95
AVbe
0.45
AIb
0.2
dAVBE
2.0
V
V
V
V
V
V
mV
transistors
all
Temperature coefficient of AVbe
= 10/iA, Ie =
= 1mA, Ib =
Ic = 10//A, Ir = Ie =
Ib = 10//A, Ic = Ie =
Vce = 6V, Ic = 1mA
Ic = 10mA, Ib = 1mA
Veb = 4V
Ic = 10mA, Ib = 1mA
Vce = 6V, Ic = 1mA
Ic
Ic
Vce
vv/c Vce
=
=
6V, Ic
6V, Ic
= 1mA
= 1mA
dT
Temperature coefficient of Vbe
dVBE
-1.6
mV/C Vce =6V,
Ic
95
Vce
Vce
= 6V,
= 6V,
Ic
= 1mA
dT
Static forward current ratio
Hfe
Icbo
35
35
100
40
100
0.3
CIO
0.6
BIO
100
Ceb
CCB
0.4

Cci
0.8
Base
isolation leakage
Dynamic
0.4
nA
nA
nA
PF
PF
PF
Ic
Vce =6V, Ic
Vcb = 16V
= 20V
= 5V
Veb = 0V
Vcb = 0V
Vci
Vbi
Va =0V
characteristics
Wideband noise figure

Knee of 1/f noise curve
fT
1.6
NF
3.6
1
GHz Vce = 6V, Ic = 5mA

dB f = 60MHz \ Vce = 6V
kHz
[
)

above
which operating life maybe shortened or specified parameters may be degraded.

All electrical ratings apply to individual
transistors.
most negative voltage applied to the package to maintain
electrical isolation.
VC8 = 20volt
VE8 = 4.0 volt
VCE = 15volt
VCI =20 volt
Ic
= 20 mA
Maximum
200 mWatt
Storage temperature -55C to 150C

Max junction temperature 150C
Package thermal resistance (C/watt):Package Type

Chip to case
Chip to ambient
DG16
DP16
40
120
180
NOTE:
the power is being dissipated in one transistor,
these
resistance figures should be increased bv
'
100C/watt.
If all
thermal
150
= 5mA
= 0.1mA
= 1mA
Ic
Rs
= 2mA
=2000
SL3127
10
COLLECTOR BASE VOLTAGE
Fig.
(IC
[tT )
v.
(V)
collector base voltage
= 5mA,Frequency = 200MHz)
.,
3-2
I
2-4
20
VCB" 5V
ic
-s
16
VCB
2V
5mA
1-2
OS
0-4
80
60
40
20
TEMPERATURE
Fig.
5 Variation of
transition
16
(*C)
frequency
(fT )
*"ri temperature
151
SL3127
TO
SO
10
100 nA
IOuA
100pA
COLLECTOR CURRENT
Fig.
DC current gain
v.
collector current
DO
10 OMHz
Fig.
152
7 Zfj (derived from scattering parameters)
v.
frequency
{Zn
-"-&$')
SL3145
Semiconductors
^^P' Senriconductoi
SL3145C,E
1.2GHz HIGH
The SL3145C
low current
a monolithic array of
is
NPN
FREQUENCY NPN TRANSISTOR ARRAYS
transistors.
five
high frequency
consists of 3
The SL3145C
isolated transistors and a differential pair in a 14 lead

package. The transistors exhibit typical frs of 1.6GHz
wideband noise figures of 3.0dB. The device is
DIL
and
pin
compatible with the SL3045C. The SL3145E has guaranteed
Ccb and
fr figures.
FEATURES
fj Typically
.6
DG14
DP14
GHz
Wideband Noise Figure 3.0dB

V BE Matching Better Than 5mV
Fig.1 Pin
APPLICATIONS
Wide Band
PCM
connections SL3145
Ordering Information
Amplifiers
SL3145C-DG
SL3145C-DP
SL3145E-DP
Regenerators
High Speed Interface Circuits
Ceramic
Plastic
Plastic
High Performance Instrumentation Amplifiers

High Speed
Modems
10
_.
_
I
P.
1-0
10
to
COLLECTOR CURRENT <mA)

Fig.2 Transition frequency (U)
v.
collector current (Vcb
2V,
200MHz)
153
SL3145
Tamb =22C 2C
Value
Symbol
Characteristic
Min.
Typ.
Unite
Max.
Conditions
Static characteristics
Collector base breakdown
BVcbo
20
30
breakdown
Collector substrate breakdown
LVceo
BVcio
15
18
20
55
Collector emitter
V
V
V
Ic
=
=
=
Ic
Ic
10M,Ie
1mA,lB
1QuA,Ir
=
=
=
Ie
(isolation)
Base to isolation breakdown

Collector emitter saturation voltage
BVbio
10
20
Vbe
0.64
0.74
0.84
Vce(SAT)
0.26
0.5
V
V
V
Iebo
0.1
//A
Vbe(SAT)
0.95
AVbe
0.45
mV
= Ie =
= 1mA
Ic = 10mA,lB = 1mA
Veb = 4V
Ic = 10mA,lB = 1mA
Vce =6V,lc = 1mA
AVbe
0.35
mV
Vce
6V,lc
= 1mA
AIb
0.2
A/A
Vce
6V,lc
= 1mA
Vce
6V,lc
= 1mA
mV/C Vce =
6V,lc
= 1mA

Base emitter voltage difference,
transistors except TR1.TR2
Base emitter voltage difference
Ib
10//A,lc
Vce =6V,lc
all
TR1,
TR2
(except for TR1, TR2)

Input offset current TR1,
TR2
AVbe
Temperature coefficient of
Temperature coefficient of Vbe
AIb
0.2
dAVBE
2.0
dVBE
-1.6
Static forward current ratio
Hfe
ICBO
40
100
100
Vbi
0.4
PF
Veb
PF
PF
PF
Vcb
CIO
0.6
Base
BIO
Ceb
Vce
nA
nA
nA
0.3

isolation leakage
AfV/C
Vcb
Vci
= 6V,lc = 1mA
= 16V
= 20V
=5V
= 0V
SL3145C
SL3145E
CCB
Cci
Dynamic
0.4
0.4
1.1
0.8
Vcb.
Vci
= 0V
= 0V
=0V
characteristics
SL3145C
SL3145E
Wideband noise frequency
Knee
fT
GHz
GHz
1.6
1.2
NF
of 1/f noise curve
3.0
dB
kHz
= 5mA
= 10mA
Vce
2V,Rs = 1kO
Ic = 100/iA,f = 60MHz
Vce = 6V,Rs = 200fi
Ic = 2mA
Vce
Vce
=
=
=
6V,lc
6V,lc

above
which operating life maybe shortened or specified parameters may be degraded.

All electrical ratings apply to individual transistors.
most negative voltage applied to the package to maintain
electrical isolation.
VCB = 20 volt
VEB = 4.0 volt
VCE = 15volt
Vcl =20 volt
Ic
Storage temperature 55C to 1 50C

Max junction temperature 1 50C
154
DG14
DP14
Chip to case
Chip to ambient
40
125
180
NOTE:
the
power
is being dissipated in one transistor, these

resistance figures should be increased bv
100C/watt.
If
all
thermal
= 20 mA
Maximum
Package thermal resistance (C/watt):-
PackageType
200 mWatt
r
SL3145
ctttttf
COLLECTOR BASE VOLTAGE

Fig.3 Transition frequency (fr)
v.
(V)
collector base voltage (Ic
= 5mA,
frequency
= 200MHz)
32
2-4
*CB" 5V
mA
VC 8-2V
1C*5mA
80
40
20
40
TEMPERATURE
SO
80
100
120
140
100
(*C>
Fig.4 Variation of transition frequency (fr) with temperature
155
SL3145
lOOpA
10mA
COLLECTOR CURRENT
Fig.5
DC
current gain
v.
collector curent
'a 200
i
<
10 OMHz
FREQUENCY
Fig.6
156
Zn
(derived from scattering parameters)
v.
frequency (Znr66')
SL6270C
^^ Semiconducto
Semiconductors
SL6270C
GAIN CONTROLLED PREAMPLIFIER
The SL6270C is a silicon integrated circuit combining
the functions of audio amplifier and voice operated
gain adjusting device (VOGAD).
sensitivity
It is designed to accept signals from a low
microphone and to provide an essentially constant
60dB range
output signal for a
of input.
MAIN AMP INPUT
The dynamic
range, attack and decay times are controlled by external
components.
CM8/S
FEATURES
Constant Output Signal
Fast Attack
Fig.
Pin connections.
SL6270C -
CM
(bottom view)

Simple Circuitry
AGC TIME CONST [
PREAMP OUTPUT [
Vcc[ 3
APPLICATIONS
PREAMP INPUT
' ]
MAIN AMP INPUT
6 ]0V
] PREAMP INPUT
AGC
Systems
Transmitter Overmodulation Protection
Tape Recorders
Audio
8 ] MAIN AMP OUTPUT
DP8
Fig.
2 Pin connections. SL6270C -
DP
(top view)

Supply Voltage 4.5V to
Voltage Gain 52dB
:
0V

Supply voltage
2V
Storage temperature
-55Cto +|125C
Fig.
3 SL6270C block diagram
157
SL6270C
Supply voltage Vcc 6V
Input signal frequency: 1 kHz
Ambient temperature 30C to +85C
Test circuit shown in Fig. 4
Value
Characteristic
Min.
Supply current
Input impedance
Typ.
5
Max.
Units
10
mA
150
Conditions
Pin
or 5
Differential input
impedance
Output
300
Voltage gain
40
55
level
THD
52
90
2
IOji
dB
140
5
If
input not
Fig.
AC coupled the resistance
4 SL6270C
test
less than
and application
10 ohms.
circuit
APPLICATION NOTES
Voltage gain
The input to the SL6270C may be single ended or
but must be capacitor coupled. In the
single-ended mode the signal can be applied to either
input, the remaining input being decoupled to ground.
Input signals of less than a few hundred microvolts
rms are amplified normally but as the input level is
increased the AGC begins to take effect and the output
is held almost constant at 90mV rms over an input
range of 50dB.
The dynamic range and sensitivity can be reduced by
reducing the main amplifier voltage gain. The connection of a 1k resistor between pins 7 and 8 will reduce
both by approximately 20dB. Values less than 680Q
differential
are not advised.
Frequency response
The low frequency response of the SL6270C is
determined by the input, output and coupling capaciNormally the coupling capacitor between pins 2
and 7 is chosen to give a 3dB point at 300Hz,
tors.
158
72uV rms input pin 4

!4|mV rms|input pin 4
90mV rms input pin 4
>
tt
Voltage
between pins 4 and 5 must be
rms
OkilMM LOAD)
..
N.B.
mV
gam
10kQ
g^
Upper frequency response 10kQ/4.7nF

Lower frequency response 680Q/2.2|iF
Fig.
= 3kHz
= 300Hz
5 SL6270C frequency response
corresponding to 2.2jiF, and the other capacitors are

chosen to give a response to 1 00Hz or less.
The SL6270C has an open loop upper frequency
response of a few MHz and a capacitor should be
connected between pins 7 and 8 to give the required
bandwidth.
Attack and decay times

Normally the SL6270C is required to respond
quickly by holding the output level almost constant as
the input is increased. This 'attack time', the time taken
for the output to return to within 10% of the original
level following a 20dB increase in input level, will be
approximately 20ms with the circuit of Fig. 4. It is
determined by the value of the capacitor connected
between pin 1 and ground and can be calculated
approximately from the formula
Attack time
0.4ms/uF
The decay time is determined by the discharge rate of

the capacitor and the recommended circuit gives a
decay rate of 20dB/second. Other values jof (resistance
between pin 1 and ground can be used to obtain
|
different results.
SL6270C
100
II
<0
70
j
CO
Vs=
' 25 C
-1kHz
'
a.
*6V, TA
so
z
a
40
^/
INPUT (RMS)
Fig.
6 Voltage gain
(single
ended input)
Vg'SV,
(typical)
1k
is
S
sj
-
l
I
THIRD HARMONIC
SINGLE ENDED INPUT (mVRMSl

Fig.
7 Overload characteristics
(typical)
10
uu
8 z
11)
so
40
s
v
Vs-v
<
"-so
I
3
-M
THIRD OR
Fir
XR
rrrr"
20
ORDER
-o
10
lOOkHi
SINGLE ENDED INPUT (mV RMS)

Fig.
Typical Intermodulation distortion (1.55
and 1.85kHz
FREQUENCY
tones)
Fig.
9 Open loop frequency response
(typical)
159
SL6270C
160
SL6310C
SL6310C
SWITCHABLE AUDIO AMPLIFIER
The SL6310C is a low power audio amplifier which
off by applying a mute signal to the
appropriate pin. Despite the low quiescent current
(only 0.6mA when muted) a
consumption of 5
minimum output power of 400mW is available into an
supply.
a
9V
load
from
8Q
can be switched
MUTEB'
mm
mA
a-
^J|V^
K l-OC
Vcc
N0 MV. MPUT
20-1 INV INPUT
^^-JL-^^ N EARTH
FEATURES
OUTPUT
CM8/S
Can be Muted with High or Low State

Inputs
Operational Amplifier Configuration
Fig. 1 Pin
connections,
SL6310C
CM (bottom view)
Works Over Wide Voltage Range
mmm
APPLICATIONS
8 ]muteb'
wput[
wvmpur[
7 ] MUTE
earth[ 3
Audio Amplifier for Portable Receivers

Power Op. Amp
High Level Active Filter
output[
A'
5 ]Vcc
DP8
Fig. 2 Pin connections SL6310C DP (top view)

Supply Voltage 4.5V to
:
Output
into
3.6V
70dB
8Q on 9V Supply 400mW
Voltage Gain
MUTE'B MOTE
11
8
I'
A'

WOn
Supply voltage
5V
Storage temperature
INPUT
:
55C to
+125C
1|-
rrTTrir^
-^r
Fig.
3 SL6310C test circuit
161
SL6310C
Supply voltage Vcc 9VI
Ambient temperature 30C to +85C
Mute facility: Pins 7 and 8 open circuit
Value
Characteristic
Min.
Typ.
Supply current
Supply current muted (A)
Supply current muted (B)
5.0
0.55

Input bias current (Note 1)
Voltage gain
Input voltage range
40
0.6
0.9
50
20
500
0.2
60
500
bias current flows
Fig.
out
of pins
4 SL6310C lamp
and
due
PNP
to
Conditions
mA
mA
mA
mV
Pin 7 via 1 00k to earth

Pin 8
Vcc
mW
Fig.
facility
The SL6310C has two mute control pins to allow

easy interfacing to inputs of high or low levels. Mute
control 'A', pin 7, is left open circuit or connected to a
voltage within one volt of Vcc (via a 100kQ resistor)
for normal operation. When the voltage on pin 7 is
reduced to within 1 volt of earth (via a 100kQ resistor)
the SL6310C is muted.
Mute control 'B', pin 8, is left open circuit or connected to a voltage less than 1 volt for normal operation a
voltage greater than 2.5V on pin 8 mutes the device.
The input resistance at pin 8 is around 100kQ and is
suitable for interfacing with CMOS.
Only one mute control pin may be used at any time;
the unused pin must be left open circuit.
Audio amplifier
As the SL6310C is an operational amplifier it is easy
to obtain the voltage gain and frequency response
required. To keep the input impedance high it is wise
to feed the signal to the non-inverting input as shown
:
=
=
4.5V
1
3V
Rs<10k
Rl= 8Q
Pout = 400mW,
Gain= 28dB
input stage
driver
OPERATING NOTES
Rssj10k
Vcc
Vcc
0.4
Units
nA
uA
dB
V
V
dB
10.6
THD
162
7.5
70
40
400
Output power
Mute
2.1
CMRR
The input
Max.
5 SL6310C
servo amplifier
in Fig. 3. In this example the input impedance

is
approximately 100kQ. The voltage gain is determined
by the ratio (R3 +R4)/R3 and should be between 3 and
30 for best results. The capacitor in series with R3,

together with the input and output coupling capacitors,
determines the low frequency rolloff point. The upper
frequency limit is set by the device but can be restricted
by connecting a capacitor across R4.
The output and power supply decoupling capacitors
have to carry currents of several hundred milliamps and
should be rated accordingly.
Applications include hand-held radio equipment,
hi-fi headphone amplifiers and
Operational amplifier
line drivers.
impossible to list all their application possibilities in a single data sheet but the SL6310C
offers
considerable advantages over conventional devices in
high output current applications such as lamp drivers
(Fig. 4) and servo amplifiers (Fig. 5).
Buffer and output stages for signal generators are
another possibility together with active filter sections
requiring a high output current.
It
is
SL6310C
FREQUENCY
Fig.
VOLTAGE
Hz]
Fig.
6 Gain v frequency
7 Gain
v.
(V)
supply voltage
1500
NO N-MUTED
<
a LOAD
/ /load
/ 8"
o
MUTE
^^^
^^MUTEA
M
/
E
C
16ft
LOAD
3
O
MUTE B PIN 8 TO SUPPLY
MUTEA'-PIN 7 TO EARTH V 100k RESISTOR
:
VOLTAGE
F/gr.
8 Supply current v. supply voltage
f/ff.
(V)
9 Oufpuf power v. supply voltage at 5% {max)
distortion
163
SL6310C
164
SL6440A/C
JUN82
ADVANCE INFORMATION
Plessey Semiconductors range which, "^'^^,',^11
Ce i^f^"oi^s~Td*ise"c7stomers of new additions to the
we would expect this performance da a to
ha^'preproduction- status. Details given may, therefore, change without notice although
your local Plessey Semiconductors Sales Office
contact
Please
cases.
in
most
pfoduct
be represSve of 'full production'Status
Adv
for details of current status.
SL6440A&C
HIGH LEVEL MIXER
The SL6440
is
a double balanced mixer intended for use in
radio systems up to 150MHz. A special feature of the circuit

allows external selection of the DC operating conditions by
means of a resistor connected between pin 1 1 (bias) and Vcc.
When biased for a supply current of 50mA the SL6440 offers
OUTPUT A [ 3
a 3rd order intermodulation intercept point of typically

+30dBm, a value previously unobtainable with integrated
This makes the device suitable for many
circuits.
applications where diode ring mixers had previously been
used and offers the advantages of a voltage gain, low local
requirement and superior isolation.

(in a 16-lead DIL plastic package)
specified for operation from -30C to +85C; the SL6440A
ceramic) has a military temperature range specification.
[ 2
OUTPUT
] SIGNAL INPUT A
] SIGNAL INPUT B
10 ]
Vct[ 4
LOCAL OSCILLATOR INPUT
* ]
] PROGRAMMING CURRENT INPUT
ov[
DG16
0P16
oscillator drive
The SL6440C
is
(in
Fig.
Pin connections
top view
Supply voltage and output pins: 15V

Power dissipation (package limitation): 1200mW
(Derate above 25 C: 8mW/C)
Storage temperature range: -65 C to +150 C
+30dBm Input Intercept Point

+15dBm Compression Point (1dB)
Programmable Performance
-55C to +125C Temperature Range
Programming current
in
into pin
1 1
50mA
PACKAGE THERMAL DATA - BOTH PACKAGES
APPLICATIONS
Thermal resistance: Junction-Ambient: 125 C/W
Radio Transceivers
Junction-Case: 40 C/W
1.9 mins.
Phase Comparators
Time constant: Junction-Ambient:
Modulators
II
FEATURES
Mixers
Max. chip temperature: 150 C
BAAn
= 12V; Vcc2 = 10V; P = 25mA; T amb = -55C to +125C (SL6440A), -30C to +85C (SL6440C)
Local oscillator input level = OdBm; Test circ uit Fig. 2.
Vcd
Characteristic
Signal frequency
Min.
100
100
3dB point
3dB point
Oscillator frequency
3rd order input intercept point

Third order intermodulation distortion
Second order intermodulation distortion
1dB compression point
Noise figure
Conversion gain
(total
from
Vcd &
Supply current
in
Pin 3
is
MHz
MHz
dBm
11
-1
dB
dB
dB
-25
dBm
dB
dB
dBm
dBm
mA
mA
60
250
Vcc2)
equal to that
in
Pin 14
and
is
mVrms
1.5
kQ
500
1000
Q
n
equal to
In
See
over.
V P n11
Conditions
Units
150
150
+30
-60
-75
15
12
Local oscillator input

Local oscillator input impedance
Signal input impedance
NOTE
Max.
-40
Carrier leak to signal input

Level of carrier at IF output
Supply current
Supply current
J/aJus_
Typ.
Two OdBm
input
Signals
Vcd
Vcd
=
=
15V
12V
Vcc2
Vcc2
12V
10V
Fig.8 test circuit
50fi load Fig.2

Test circuit Fig.8
See applications information
l
35mA
Single ended
Differential
3VoeSS2.1V
165
SL6440A/C
CIRCUIT DESCRIPTION
The SL6440
RF
l
is a high level mixer designed to have a linear

performance. The linearity can be programmed using the
pin (11).
The output pins are open collector outputs so that the

conversion gain and output loads can be chosen for the
The current
via
GdB
frequency response
GdB
Minimum Vcd
(l P
programmed current
RL
DC
max
Vs
if
the signal swing
minimum Vcd
is
= 2
In this case the signal

output saturates.
x RL) + Vs + Vcc2
signal swing at output
not known:
P x RL) + Vcc2
be
is
RL
|
+ o.o785| for single-ended output
pi
Device dissipation
is
for differential output
o 078q
calculated using the formula
Vo + V P P + Vcc2 Diss
= voltage on pin 3 or pin 14
VP
= voltage on pin 1
lp
= programming current (mA)
Vcc2 Diss= dissipation obtained from graph(Fig.5)
= 2 P
l
where Vo
As an example Fig. 7 shows typical dissipations assuming

Vcd and Vo are equal. This may not be the case in practice
and the device dissipation will have to be calculated for any
load resistance
particular application.
Fig. 4 shows the intermodulation performance against
P
The curves are independent of Vcd and Vcc2 but if Vcd
becomes too low the output signal swing cannot be
accommodated, and if Vcc2 becomes too low the circuit will
not provide enough drive to sink the programmed current.
Examples are shown of performance at various supply
l
(l
will
log
mW diss
saturation.
where
into pin 11 can be supplied

or from a current source.
equal to
Vcd
reduce as the output transistors near
will
programmed
P)
^g
o
20 Log
Ts 6
= 20
specific application.
Since the outputs are open collectors they should be

returned to a supply Vcd through a load.
The choice of Vcd is important since it must be ensured
that the voltage on pins 3 and 1 4 is not low enough to saturate
the output transistors and so limit the signal swing
unnecessarily. If the voltage on pins 3 and 14 is always
greater than Vcc2 the outputs will not saturate. The output
(l
a resistor from
The conversion gain
limiting at the input before the
The device has a separate supply (Vcc2)
for the oscillator
buffer (pin 4).
voltages.
WCOMPM 8SI0N POINT
|Vcci-v
+
_ \Yc c 2-12V
lYccl-MV
T
\Vc c 2-10V
LOCAL OSCIUA TOH-MHz0dBm
""-HI
"X
IF
-10MHz
oooiv
/7T77
nrrt
HI-
fTTTl
O' 001
If
Fig. 2
Typical application
+
(mA)
TOTAL OUTPUT CURRENT (2L,)
and
test circuit
Fig.3
Compression point
total
v.
output current
WANTED OUTPUT
LO-3 1.4MMi0d
-10
Ml
MMHiOd
30.01
Km Odtm
1
-V^
8
7
>
Vcd
I' \\
>v
Vcc2 - sv
Vcc
Vcc
-V
-V
Vccl - 10V
Vcc2 - V
1
J
I
-50
\l
x
i
Fig.4
166
Vc 1-12V
Vcc J -10V
%l
/I
"*
\/
î/
2nd
omen imd
PROGRAMMING CURRENT (mA)

Intermodulation v. programming
Fig.5
Supply current
v.
Vcc2
(lP
0)
i
i
;
current
The current in pin 1 4 is equal to the current in pin 3 which

equal to the current in pin 11.
is
SL6440A/C
T
T
T
_ T.
T.
"*
--
i-<
3 -i
o
-*
SKMOU. 10MHz HIOHER-
THAN LOCAL OSCILLATOR
"W
-w
-J
Q
UJ
-^
\
\\
-7
\*
LOCAL OSOLLATOR NPUTIVEL-0dBm

RF INPUT LEVEL
Vc-SVf
1,-24 |A
"
VCC1-12VI
-10V) *
Vcc2
-11
1
LOCAL OSCILLATOR FREQUENCY MHz

Fig.6
Frequency response
APPLICATIONS
The SL6440 can be used with differential or singleended inputs and outputs. A balanced input will give
better carrier leak. The high input impedance allows stepup transformers to be used if desired, whilst high output
impedance allows a choice of output impedance and
constant output IF
Decide on input configuration using local oscillator data.

using transformer on input, decide on ratio from noise
considerations.
Decide on output configuration and value of conversion
2.
gain required.
Decide on value of P and Vcc2 using intermodulation and
3.
1
If
conversion gain.
application circuit. The input
and output are single-ended and P is supplied from Vcd
conversion
via a resistor. Increasing RL will increase the
gain, care being taken to choose a suitable value for Vcd
input, for
balanced
Fig. 8 shows an application with
improved carrier leak, and balanced output for increased
conversion gain. A lower Vcd giving lower device
Fig. 2
at
DESIGN PROCEDURE
shows the simplest
compression point graphs.

Using values of conversion gain, Vcc2, load and lp
4.
already chosen, decide on value of Vcd.
Calculate device dissipation and decide whether
5.
heatsink is required from maximum operating temperature
considerations.
can be used with this arrangement.

Further Applications information is available. Request
dissipation
AN1007 and AN1009.
/7777
!...
/7777
-Hcc-
0-1*i
VCC-12V
LTAO ONI MS 3,
<fcc-<
1AM
JT
iomîou
/7777
Vc C - 10V
uuu
as*
soreRATION WITI OUT EAT! MK
ci.
Vcc-V
czz>
.Vcc-OV
..._
600
-Ycc-SV
n
i con 3UTH
o
400
win OUJ_ EATS
/7777
/T777
-;
R
in
Fig. 8
Fig.7 Device dissipation
v.
put9
"^"
1:1 - 5
1 -5
* 8
Typical application circuit for highest performance
lp
167
SL6440A/C
168
SL6601
^^P' Semiconductors
SL6601C
LOW POWER
IF/AF PLL CIRCUIT
FOR NARROW BAND FM
The SL6601 is a straight through or single conversion IF

and detector for FM radio applications. Its minimal
power consumption makes it ideal for hand held and remote
applications where battery conservation is important. Unlike
'**
amplifier
CRYSTAL [
MIXER DECOUPLE [
integrated circuits, the SL6601 uses an advanced

phase locked loop detector capable of giving superior signal-
many FM
excellent
with
to-noise
ratio
rejection,
and operates with an
co-channel
IF
2N0
interference
of less than
2ND
18
IF
IF
FILTER
IFI P
] EARTH
!6
] DECOUPLE
0EC0UPLE [
Vcc
] IVCO
TIMING
-.
1MHz.
SQUELCH
be fed with an input signal of up to

17MHz: there is a crystal oscillator and mixer for conversion
to the IF amplifier, a PLL detector and squelch system.
Normally the SL6601
CRYSTAL [
will
0.
SQUELCH TRIGGER FILTER
AFOP
[
VCO TIMING RESISTOR
CAPACITOR
LOOP
FILTER
] VCO TIMING RESISTOR
FEATURES
TOP VIEW
2uV Typical
2-3mA Typical at 7V
High
Sensitivity:
Low
Power:
Advanced PLL Detector

Available
1
00%
in
Miniature 'Chip Carrier'
Tested
for
Package
SINAD
16
W
15
M
5|
6l
15
3
3
14
16
C
C
C
4
5
2nnn=I
DP18
BOTTOM VIEW
w"ii
11
10 9
GC18
CONNECTIONS AS DG/DP 18 PACKAGE

Fig.1 Pin
connections
APPLICATIONS
Low Power NBFM Receivers

FSK Data Equipment
Cellular Radio
Supply Voltage 7V
50dB S/N
Telephones
Ratio
NOTE, RESISTIVE
IMPEDANCE
AT PIN 4 = 2Skn.(TYP),36k/i(MAX)
INPUT
1|-
K^fc
HWER ~fa
DECOUPLE
rfn
i^lLTER sfr
[DECOUPLE
=10011 .33p
rrn
rrn
:=WOn
rm
lefoECOUPLE
I
~WOn
rrn
_,_
1
-r
WOk
*CC
Fig.2
SL6601 block diagram
169
SL6601
Supply voltage Vcc
7V
Input signal frequency: 10.7MHz, frequency modulated with a 1kHz tone with a 2.5kHz frequency deviation
Ambient temperature: -30 C to +85 C; IF = 100kHz; AF bandwidth = 15kHz
Value
Characteristic
Min.
Supply current
100
Input capacity
0.5
Maximum
0.5
input voltage level
Sensitivity
Audio output
Audio THD
+ N/N
rejection
Squelch low
Squelch high
Max.
2.3
Input impedance
AM
Typ.
2.7
300
2.0
3.5
35
90
140
1.3
3.0
30
50
30
Note
level
level
6.5
30
100
Squelch output load

Input voltage range
dB
dB
dB
//V
250
80
3rd order intercept point (input)
%
Vdc
Vdc
Input gain compression
PF
V rms
iV rms
mV rms
0.5
6.9
Conversion gain
mA
O
dB
dB
0.2
Squelch hysteresis
Noise figure
Units
rms
Conditions
Source impedance
200fi
At pin 18
At pin 18 for
1mV rms
1mV rms
+ N/N = 20dB
input at pin 18
input at pin 18
rms input at pin 18,

rms input at pin 18
100//V
20/uV
No
30% AM
input
3fj\/
input at pin 18
50O source
Pin 18 to pin 4
Pin 18 to pin
4,
1dB compression
100
kO
dB
-38
dBm
Input pin 18, output pin 4
kHz
kHz
kHz
390pF timing capacitor

At pin
8;
+ N/N
above 20dB S
VCO frequency
Grade 1
Grade 2
Grade 3
Source impedance (pin
AF output impedance
Lock-in dynamic range
External
LO
85
100
95
110
105
120
4)
25
40
kfJ
10
kfi
kHz
20/A/ to
250
mV rms
o
At pin 2
drive level
50
CrystaTESR
25
1mV rms
j
>
No
input
at pin 18
10.8MHz
APPLICATION NOTES
external capacitor according to the formula <35)pF, where f

is the
frequency in MHz. The nominal frequency may
differ from the theoretical but there is provision for a fine
frequency adjustment by means of a variable resistor
between the
output pins; a value of 470k has negligible
effect while 6.8k (recommended minimum value) increases
VCO
IF Amplifiers
and Mixer
The SL6601 can be operated either in a 'straight through'

with a maximum recommended input frequency of
800kHz or in a single conversion mode with an input
mode
frequency of 50MHz maximum and an IF of 100kHz or ten

times the peak deviation, whichever is the larger. The crystal
oscillator frequency can be equal to either the sum or
difference of the two IF's; the exact frequency is not critical.
The circuit is designed to use series resonant fundamental
crystals between 1 and 17MHz.
When a suitable crystal frequency is not available a
fundamental crystal of one third of that frequency may be
used, with some degradation in performance,
recommended level is 70mV rms and the unused pin should
be left O/C. The input is AC coupled via a 0.01//F capacitor.
A capacitor connected between pin 4 and ground will
shunt the mixer output and limit the frequency response of
the mixer output and limit the frequency response of the
input signal to the second IF amplifier.
advised when the second IF frequency
advised for 455kHz.
value of 33pF
100kHz; 6.8pF
the frequency by approximately 20 %.

Care should be taken to ensure that the free running VCO
frequency is correct; because the VCO and limiting IF
amplifier output produce square waves, it is possible to
obtain lock with the VCO frequency fractionally related to the
IF, e.g. IF = 100kHz, VCO = 150kHz. This condition
can
produce good SI NAD ratios but poor squelch performance.
The loop filter is connected between pins 1 1 and 12; a 33k
resistor is also required between pin 1 1 and Vcc.
The values of the filter resistor R2 and capacitor C1 must
be chosen so that the natural loop frequency and damping
factor are suitable for the FM deviation and modulation
bandwidth required. The recommended values for various

conditions are tabulated below:
is
Centre frequency
Deviation
Resistor
is
kHz
kHz
kO
PF
100
6.2
2200
100
455
10
5.6"
1800
detector features a voltage
4.7
1500
nominal frequency set by an
455
10
3.9
is
Phase Locked Loop
The Phase Locked Loop

controlled oscillator with
VCO
Note that the values of loop

many cases may be omitted.
170
filter
are not
Capacitor
1200
critical
and
in
SL6601
The AF output voltage depends upon the
% deviation and
inversely proportional to
centre frequency. As the noise is constant, the signal to noise
ratio is also inversely proportional to centre frequency.
so, for
VCO
a given deviation, output
is
Frequency Grading
is supplied in 3 selections of VCO centre

frequency. This frequency is measured with a 390pF timing
capacitor and no input signal.
Devices are coded 'SL6601C and a 7V, 72', 73' to indicate
the selection.
Frequency tolerances are:
The SL6601
Operation at signal to noise ratios outside the range 5is not recommended. Where the 'front end' noise is
high (because of very high front end gain) the squelch may
well never operate. This effect can be obviated by sensible
receiver gain distribution.
The load on the squelch output (pin 6) should not be less
than 250kO. Reduction of the load below this level leads to
hysteresis problems in the squelch circuit.
The use of an external PNP transistor allows hysteresis to
be increased. See Fig.3. The use of capacitors greater than
18dB
1000pF from pin 6
85 100kHz
95 -110kHz
105 - 120kHz
Note that orders cannot be accepted for any particular
selection, but all devices in a tube will be the same selection.
Outputs
Squelch
used.
/1
/2
/3
Facility
When inputs to the product detector differ in phase a series

of current pulses will flow out of pin 7. The feature can be
used to adjust the VCO; when a 1mV unmodulated input
frequency should be
signal is applied to pin 18 the
trimmed to maximise the voltage on pin 7.
The squelch level is adjusted by means of a preset variable
VCO
between pin 7 and Vcc to set the output signal to

noise ratio at which it is required to mute the output. The
capacitor between pin 7 and ground determines the squelch
attack time. A value between 10nFand 10j/Fcan be chosen to
give the required characteristics.
resistor
ground
to
is
not recommended.
High speed data outputs can be taken direct from pins 1

and 12 but normally for audio applications pin 8 is used. A
filter network will be needed to restrict the audio bandwidth
and an RC network consisting of 4.7kO and 4.7nF may be
Layout Techniques and Alignment

is not critical in PCB layout requirements
the 'straight through' mode. In this mode, the input
components and circuits should be isolated from the VCO
components, as otherwise the VCO will attempt to 'lock' to
The SL6601
except
itself,
in
and the ultimate
signal to noise ratio will suffer.
The recommended method of VCO adjustment is with a

frequency measurement system on pin 9. The impedance
must be high, and the VCO frequency is adjusted with no
input signal.
i-fi-ii-irSnr-ii-ii-i
IT
W IS 14 13 12
II
Fig.3 Using
an external
PNP in
Fig.4
the squelch circuit
(1st IF
SL6601 application diagram
10.7MHz, 2nd IF
100kHz)
[
PFM.T
L
DEV UTION
FMOOlkH
I "
AF
1* i2n
\
I
ANOW DTH1
L<X PF1LT
IATK9N
RO^k
L2n
FW OlkH
-M0
-1M
-100
-30
-SO
-40
-70
-00
-m
INPUT LEVEL (dBm) AT PIN 18
-20
(signal
noise
SINAD
+ distortion!noise +
-120
-110
-100
-00
-00
40
-70
-40-30-20-10
-SO
INPUT LEVEL (dBm) AT PIN
INPUT VOLTAGE LEVEL (dBm) AT PIN 1*

Fig.5 Typical
-10
18
INPUT VOLTAGE LEVEL (dBm) AT PIN
Fig.6 Typical recovered audio
v.
18
input level (3kHz deviation)
distortion)
171
SL6601
.,
85
VARIATION WITH
TEMPERATURE
TVPIO L
MINIML
Vcc = 7V
M
GUARANTEED
OPERATIVE
AREA
VARIATION WIT
J^
ss
SUPPLY VOLTA( *-^^^

T = 2S'C
-30
SUPPLY VOLTAGE
Fig.7
Supply voltage
v.
Vco FREQUENCY DRIFT (%)
(V)
Fig.8 Typical
temperature
VCO
\.
LOC PFILT :R6Jk
V-H
*< =^
2.2n
IATION 3kHz
FM JDIkl
s
S
^"""
INTERNAL NOISE LEVEL

OWIDTIH)
t
z
characteristics
\
>
\^
o
(A
-120
INPLTT
LEVEL (dBm) AT PIN
Fig.9 Typical squelch current
v.
-110
-100
18
input level
Fig.
10 Typical
AM rejection
(the ratio
(a)
I
a
<
2Ml IF
-10
= 100kH2
(b)
between the audio output produced by:

a 3kHz deviation 1kHz modulation FM signal and
a 30% modulated 1kHz modulation AM signal at the
same
input voltage
level.)
-20
?
>
<
-40
-50
Supply voltage
Storage temperature
-60
i-
3
Q.
9V
-55
O
80
(see Electrical Characteristics)

Input voltage
Fig. 11
172
to
+125 C (DP package)

+150 C (DG/GC)
-55Cto +125C
-55 C to
-70
Typical conversion gain (to pin 4)
1V
RMS
at pin
18
SL6691C
Semiconductors
SL6691C
MONOLITHIC CIRCUIT FOR PAGING RECEIVERS
The SL6691C
is
an
IF
system for paging receivers,
consisting of a limiting IF amplifier, quadrature demodulator,

voltage regulator and audio tone amplifier with Schmitt
trigger.
The voltage regulator requires an external PNP transistor

as the series pass transistor. The frequency response of the
tone audio amplifier is externally defined.
The SL6691C operates over the temperature range -30 C
to +85 C.
SUPPLY (V B )
scwutt trigger 0/p
time ampuher 0/p
tom mwuher up
] REGULATED SUPPLY LINE
demodulator ojp
] IFAMPI/F
quadrature coil
quadrature coil
[ 6
] EARTH
demodulator dhver
] IF
demodulator driver
[ 8
] IFAMPO/P
16
] SERIES PASS TRANSISTOR ORtVER
IF
AMP IP
AMP
0/P
FEATURES
Very Low Standby Current
Wide Dynamic Range

Minimum External Components
qpi g
Fast Turn-on
SOMTTTFJGGER OUTPUT
TOM MffUHER OUTPUT
\
/
2
18
JU UU
I
BASED
E17
3 NC
4 TORE AMPUHER WITT
5 OEMOEUATOR OUTPUT
HEEUATED^n 16
VMATJRERRMT 15
APPLICATIONS
f NWUmiVUT 14
6|
>
EARTH
Portable
JLtjjl
FM
OUHMTURECOi
13
Pagers
GC18
Broadcast Receivers
BOTTOM VIEW
Storage temperature - 65C to + 1 50C

Supply voltage 6V
10
11
TOP VIEW
Fig.1 Pin connections (top view)
11
LIMITING IF
AMPLIFIER
54
DEMODULATOR
l
VCCORVB
TONE AMP 0/P
Fig.2
SL6691C
test circuit
Fig.3
SL6691C block diagram
173
SL6691C
Temperature
-30C to +85C
Supply voltage (Vc
2.5V
)
455kHz (nominal)
500Hz
4.5kHz
IF frequency
Modulation frequency
Deviation
Value
Characteristic
Min.
Quiescent current
Typ.
1.0
Conditions
Units
Max.
1.4
mA
Vb
=3V
S/C
and4 0/C
Pins 2 and 3
Pinsl
Switch on time
12
18
ms
Notel
2.1
V
dB
Vb > 2.2V
Vb > 2.2V
200mV p-p square wave @ 500 Hz
Voltage regulator
Regulated voltage
Supply line rejection
1.9
40
injected
Current sink capability pin
uA
100
IF amplifier
Input impedance
Output impedance
Dynamic range
Output voltage swing
Amplifier gain
Sensitivity
AM rejection
Amplifier
kO//pF
20//2
2
20
3dB bandwidth
kQ
dB
100
600
90
16
40
mVp-p
dB
uVrms
dB
MHz.
1.5
Audio 20dB S+N/N ratio

1 OOuV rms
/P @ 30% AM modulation
I
Demodulator
Audio output
THD
mVrms
15
Quadrature element L-C tuned
circuit
Q = 30
1.5
Output impedance
Signal-to-noise ratio
40
dB
Open loop gain
54
Peak output current
20
dB
uA
Schmitt trigger
Mark space ratio
Output current
45/55
Distortion,
kfi
100uVrms
l/P
3kHz audio bandwidth
Tone amplifier
38/62
150
20nVrms
l/P
uA
NOTES
The 'Switch On' time is the time to the zero crossing point of the centre of the first occurrence of a 30/70 or 70/30 mark space
1
output of the Schmitt trigger after the supply voltage has been switched on. Conditions: V = 2V,Tone filter connected
wave on the
IF inDut -
(See Fia 2)
100MVrms,Modulation500Hz@2kHzdeviation.
CIRCUIT DESCRIPTION
IF Amplifier
and Detector
The
IF amplifier consists of five identical differential

amplifier/emitter follower stages with outputs at the fourth
(pins 9 and 10) and fifth (pins 7 and 8) stages. The outputs
Ton* (Audio) Amplifier
The tone
amplifier
is
a simple
inverting audio amplifier
with voltage gain determined by the ratio of feedback

resistor to input resistor. The frequency response can
readily be controlled by suitable selection of feedback
components.
from the fourth stage are used when the lowest turn-on
time is required. Coupling to the quadrature network of the
detector is via external capacitors; otherwise the design is
conventional. The audio output is taken from pin 4 and
which saturates when the input at pin 2 is high. A 20pV rms
filtered externally.
input is sufficient.
174
Schmitt Trigger
The Schmitt trigger has an open collector output stage
SL6691C
NOMINAL DC
PIN VOLTAGES(DP16)
Voltage
Function
Pin
Supply
16 Battery voltage
15 Battery voltage -0.7V
14 2V
Series pass transistor driver
Regulated supply
line
OV
1V
1V
1V
1V
1V
1V
5 1V
Earth
11
IFampl/P
13
12
10
9
4
6
IF
IF
IF
amp l/P
amp 0/P
amp O/P
Demodulator 0/P
Quadrature
Quadrature
Tone
coil
coil
amplifier l/P
Schmitt trigger O/P
Tone amplifier O/P
Demodulator driver
Demodulator driver
1.4V
0V
2
7
or pin
16 or
pin
14
1.4V
1V
1V
175
SL6691C
176
SL6700A
^^P' Semiconductors
SL6700A
IF
AMPLIFIER
AND AM DETECTOR
The SL6700A is a single or double conversion IF amplifier

and detector for AM radio applications. Its low power
consumption makes it ideal for hand held applications.
Normally the SL6700A will be fed with a first IF signal of
10.7MHz or 21.4MHz; there is a mixer for conversion to the
first or second IF, a detector, an AGC generator with optional
delayed output and a noise blanker monostable. This device
is characterised for operation from -55 C to +125C.
XT7'
18
]fmput
[ 2
]hhth
l 3
16
]GCDtC0UPUNG
ftGCKCOUFlMG [
MOMS
wthbte|
mUPlMG U
I
M5
is ] AUDIO OUTPUT
DBAYH>GC OUTPUT [ 5
foumjr [6
FEATURES
MXERWUT
High
Sensitivity:
Low
Power:
Typical at
6V
[ 7
12
MKBUWBITMH6CM>WrraR
ma output
n ] M6EBUIKR OUTPUT
L0CM0SC.MFUT
]Vcc
10pV Minimum
8mA
]DBajFlN6P0NT
13 ] DETtCTORMFUI
Linear Detector
Full
DG18
MIL Temperature Range

Fig. 1
APPLICATIONS
Low Power AM/SSB Receivers
Input
7.5V
Supply voltage
Storage temperature
Supply Voltage: 4.5V
C to +150 C
-55 C to +125C
-55
Dynamic Range: 100rJB Typical
NOISE
GROUNO
r~i"
_Oli
BLANKER
NOISE
TIMING
BLANKER
CAPACITOR
OUTPUT
+6V
SUPPLY
JZl
-WIF AMPLIFIER
V r%^
)>
IF AMPLIFIER
CCT
07
rir
LJ3
Lil t
INTERSTAGE
COUPLING
Oi
or
DELAYEO
AGC
TJi
Cli
IF
MIXER
OUTPUT
INPUT
MIXER
OUTPUT
O?
LOCAL
OSC
OUTPUT
TERMINALS
Fig.2
SL6700A block diagram
177
SL6700A
Tamb-55C to +125C Test circuit Fig.6. Modulation frequency 1kHz
Value
Characteristic
Mln.
Supply voltage
Typ.
Supply current
3.5
S/N
40
TH
ratio
distortion
Sensitivity
10
Audio output
AGC
AGC
AF
change
level
output
Delayed
20
level
AGC
mA
10
threshold
AV
dB
mV
mV
rms
rms
dB
25
MHz
IF amplifier gain
40
50
Detector gain
40
46
55
6.8
kfi
1.8
4.5
kfi
0.3
V
V
Detector
Zm
pin 13
Zm
IF amplifier
Noise blank
pin 18
level
10//Vto50mVinput80%
dB
80
40
100
frequency response
1mV input 80% modulation

1mV input 30% modulation
10dBS + N/N ratio, 30%
15
IF
60
80
gain reduction
10.7MHz (both amplifiers cascaded)

455kHz 80% AM
Logic
Logic
300
400
500
/JS
pin 12
Mixer conversion gain
1.0R
1.2R
1.5R
kfi
is
kfi
150
8.2
Zm
(Signal)
Mixer Zm (L.O.)
Mixer L.O. injection
50
5
100
Detector output voltage change
input
Noise floor to overload
3dB
dB
dB
4.0
% modulation 1mV
% modulation
30
Noise blank duration

Mixer
at 4.5V
//V
10
Dynamic range
Conditions
Optimum performance
dB
5
range
Units
5
6
threshold
Max.
= 30nF,R
pin 12-11
18k
load resistor in kfi
kfi
mV
rms
dB
= 10.245MHz
mV rms input, modulation
fc
1
from
30%
to
increased
80%
OPERATING NOTES
The noise blank duration can be varied from the suggested
value of 30/js using the formula: Duration time = 0.7CR,
where R is value of resistor between pins 1 1 and 1 2 and C is
value of capacitor from pin 12 to ground.
There is no squelch in the SL6700A and the delay in the
delayed
is too large to make this output suitable.
Squelch is best obtained from a comparator on the
m0"
""'
10011
^ X
AGC
AGC
decoupling point, pin
The
IF amplifiers
17
16
IS
13
12
11
10
16.
may be operated
at
455kHz giving a
SL6700A
single conversion system.
The mixer may also be used as a product detector. Further

application information is available on request.
application information is available on request in Application
"Y
10-245 M*
NoteAN1001.
fl"
2U/M
TAP AT 257.
Ou*
TYPICAL DC PIN VOLTAGES
75
(Supply 4.5V, Input 1mV)
178
Pin
Voltage
Pin
Voltage
2.25V
10
4.5V
3.7V
2.09V
11
3.68V
12
OV
0.7V
13
0.77V
5
6
0.6V
14
1.5V
3.7V
15
1.0V
1.5V
16
0.7V
4.3V
17
OV
1.5V
18
0.7V
Fig.3
SL6700A
AM double conversion receiver with noise blanker
SL6700A
m
+50
o
<
t
UJ
PIN 5
kA LOAD
5
z
O>30
1
+ 40
+ 60
5
Z
INPUT (dBjjV RMS]
Fig.4 Typical delayed

(f
AGC output variation
10.7MHz,
30%
+20
<
Z
with input signal
+60
+A0
+20
+60
+100
INPUT IdBpV RMS)
modulation)
F/g.5 Typ/ca/ signal to noise ratio (S

(f
10.7MHz,
30%
N/N) with input signal
modulation)
Hh-i
*
,,
-L
d_
fl.
1nf
rSrHrHr^r^fîr^r^l
.
18
17
16
15
14
13
12
SL6700A
11
10
LfT
^T^Tî
Pin1
r7^77
15
/7777
F/g.6 Tesf circuit
179
'
SL6700A
/
O
*
~
I
'
t **S of'
tH*2
"g
rM
Z0<0<2
F/g.7
180
SL6700A Typical application
circuit
showing
interfacing
<
SL6700C
ADVANCE INFORMATION
*^F Semiconductors
SL6700C
IF
AMPLIFIER
AND AM DETECTOR
is a single or double conversion IF

and detector for AM radio applications. Its low
power consumption makes it ideal for hand held
applications. Normally the SL6700C will be fed with a first
IF signal of 10.7MHz or 21.4MHz; there is a mixer for
conversion to the first or second IF, a detector, an AGC
generator with optional delayed output and a noise blanker
The SL6700C
amplifier
AGC DECOUPLING [
3
INTERSTAGE
'"
COUPLING TERMINALS
monostable.
DELAYED AGC OUTPUT [
FEATURES
High
Sensitivity:
IF
,8 ]
IF
INPUT
] EARTH
AGC BIAS [
OUTPUT [ 6
16 ] AGC DECOUPLING
] AUDIO OUTPUT
] DECOUPLING POINT
13 ] DETECTOR INPUT
MIXER INPUT
] NOISE BUNKER TIMING CAPACITOR
MIXER OUTPUT
] vcc
tyV minimum
Low Power: 8mA Typical
at
NOISE
BUNKER OUTPUT
6V
LOCAL OSC. INPUT
Linear Detector
DP18
APPLICATIONS
Fig.
Low Power AM/ SSB Receivers

Supply voltage: 7.5V
Supply Voltage: 4.5V

Input
Dynamic Range: 1 0OdB Typical
AGC
INPUT
GROUND
r 1"
DECOUPLING
[I*
AUDIO
OUTPUT
r-1'5
55C to
+125C
DECOUPLING DETECTOR
POINT
[^
INPUT
[î
_I=ZL1
DECOUPLING
BIAS
Fig.
SL6700C block diagram
181
SL6700C
Tst conditions (unless otherwise stated):
Supply voltage 4.5V
TAmb-30Cto+85C
Value
Characteristic
Min.
Typ.
Max.
Units
Supply voltage
Supply current
4.5
mA
S/N
40
dB
TH
ratio
distortion
10
Audio output
AGC
AGC
AF
level
change
threshold
Delayed
threshold
10//V to
50mV
rms
rms
dB
MHz
IF amplifier gain
40
50
60
Detector gain
40
6.8
1.8
4.5
Noise blank
2.7
Noise blank duration

Mixer
Zin (signal)
Mixer Zm (LO)
Mixer
LO
55
300
Mixer conversion gain
injection
Detector output voltage change
ratio,
input
% modulation
% modulation
@ 1kHz
@ 1kHz
30% mod 1kHz

80% mod 1kHz
1kHz
Noise floor to overload
3dB
gain reduction
Logic
46
4
level
80
0.6
pin 13
30
dB
dB
kO
kO
V
V
IF amplifier Zin pin 18
Zm
n/N
at 4.5V
dB
50
Detector
80% mod
80% mod
10dB S
100
frequency response
input
input
dB
40
IF
1mV
1mV
/"V
mV
mV
10
Dynamic range
Optimum performance
//V
80
25
level
AGC
10
range
output
Sensitivity
Conditions
10.7MHz (both amplifiers cascaded)

455kHz 80% AM 1kHz
Logic
fJS
pin 12
1.0R
1.2R
1.5R
kfi
is
kO.
20
50
150
8.2
=30nF
load resistor
in kfi.
kfi
mV
rms
dB
fc
10.245MHz
1mV rms
input,
1kHz modulation
% to 80 %
increased from 30
OPERATING NOTES
The noise blank duration can be varied from the
suggested value of 300ns using the formula: Duration time
- 0.7CR, where R is value of resistor between pins 1 1 and
12 and C is value of capacitor from pin 12 to ground.
There is no squelch in the SL6700C and the delay in the
delayed AGC is too large to make this output suitable.

Squelch is best obtained from a comparator on the AGC
decoupling point, pin 16.
The IF amplifiers may be operated at

single conversion system.
455kHz
giving

application
information
is
available
in
Application Note
AN1001.
TYPICAL DC PIN VOLTAGES

(Supply 4.5V, Input 1 mV)
Pin
Voltage
Pin
2.25V
2 09V
3.68V
0.7V
0.6V
3.7V
1.5V
4.3V
10
1.5V
182
11
12
13
14
15
16
17
18
Voltage
4.5V
3.7V
0V
0.77V
1.5V
1.0V
0.7V
0V
0.7V
Fig.
3 SL6700CAM double conversion receiver with noise blanker
SL6700C
m
+50
o
K
PIN 5
.10
kA LOAD
+30
6
6
<
INPUT (dBpV RMS)
Fig.
Typical delayed AGC output variation with input signal
(f=10.7MHz,
INPUT (dB(iV
30% modulation)
Fig.
RMS)
Typical signal to noise ratio (S+NIN) with input signal
(f=10.7MHz,
30%
modulation)
183
SL6700C
i^^s.
3
a
1
zo<o<z
Fig.6
184
SL6700C
Typical application circuit showing interfacing
TAB1042
Semiconductors
TAB1042
QUAD PROGRAMMABLE OPERATIONAL AMPLIFIER
The TAB1042
is
an advanced bipolar integrated
circuit containing four separate programmable operational amplifiers. The four amplifiers are programmed by
current into a common bias pin which determines the
main characteristics of each amplifier, supply current,
<
16
] NON-INVERTING INPUT C
inverting input a c
15
] INVERTING INPUT C
outputaC
14
] OUTPUT C
suppiy[
13
] NEGATIVE SUPPLY
0UTPUTB[
12
] OUTPUT D
B[
II
] INVERTING INPUT
NON INVERTING INPUT B [
10
BIAS[
positive
frequency response and slew rate.

For example, with a suitable choice of bias current,
the TAB1042 will perform in a manner similar to four
amplifiers of the 741 type, but with improved frequency
response and input characteristics.
The TAB1042 is especially suitable for use in active
filter
non-inverting input a [
INVERTING INPUT
] NON-INVERTING INPUT D
]N/C
DPI 6
applications.
Fig. 1
APPLICATIONS
FEATURES
Four Independent Op. Amps,
Pin connections
in
Active
One
Filters
Package
Oscillators
Internally Compensated
Wide Range of Supply Voltages from
1.5Vto 12V
Low
Voltage Amplifiers
No Latch-Up
Supply Voltages 1 .5V to 1 2V

Supply Current 40uA to 2mA
Operating Frequency Range 1 MHz
Gain 95dB
Operating Temperature Range -40C to
Programmable Over 1 00 :1 Current Range

Gain Bandwidth Product Up to 4MHz
Built-in Short Circuit Protection
Low Noise
Fig.
Circuit
+85C
diagram
185
TAB1042
Tamb 25C
Operating
Operating
Operating
mode A Supply
mode B Supply
mode C Supply
12V
volts
volts
volts
1
1
Bias set current 75Â

2V Bias set current 1 nA
.5V Bias set current 1 yA
Operating
Characteristics
Mode
Conditions
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

mV
20
200
50
50
250
500
30
100
30
100
nA
nA
Input bias current

Input resistance
0.1
Supply current
Large signal
0.6
0.5
1000 1600 2200
volt gain
0.5
42
20
40
MO
60
/iA
74
95
66
90
66
90
dB
Input voltage range
10
10.5
10
10.5
0.2
0.4
Common mode
70
110
10.8
75
96
4
rejection ratio
Supply voltage rejection
ratio
Short circuit current
2.5
82
82
dB
0.3
0.2
75
86
75
86
dB
0.1
0.25
0.22
mA
RL = 4kO(A)
RL = 100kO(B)
RL =4kO(C)
Rs10kO
Tamb0CtO70C
50
50
kHz
Gain
20dB
MHz
3.5
rate
RL = 4kO(A)
RL = 100kO(B)
RL = 100kO(C)
Rs10kO
10.8
Slew
Rs 10kfi
1.5
0.02
0.02
V/fjs
Input noise voltage
15
45
45
Input noise current
1.6
1.6
1.0
nVA/Hz
pA/VHz
Gain
=
=
fo
fo
= 20dB
1kHz
1kHz
OPERATING NOTES
Bias set current
The amplifiers are programmed by the Iset current

into the BIAS pin to determine the frequency response,
slew rate and the value of supply current. The relationship
is
summarised as follows

Power supply current
(each supply)
Iset
Iset
x 25u.A
Slew
Iset
x 0.02 V/ns
rate
V SUPPLY
2V
50kHz
:
(Iset in
15
uA)
The open loop voltage gain is largely unaffected by

change in bias set current but tends to peak sliqhtlv at
10nA.
Since the voltage on the BIAS pin is approximately
0.65V more positive than the negative supply, a resistor
may be connected between the bias pin and either 0V
"1
or the positive supply to set the current. Thus, if the

resistor is connected to 0V, the Iset current is deter-
BIAS SET CURRENT
mined by:
Vs - 0.65
Iset
where R is value of the 'set' resistor.

The output goes high if the non-inverting input is
taken lower than 1 V above the negative power supply.
186
Fig.
3 Supply
v.
(jiA)
current (each supply)
bias set current
TAB1042
000
SUPPLY
I*
V<
wiuu
+ 2S' C
12
SET
112V
"*
<
o
o
<
o
0.
60
o
o
<
o
<
20
FREQUENCY (Hi)
BIAS
Fig.
SET CURRENT
()iA)
4 Gain bandwidth product
v.
Fig.
Typical frequency response
/set

15V
Supply voltages
Common mode
input voltage
Not greater than

supplies
Differential input voltage
Bias set current
Storage
Power
dissipation
Derate at
25V
10mA each pin
-55Cto +125C
800mWat25C
7mW/c C above 25 C
-40Cto +85 C
187
TAB1042
188
TAB1043
^^^ Semiconductors
TAB 1043
QUAD PROGRAMMABLE OPERATIONAL AMPLIFIER
The TAB1043
is
an advanced bipolar integrated

NON-INVERTING INPUT A [
circuit containing four separate operational amplifiers.

The amplifiers are programmed by current into the
appropriate bias pin. Pin 8 (Bias 2) programmes

amplifiers B, C and D and pin 16 (Bias 1) programmes
amplifier A.
For example, with a suitable choice of bias current,
the TAB1043 will perform in a manner similar to four
]N0N
INVERTING INPUT C
15
OUTPUT At
H Imverthgmvtc
posmvt SUPPLY [ 4
amplifiers of the 741 type, but with improved frequency

response and input characteristics.
The TAB1043 is especially suitable for use in active
filter
]HAS1
INVERTING INPUT A [
13
] OUTPUT C
OUTPUT B[
12
] NEGATIVE SUPPLY
MVERTtNG INPUT B[
11
NW-MVERTMG INPUT B[
] INVERTING INPUT
BIAS 2 [ 8
OUTPUT
]NON-INVEHTRW INPUT
DP16
applications.
Fig. 1
APPLICATIONS
FEATURES
Four Independent Op. Amps,
Pin connections
in
Active
One
Filters
Package
Oscillators
Internally Compensated
Wide Range of Supply Voltages from
1.5Vto 12V
Low
Voltage Amplifiers
No Latch-Up
Supply Voltages 1 .5V to 1 2V

Supply Current 40uA to 2mA
Operating Frequency Range 1 MHz
Programmable Over 1 00 :1 Current Range

Gain Bandwidth Product Up to 4MHz
Built-in Short Circuit Protection
Low Noise
Gain 95dB
Operating Temperature Range -40C to +85C
OUTPUT
A
INV
INPUT B
jo
NON-UK
INPUT D
to
to
OUTPUT
59
INV
NON-WV
MPUTC
INPUTC
119
OUTPUT
C
"j>
"<
o.
Fig.
AMPLIFIER B
AMPLIFIER C
I
AMPLIFIER
Circuit diagram
189
TAB1043
Tamb 25C
Operating
Operating
Operating
mode A Supply
mode B:Supply
mode C Supply
volts
volts
volts
12V
1
1
Bias set current 75nA)

2V Bias set current 1 nA \
.5V Bias set current 1 nA )
Operating
Characteristics
sum
mV
20
200
50
50
250
500
30
100
30
100
nA
nA
0.6
0.1
Supply current
0.5
1000 1700 2500
Conditions
Units
Input resistance
Typ. Max. Min. Typ. Max.
Input bias current
8 and
Mode
Min. Typ. Max. Min.
of currents into pins
0.5
220
100
200
RslOkfi
MO
400
74
95
66
90
66
90
dB
RL = 4kO(A)
RL = 100kO(B)
RL = 100kfi(C)
Input voltage range
10
10.5
10
10.5
1.5
1.7
RslOkfi
Common mode
70
110
82
dB
10.5
0.8
Large signal
volt gain
rejection ratio
Supply voltage rejection

Short
82
9
10.5
0.7
75
96
75
86
75
86
12
20
1.1
2.5
1.0
ratio
RL =
RL =
RL =
Tamb0C to70C
Gain = 20dB
mA
50
kHz
1.5
0.02
0.02
V///S
Input noise voltage
15
45
45
Input noise current
1.6
1.6
1.0
nV/VHz
pA/VHz
MHz
3.5
rate
100kfi(C)
RslOkfi
2.2
Slew
100kfi(B)
dB
50
circuit current
4kfi(A)
Gain
fo
fo
=
=
= 20dB
1kHz
1kHz
OPERATING NOTES
Bias set current
The amplifiers are programmed by the Iset current

into the BIAS pins to determine the frequency response,
slew rate and the value of supply current. The relationship is summarised as follows,
set current into pins 8 and 1 6
where
Iset
is
V SUPPLY
2V
the total
=

Power supply current
(each supply)
Iset x
Slew
Iset
rate
Iset
15
50kHz
25(iA
x 0.02 V/us
(Iset in
uA)
The open loop voltage gain is largely unaffected by

change in bias set current but tends to peak slightly at
10nA.
Since the voltage on either BIAS pin is approximately
0.65V more positive than the negative supply, a
resistor may be connected between the bias pin and
either 0V or the positive supply to set the current.
Thus, if the resistor is connected to 0V, the Iset current
is determined by
Iset
Vs - 0.65
where R is value of the 'set' resistor.

The output goes high if the non-inverting input is
taken lower than 1 V above the negative power supply.
190
BIAS SET CURRENT

Fig.
(pA)
3 Supply current (each supply)

v.
bias set current
TAB1043
1000
1
V SUPPLY
TA =
Ve
m too
+2S C
tiv
"
12
z
t
lu
I
<
>
o
o
<
:
<
D "'
FREQUENCY (Hz)
BIAS
Fig.
SET CURRENT (pA)
4 Gain bandwidth product
v.
Fig.
Typical frequency response
IsET

15V
Supply voltages
Common mode
input voltage
Not greater than

supplies
25V
10mA
Differential input voltage
Bias set current
Storage
Power
dissipation
-55Cto +125C
800mW
at 25
Derate at 7rrW/ C above 25

-40Cto +85
C
C
C
191
TAB1043
192
Package Outlines
193
194
4-32/5-33_
10-170/0210)
1-27(0O50m>
5-31/5-85 4-45/4-95
(0-209/0-230H0-175/0-195)
0-914/1-219
fiM)36|0-048)
CM 6
LEAD TO-71
4-19/4-70
1270/14-22
J
(0165/0185)
(0-500/0-560)
6-33/8-07
(0328/0318)
863/9
(0340/C
t
1
025/102
(0 01
LEAD TO-5
)/0040)
CM8
195
8-50/8-01
9195/9093
(0335/0-315)
(0362/0-358)
LEAD TO-5 WITH STANDOFF
CM8/S
(0-165/0-185)
12-7Q/14-22
(0-500/0-560)
10
196
LEAD TO-5
^ .,0-25/1-02
(0-010/0-040)
CM10
L-241/2 67(0095/0105)
NON ACCUMULATIVE
1981/20-57
(0-780/0-8IO)
I270MAX
SEATING PLANE
05
eg
1
5>
10500)
020/0
m w
u -LJ-L
MiH-
3-18/4-45
-L_J
(O
'
(OOOfa/OOi2i
__^
'
O 41/051
'
(0016/0020
NOMINAL CRS.
16
LEAD DILMON
DC16
(0045/0 0551
0-18
RAD
TYP.
(0007)
(O-l
P
/
t=I
SPOT IDENTIFIES
PIN
No.
CERAMIC CHIP CARRIER
GC18
197
r-i
ii
ii
ii
ii
617/668
(0-243/0-263)
V
7 62(0-30)
2-52/2 56 (0-099/0-101)
NON ACCUMULATIVE
LEAD CERAMIC DIL
14
i-i
n n n
r-i
DG14
fl
,
7
u
u uuuu u
6 17/6 68
(0243/02631
u
16
(0
010/0012)
(0017/0021)
7
62(030)
CRS NOM
2-52/2-56 (0 099/0101)
NON ACCUMULATIVE
16
198
LEAD CERAMIC DIL
DG16
7
(0-883/0-897)
249/2-59 (0O98/0102)
HON ACCUMULATIVE
18
LEAD CERAMIC DIL
DG18
nnnnr\r*f*nnnn
1
uuuuuuuuuuuu
13-06/13-87
(0-514/0-546)
31-45/32-61
(1-238/1-284)
Q-2S/0-30
(0010/0-012)
41 /O-S&H
(0-016/0-022)
15-24
2-49/2-59
(Q-098/0-1021
(C-6)
NON-ACCUMULATIVE
24
LEAD CERAMIC DIL
DG24
199
76(0 030)
n n n
DE
, IDENTIFIES
PIN No
^-^-'
%
l_l
1_I
I_l
o
o
o
l_l
1000
10-3941
MAX
71(0-280)
r
JL
(0015/0-024)
3
PITCHES
NON ACCUMULATIVE
249/259
(0098/0102)
LEAD PLASTIC DIL
.2
0-76
0P8
28
[0030
i-i
r-i
n n
ri
Ul
l_l
l_l
1_|
l_I
l_l
-IDENTIFIES PIN No
1_I
20 (0-787)
7-1(0 280)
MAX
9
!~*
O
m
o>
'
r^H
(&015/O024)
0-23/0-41
6
PITCHES
(0009/0-016)
NON ACCUMULATIVE
252/256
7-62 (0-3)
1
(0-099/0101)
14
200
LEAD PLASTIC DIL
DP14
'u
c
u u u uuuu
16
7
1
MAX
(0-280)
22 00/18-80
"
(0-866/ 0740)
o
9^
o
oz
in
p
O
Oz
jinnjinnrm
.1/M h\J-\)-\J-\J-\f-\ 7
L_l
I
1
"
|
38/0
'
61
'"(0-015/0-024)
23/0
(0
7
m
"
009/0016)
PITCHES
NON ACCUMULATIVE
2 52/2 56
(0-099/0101)
16
41
LEAD PLASTIC DIL
7-63(0-3)
CRS NOM
DP16
fcfmroi
(0-015/0-024)
8 PITCHES
NON ACCUMULATIVE
2-52/2-56
(0099/0-101)
18
LEAD PLASTIC DIL
DP18
201
202
Plessey
Semiconductors
World Wide
203
204
Sales offices
BELGIUM, NETHERLANDS, LUXEMBOURG
Plessey Semiconductors, Avenue de Tervuren 149, Box
Tel:
FRANCE
ITALY
UNITED KINGDOM
2,
Brussels
150, Belgium.
22100
331347
Plessey Semiconductors, 1641 Kaiser Avenue, Irvine, California 92714, USA.

Tel: 714 540 9979 Twx: 910 595 1930
Plessey Semiconductors, 2525 Oakton Street, Suite A-13, Arlington Heights,
Illinois 60005 USA. Tel: (312) 437 1860 Twx: 910 687 1484
Plessey Semiconductors, 89 Marcus Blvd., Hauppauge, N.Y., 1 1787 USA.
Tel: 516 273 3060 Twx: 96 1419
Plessey Semiconductors, 7094 Peachtree Industrial Blvd., Suite 295,
Norcross, GA 30071 USA. Tel: 404 447 6910 Twx: 70 7309
Plessey Semiconductors, 710 Lakeway, Suite 265, Sunnyvale, CA 94086 USA.
Tel:
SOUTH AFRICA
Tx:
Plessey Semiconductors, Z.A. de Courtaboeuf, rue de Quebec,

B.P. No. 142, 914 - Les Ulis Cedex.
Tel: (6) 446-23-45 Tx: 692858F
Plessey Trading SpA, Corso Garibaldi 70, 201 21 Milan. Tel: 3452081
Tx:
NORTH AMERICA
02 733 9730
408 245 9890
Plessey Semiconductors, 112 East High Street, Hicksville, Ohio 43526 USA.
Twx: 810 490 2551
Plessey South Africa Ltd., Forum Building, Struben Street, P.O. Box 2416,
Pretoria 0001, Transvaal. Tel: 3451 1 Tx: 53 0277
Plessey Semiconductors Ltd., Cheney Manor, Swindon, Wiltshire SN2 2QW.
Tel:
(0793) 36251 Tx: 449637
WEST GERMANY, AUSTRIA, SWITZERLAND

Plessey
Tel:
GmbH,
089 23 62
Altheimer Eck, 10, 8000

Tx:
Munchen
2,
West Germany.
0522197
205
Agents
ARGENTINA
Electroimpex SA, Guatemala 5991, (1425)Buenos Aires.

771 -3773/772-9573
Plessey Australia Pty Ltd., P.O. Box 2, Christina Road, Villawood,
New South Wales 2163. Tel: Sydney 72 0133 Tx: AA20384
Plessey Brazil, Rua Ferreira Viana 892, 04761 Sao Paulo, Brazil.
Tel:
AUSTRALIA
BRAZIL
Tel: 01
EASTERN EUROPE
GREECE
548 6570
Tx:
1 1
23328 ATETBR
219251
& Exportations, P.O. Box 1 81 Piraeus.

213835 LHGR
Semiconductors Ltd., 809 Raheja Centre, Nariman Point, Bombay 400 021
Tel: 233999 Tx: 011-5415 CITO IN
Semiconductors Ltd., Unity Buildings, JC. Road, Bangalore 560-001
Tel: 52072 & 578739
Semiconductors Ltd., 51 3, Ashoka Estate, 24, Barakhamba Road,
Nf w Delhi - 1 1 0001 Tel: 44879 Tx: 31 3369
Comes & Company Ltd., Maruzen Building, 2 Chome Nihonbachi,
Chuo-Ku, C.P.O. Box 1 58, Tokyo 1 00-91 Tel: 272 5771 Tx: 24874
Mammeas,
Representations
4172597
Tel:
INDIA
Tx:
Plessey pic, Vicarage Lane, llford, Essex, England. Tel: 01 478 3040
Tx: 231 66
Plessey Company Ltd., Hadjigianna Mexi 2, Athens. Tel: 21 724 3000
,
Tx:
JAPAN
HONG KONG
Comes & Company
Ltd.,
Osaka
1012
SPAIN
SWEDEN
TAIWAN
THAILAND
782
Plessey
Ind Co.
1
707
New
Tx:
Ltd.,
Yeoevido, P.O. Box 149, Seoul.
K25701
Zealand
Ltd.,
Ratanui, Henderson, Auckland 8. Tel:
64189
NZ2851
Electronics Trading Co. (Pte) Ltd., 66/66a Upper Serangoon Road,

Singapore 1 334. Tel: 285291 1 Tx: 22088
Plessey Singapore Private Ltd., 23 Kim Chuan Terrace,
Singapore 1 953. Paya Lebar P.O.Box 50, Singapore 91 54
Tel: 8051 1 1 Tx: RS 23844
JR Trading, Martires de Alcala 4-3, Madrid 8.
Tel: 248 12 18/248 38 82 Tx: 42701
Micronet AB, Kemistvaegen 10a, Box 509, S-183 25 Taby.
Tel: 8 756 02 55 Tx: 12800
Artistex International Inc., Express Trade Building 3rd Floor,
56 Nanking Road East, Section 4 Tapei 1 05, (P.O. Box 59253, Taipei
Taiwan, Republic of China. Tel: 7526330 Tx: 271 1 3 ARTISTEX
Plessey Thailand, Rama Mansion 47, Sukhumvit Soi 1 2, Bangkok 1 1
Tel:
TURKEY
525-4496
12-444241-6 Tx: 36590
Young
Tx:
SINGAPORE
Nishihonmachi, Nishi-Ku,
Products Ltd., Block E, 15/F Golden Bear Industrial Centre,

66-82 Chaiwan Kok Street, Tsuen Wan, NT., Hong Kong.
Tel:
NEW ZEALAND
Tx:
Chome
YES
Tel:
KOREA
550. Tel: 532
13-40
2526621 Tx: CHAVALIT TH2747

Ltd., Hatay Sokak
Turkelek Elektronik Co.
8,
Ankara.
Tel:
00)
18 94 83
Tx:42120TRKLTR
Turkelek Elektronik Co.
Istanbul. Tel:
206
43 40 46
Ltd.,
Kemeralti
CD Tophane
Ishani 406,
Tophane,
Distributors
BELGIUM
du Proges 52 B.3 Vooruitgangstraat, Bruxelles 1000

02 219 24 53 Tx: 23662
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Electronic Manufacturing Co., 3B Avonbeg Industrial Estate,
Long Mile Road, Dublin 12. Tel: 001 521242 Tx: 31125
Semiconductors Ltd., 809 Raheja Centre, Nariman Point, Bombay 400 021
Tel: 233999 Tx: 011-5415 CITO IN
Melchioni, Via P. Colletta 39, 20135 Milan. Tel: 5794 Tx: 320321
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Modelec B.V., Postbox 1 81 671 BD EDE,
Tel: 08380-362 62 Tx: 37053
Professional Electronics Ltd., P.O. Box 31-143, Auckland. Tel: 493 209
Tx: 21 084
Simac
Electronics, rue
BrusselTel:
FRANCE
IRELAND
INDIA
ITALY
NETHERLANDS
NEW ZEALAND
SCANDINAVIA
Denmark
Scansupply, Nannasgade 18-20, DK-2200 Copenhagen. Tel: 45

Tx:
Finland
83 50 90
19037
SF-00380 Helsinki 38.

1
90 55 00 02 Tx: 122214
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Tel: 02 64 1 1 50 Tx: 71 963
Tx: 1 1 1 81
Fertronic AB, Box 56, 1 61 Bromma. Tel: 08-25 26 1
Oy
Ferrado AB, P.O. Box 54, Valimontie
Tel:
Norway
Sweden
SWITZERLAND
Aumann &
Co. AG., Forrlibuckstrasse
50,
CH-8037
Zurich
/443300 Tx: 56228

Celdis-SDS 37-39 Loverock Road, Reading, Berks RG3 1 ED.
Tel: 0734 58221 1 /5851 71 Tx: 848370
Gothic Electronic Components, 380 Bath Road, Slough,
Berkshire SL1 6JE. Tel: 06286 4300 Tx: 847571
Quarndon Ltd., Slack Lane, Derby DE3 3ED. Tel: 0332 32651 Tx: 37163
Semiconductor Specialists (UK) Ltd., Carroll House, 159 High Street,
West Drayton, Middlesex UB7 7QN. Tel: 08954 45522 Tx: 21958
Nordelektronik GmbH KG, Carl-Zeiss-Str. 6, 2085 Quickborn.
Tel: 04106/74174 Tx: 02 14299
Tel: 01
UNITED KINGDOM
WEST GERMANY
Halbleiter-Spezialvertrieb, Carroll
&
Co.
GmbH,
Vilbeler Landstr.41
06194/3805-6 Tx: 0418054

Astronic GmbH & Co. KG, Winzererstrasse 47D, 8000 Munchen 40.
Tel: 089/309031 Tx: 05 216 187
Neumuller GmbH, Eschenstrasse 2, 8021 Taufkirchen b. Munchen.
Tel: 089/61181 Tx: 05 221 06
Micronetics GmbH, Weil der Stadter Str. 55a, 7253 Renningen 1
Tel: 071 59/601 9 Tx: 07-24708
6000 Frankfurt/M.60.
Tel:
207
'yv/bwvw]
PLESSEY
Semiconductors <$>
Plessey Semiconductors Limited,
Cheney Manor, Swindon,

Wiltshire.
SN2 2QW.
United Kingdom.
Tel:{0793) 36251 Telex:
449637

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LINEAR

Designed and produced by Peter Wigens Consultants

This publication is issued to provide outline information only and (unless

The name Plessey and the Plessey logo are

The Plessey Company pic.

High slew rate operational amplifier

Quad programmable operational

Ultra low noise preamplifiers

PHASE LOCKED LOOP CIRCUITS

locked loop circuits for

LIMITING WIDEBAND AMPLIFIERS

250MHz true log IF amplifier

MATCHED TRANSISTOR AND ARRAYS

Dual NPN transistors

Double balanced modulators

log IF strip amplifier

Gain controlled preamplifier

POWER CONTROL CIRCUITS

140MHz wideband log amplifier

log IF strip amplifier

250MHz true log IF amplifier

High slew rate operational amplifier

Low noise wideband amplifier

low noise preamplifiers

with external gain control

log IF strip amplifier

Very high performance transistor array

for integrated circuits of Assessed Quality (BSI Certificate

21 QC System requirements for Industry (Equivalent to

style required, according to the following table:

Ceramic Dual-in-Line (metal

Plessey Semiconductors Limited

you are invited to contact your nearest Plessey Semiconductors Sales

DELIVERED PRODUCT QUALITY

product and to achieve this end all devices

we are able to guarantee the following Acceptable Quality Level

is considerably better than this, the population

following Screening Procedures are available from Plessey Semiconductors

Screening Procedure for Standard

'Design and test times given are

depend on the complexity

transistors with close parameter matching and high ft. The

Good Frequency Response>400MHz

Very High Frequencies

ABSOLUTE MAXIMUM RATINGS

apply to individual transistors.

The absolute maximum ratings are limiting values above

Emitter base leakage current

Emitter base leakage current

Collector isolation breakdown

Forward current transfer

Collector isolation capacitance

Temperature coefficient of AVbe

2 Output capacitance (Cot,)

3 Typical variation of hp with collector current

4 fjv. collector curent(tj = fhfe .t= 100MHz

Close Vbe Matching

Good Frequency Response

QUICK REFERENCE DATA

ABSOLUTE MAXIMUM RATINGS

No one transistor may dissipate more than 75% of tne

Chip-to-case thermal resistance

Collector emitter breakdown

Collector isolation breakdown