Mavenvlsi.

org
MODULE I
Introduction to VLSI
VLSI Design Flow 'BASIC Vs FPGA
RTL Design Methodologies
Introduction to ASIC verification methodologies VLSI Design Flow Steps Demo
MODULE 2
Basic and Advanced Digital Design
Introduction to Digital Electronics .Arithmetic. Data processing Circuits Universal Logic
Elements Combinational & Sequential Circuits - Design and Analysis 'Shift Registers and
Counters Memories and PLD Finite State Machine Microcontroller Design
o

Fundamental Of Digital Design

Combinational Circuit Design

Sequential Circuit Design

Clock Dividers

Synchronizer Failure and Meta stability Estimation

Fifo & Pipeline

PLD + CPLD

Skew, Jitters

Delay Analysis

Design Examples and Case Studies

MODULE 3
Introduction to Linux
Components of Unix System
Directory Structure

 Utilities and Commands

Vi Editor

MODULE 4
CMOS Fundamentals
Non Ideal characteristics 13.11- vs FET
CMOS Characteristics
CMOS circuit design
Transistor sizing
Layout and Stick Diagrams
CMOS Processing Steps
Fabrication
CMOS Technology -Current Trends
MODULE 5
FPGA Architecture
Introduction to PLD
Xilinx CPLD - Xc9500
Xilinx FPGA - XC 4000E
Xilinx Spartan 3
ACTEL Architecture
MODULE 6
Verilog HDL RTL Coding and Synthesis
Introduction to Verilog HDL
Applications of Verilog HDL
Verilog HDL language concepts

Verilog language basics and constructs

Abstraction levels
Data Types
Type concept
Nets and registers
Non hardware equivalent variables
Arrays
Verilog Operators
Logical operators
Bitwise and Reduction operators
Concatenation and conditional
Relational and arithmetic
Shift and Equality operators
Operators precedence
Assignments
Types of assignments
Continuous assignments
Timing references Procedures
Blocking and Non-Blocking assignments
Execution branching
Tasks and Functions
Advanced Verilog for Verification
System Tasks
Internal variable monitoring
Compiler directives

 File input and output

Finite State Machine
Basic FSM structure
Moore Vs Mealy
Common FSM coding styles
Registered outputs
Synthesis Coding Style :
Registers in Verilog
Unwanted latches
Operator synthesis
RTL Coding Style
MODULE 7
Mini Project RTL Coding and Synthesis
Project Specification Analysis
Understanding the architecture
Module level implementation and verification
Building the top level module
Implementing the design onto the FPGA board

MODULE 8
Industry Standard Project
Design specification analysis
Creating the design architecture
Partitioning the design
RTL coding in Verilog/VHDL

 RTL functional verification

RTL Synthesis
Place & Route the netlist
Timing Simulation
Implementing design onto the FPGA
Verifying design on FPGA Board
SILICON MENTORS.ORG

Module 1:Introduction to vlsi design

Evolution of vlsi system
Application of VLSI system
ASIC Design flow
Role of HDL
Module 2:Introduction to Verilog
Need of Verilog
Abstraction levels
Concurrency
Digital circuit designing with Verilog
Need of verification of HDL design
Simulation and Synthesis
Testbench
4-state logic

Module 3:Verilog Syntax and Semantics

Key word s
Identifiers
White spaces
Comments
Numbers representation
Data Types
Scalar and Vectors
Operators
Delays
Module 4:Gate Level Modeling
Introduction to gate Level modeling
How to construct a module
Design of gate primitives
Design of Half Adder
Design of Multiplexer at Gate level
Modeling of tri-state gate
Design of basic digital design at gate level
Module 5:Data flow modeling
Introduction to Data flow modeling
Continuous assignment structures
Assignment statements and their use

 Designing with testbenches

Digital circuit design using continuous assignments
Module 6:Behavioral Level modeling-I
Introduction to behavioral modeling
Procedural blocks
Design with multiple always blocks
Blocking and Non-blocking assignments
if-else construct Case statement
Introduction to loops
Designing with for, repeat, while and forever loop
Digital circuit designing at behavioral level
Module 7:Behavioral Level modeling-II
Advanced circuit designing at behavioral level
System Tasks
Tasks and Functions
Introduction to FSM
FSM circuit designing
Module 8:Memory Designing
Introduction to memory designing
DualAddress ROM design
Single Address RAM design
Designing of FIFO