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ZedBoard Example
April 2013
Revision history
Revision
Date
Comments
0.1
January 2013
First draft
1.0
January 2013
First release
1.1
February 2013
1.2
February 2013
Linguistic revision
1.3
April 2013
Table of Contents
Introduction .................................................................................................................... 5
List of Figures
1 Introduction
The ZedBoard is a low-cost platform which has some very interesting features for an entry-level
development board. Adding the Radio420S to the ZedBoard creates a highly versatile software-defined
radio platform. Software may be written either for Zynq programmable logic or for the two on-chip ARM
processors.
This guide demonstrates how to generate and receive signals within the Zynq programmable logic. Once
you have completed this guide, you will be able to compile a bitstream for the ZedBoard, capture received
data using Xilinxs ChipScope Analyzer, use Xilinx SDK for application development, and configure the
Radio420S for carrier frequency between 300 MHz and 3 GHz.
2 Radio420S Example
This example illustrates how to interface the ZedBoard with the Radio420S FMC.
The Xilinxs PlanAhead project contains a Xilinx Platform Studio project, custom logic to generate DAC
data, IQ select signals and a ChipScope instance.
The Xilinx Platform Studio contains the Radio420 core to control and interface with the Radio420S FMC, a
ChipScope wrapper core to demultiplex ADC and DAC IQ data and an axi_gpio core to set the DAC DDS
frequency.
In Xilinxs PlanAhead, the Radio420 design clock is used to generate DDS data every two clock cycles. The
cosine outputs are used for DAC I data and sine outputs for DAC Q data. The custom logic connected to
the ClkEn of the DDS generator and the multiplexer are used to multiplex DDS outputs on the DAC data
input port.
The ChipScope instance is connected to the outputs of the ChipScope wrapper to monitor ADC and DAC IQ
data. The UserClk operates at half the rate of the Radio420 design clock because the data is no longer
multiplexed. ChipScope has been instantiated by opening the synthesized design in PlanAhead and by
connecting the ChipScope trigger port with the ChipScope wrapper output port nets.
Xilinx PlanAhead
Xilinx Platform Studio
Chipscope
Wrapper
Radio420 core
ADC I
ADC Q
DAC I
DAC Q
UserClk
Chipscope
dds_freqs
(axi_gpio)
DesignClk
ADC
DDS
Generator
Data
IQSel
Data
Clk
DAC
Data
z-1
IQSel
Sine
Cosine
ClkEn
z-1
2.1 Requirements
The following hardware and software requirements must be met to perform the example.
2.1.1 Hardware
1 ZedBoard
1 ZedBoard power supply
1 Nutaqs Radio420S
1 USB-to-micro USB cable (2x optional)
1 spectrum analyzer (optional)
1 MMCX -MMCX cable or a set of antennas (for RX loopback).
2.1.2 Software
Xilinx 14.2
2.2 Setup
To set up the example:
1.
On the ZedBoard, set the value of the Vadj power supply to 2.5 V.
To do so, set the Vadj jumpers according the picture below.
2.
Set the MIO jumpers of the ZedBoard according the picture below.
3.
Connect the Radio420S to the FMC LPC connector of the ZedBoard as shown below.
4.
5.
Connect the USB JTAG port of the ZedBoard (beside the power connector) to the PC using a USB
cable.
6.
Connect the USB serial console of the ZedBoard to the PC using a USB cable (optional).
7.
Connect the antennas or the MMCX-MMCX cable to the RX and TX connectors to create the RF
loopback.
IMPORTANT
2.3 Procedure
To perform the example:
1.
2.
3.
4.
In the Workspace Launcher dialog box, in the Workspace list select the
[]\ZedBoard_radio420s.sdk\SDK\SDK_Export folder as a workspace and click OK.
5.
To configure the FPGA with the Radio420s bitstream, click on Xilinx Tools in the XSDK toolbar and
select Program FPGA. The following window will appear.
Make sure the selected bitstream is the right one and click on Program. The FPGA will be configured.
6.
7.
Select Import from an existing workspace and import all the available projects.
8.
Click the Debug tab and click the Debug Configuration button.
9.
10. Still in the Debug Configuration window, select the STDIO Connection tab.
The Connect STDIO to Console checkbox must be checked. Select the COM port connected to your
Zedboard and enter 115200 as the BAUD Rate. To verify which COM to select, open the device
manager and look for the Cypress Serial entry in the Ports list.
11. Click the Debug Configuration button again to load the program in the ARM processor memory.
To see the example results, close Xilinx SDK and open the Chipscope Analyzer.
2.
3.
4.
Start the data capture by clicking the Play button in Xilinx ChipScope Analyzer and you should obtain
the following results.
This chapter describes how to generate a bitstream for the Radio420S. The bitstream generated is the
default bitstream available in the Radio420S ZedBoard reference design. Follow this step-by-step
procedure using your own modifications to generate your bitstream.
1.
2.
3.
4.
5.
6.
7.