BTA08-600BW3G,

BTA08-800BW3G
Triacs

Silicon Bidirectional Thyristors

Designed for high performance full-wave ac control applications
where high noise immunity and high commutating di/dt are required.

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Features

TRIACS
8 AMPERES RMS
600 thru 800 VOLTS

Blocking Voltage to 800 V

On-State Current Rating of 8 A RMS at 80C
Uniform Gate Trigger Currents in Three Quadrants
High Immunity to dV/dt 2000 V/ms minimum at 125C
Minimizes Snubber Networks for Protection
Industry Standard TO-220AB Package
High Commutating dI/dt 1.5 A/ms minimum at 125C
Internally Isolated (2500 VRMS)
These Devices are PbFree and are RoHS Compliant*

MT2

MT1
G

MARKING
DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

Rating

Symbol

Peak Repetitive OffState Voltage (Note 1)

(TJ = 40 to 125C, Sine Wave,
50 to 60 Hz, Gate Open)
BTA08600BW3G
BTA08800BW3G

VDRM,
VRRM

On-State RMS Current

(Full Cycle Sine Wave, 60 Hz, TC = 80C)

IT(RMS)

8.0

ITSM

90

I2t

36

A2sec

VDSM/
VRSM

VDSM/VRSM
+100

Peak Gate Current (TJ = 125C, t = 20ms)

IGM

4.0

Peak Gate Power

(Pulse Width 1.0 ms, TC = 80C)

PGM

20

Average Gate Power (TJ = 125C)

Peak Non-Repetitive Surge Current

(One Full Cycle Sine Wave, 60 Hz,
TC = 25C)
Circuit Fusing Consideration (t = 8.3 ms)
NonRepetitive Surge Peak OffState
Voltage (TJ = 25C, t = 10ms)

Value

Unit
V
1

600
800

PG(AV)

1.0

Operating Junction Temperature Range

TJ

40 to +125

Storage Temperature Range

Tstg

40 to +150

RMS Isolation Voltage

(t = 300 ms, R.H. 30%, TA = 25C)

Viso

2500

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2012

September, 2012 Rev. 1

x
A
Y
WW
G

BTA08xBWG
AYWW

TO220AB
CASE 221A
STYLE 12

= 6 or 8
= Assembly Location (Optional)*
= Year
= Work Week
= PbFree Package

* The Assembly Location code (A) is optional. In

cases where the Assembly Location is stamped
on the package the assembly code may be blank.

PIN ASSIGNMENT
1

Main Terminal 1

Main Terminal 2

Gate

No Connection

ORDERING INFORMATION
Device

Package

Shipping

BTA08600BW3G

TO220AB
(PbFree)

50 Units / Rail

BTA08800BW3G

TO220AB
(PbFree)

50 Units / Rail

Publication Order Number:

BTA08600BW3/D

BTA08600BW3G, BTA08800BW3G
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,

JunctiontoCase (AC)
JunctiontoAmbient

Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 seconds

Symbol

Value

Unit

RqJC
RqJA

2.5
63

C/W

TL

260

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted; Electricals apply in both directions)
Symbol

Min

Typ

Max

0.005
2.0

1.55

2.5
2.5
2.5

50
50
50

60

70
90
70

0.5
0.5
0.5

1.7
1.1
1.1

0.2
0.2
0.2

(dI/dt)c

1.5

A/ms

Critical Rate of Rise of OnState Current

(TJ = 125C, f = 120 Hz, IG = 2 x IGT, tr 100 ns)

dI/dt

50

A/ms

Critical Rate of Rise of Off-State Voltage

(VD = 0.66 x VDRM, Exponential Waveform, Gate Open, TJ = 125C)

dV/dt

2000

V/ms

Characteristic

Unit

OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)

TJ = 25C
TJ = 125C

IDRM,
IRRM

mA

ON CHARACTERISTICS
Peak On-State Voltage (Note 2)
(ITM = 11 A Peak)

VTM

Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 30 W)

MT2(+), G(+)
MT2(+), G()
MT2(), G()

IGT

Holding Current
(VD = 12 V, Gate Open, Initiating Current = 100 mA)

IH

Latching Current (VD = 12 V, IG = 60 mA)

MT2(+), G(+)
MT2(+), G()
MT2(), G()

IL

Gate Trigger Voltage (VD = 12 V, RL = 30 W)

MT2(+), G(+)
MT2(+), G()
MT2(), G()

VGT

Gate NonTrigger Voltage (TJ = 125C)

MT2(+), G(+)
MT2(+), G()
MT2(), G()

VGD

V
mA

mA
mA

DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current, See Figure 10.
(Gate Open, TJ = 125C, No Snubber)

2. Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.

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2

BTA08600BW3G, BTA08800BW3G
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current

Symbol

Parameter

VTM

VDRM

Peak Repetitive Forward Off State Voltage

IDRM

Peak Forward Blocking Current

VRRM

Peak Repetitive Reverse Off State Voltage

IRRM

Peak Reverse Blocking Current

VTM

Maximum On State Voltage

IH

Holding Current

on state
IRRM at VRRM

IH
Quadrant 3
MainTerminal 2

IH

off state

VTM

Quadrant Definitions for a Triac

MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2

Quadrant II

(+) MT2

() IGT
GATE

Quadrant I

(+) IGT
GATE
MT1

MT1

REF

REF
IGT

+ IGT
() MT2

Quadrant III

() MT2

Quadrant IV

(+) IGT
GATE

() IGT
GATE

MT1

MT1

REF

REF

MT2 NEGATIVE
(Negative Half Cycle)

All polarities are referenced to MT1.

With inphase signals (using standard AC lines) quadrants I and III are used.

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3

Quadrant 1
MainTerminal 2 +

+ Voltage
IDRM at VDRM

BTA08600BW3G, BTA08800BW3G
125

12

120

PAV, AVERAGE POWER (W)

TC, CASE TEMPERATURE (C)

DC
= 120, 90, 60, 30
115
= 180
110
DC
105
100

3
4
5
6
7
IT(RMS), RMS ON-STATE CURRENT (A)

10
180
8

120

6
60

4
90
= 30

2
0

100
Typical @
TJ = 40C

Typical @ TJ = 25C
Typical @ TJ = 125C

10

0.1

0.01

0.1

10
100
t, TIME (ms)

1000

1 104

Figure 4. Thermal Response

55
1

IH, HOLDING CURRENT (mA)

IT, INSTANTANEOUS ONSTATE CURRENT (A)

Figure 2. On-State Power Dissipation

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

Figure 1. RMS Current Derating

2
3
4
5
6
IT(RMS), ON-STATE CURRENT (A)

Typical @ TJ = 125C
Typical @ TJ = 25C
Typical @ TJ = 40C

0.1

0.5

1.5

2.5

3.5

4.5

45
35

MT2 POSITIVE

25
15

MT2 NEGATIVE

5
40 25 10

20

35

50

65

80

95 110 125

VT, INSTANTANEOUS ON-STATE VOLTAGE (V)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. On-State Characteristics

Figure 5. Holding Current Variation

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4

BTA08600BW3G, BTA08800BW3G
2.00

100

10

GATE TRIGGER VOLTAGE (V)

IGT, GATE TRIGGER CURRENT (mA)

VD = 12 V
RL = 30 W

Q1

Q2
Q3

1
40 25 10 5

20

35

50

65

80

95

VD = 12 V
RL = 30 W

1.80
1.60

Q1

1.40
1.20
1.00
0.80

Q3

0.60

Q2

0.40
40 25 10

110 125

TJ, JUNCTION TEMPERATURE (C)

35

50

65

80

95 110 125

TJ, JUNCTION TEMPERATURE (C)

120

5000

4K

LATCHING CURRENT (mA)

VD = 800 Vpk
TJ = 125C

3K

2K

1K

10

100
1000
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS)

VD = 12 V
RL = 30 W

100
80

Q1

60
Q3
40
Q2

20
0
40 25 10 5

10000

Figure 9. Critical Rate of Rise of Off-State Voltage

(Exponential Waveform)

35

50

65

80

95

110 125

Figure 10. Latching Current Variation

LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC

CHARGE

20

TJ, TEMPERATURE (C)

1N4007
MEASURE
I

TRIGGER

CHARGE
CONTROL

NONPOLAR
CL

TRIGGER CONTROL

dv/dt , CRITICAL RATE OF RISE OF OFFSTATE VOLTAGE (V/ s)

20

Figure 7. Gate Trigger Voltage Variation

Figure 6. Gate Trigger Current Variation

200 V

MT2
1N914 51 W

MT1
G

Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.

Figure 8. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c

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5

BTA08600BW3G, BTA08800BW3G
PACKAGE DIMENSIONS
TO220
CASE 221A07
ISSUE AA
T
B

SEATING
PLANE

A
U

1 2 3

H
K

L
V

G
D
N

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.014
0.022
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080

STYLE 12:
PIN 1.
2.
3.
4.

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.36
0.55
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04

MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED

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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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BTA08600BW3/D