2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), October 3-5, 2010, Penang, Malaysia

Simulations of Variable I-Layer Thickness

Effects on Silicon PIN Diode I-V Characteristics
Warsuzarina Mat Jubadi 1, Siti Norafzaniza Mohammad Noor 2
Department of Electronic Engineering, Faculty of Electrical and Electronic Engineering,
Universiti Tun Hussein Onn Malaysia (UTHM), Johor, Malaysia
1
suzarina@uthm.edu.my, 2afzaniza_mohammadnoor@yahoo.com
Abstract PIN Diode gains its name from the idealized
intrinsically doped, I-layer, sandwiched between a P-type
and N-type layer. The N-layer of PIN diode was doped with
Arsenic and the P-layer doped with Boron.
The
performance of the PIN diode primarily depends on the
chips geometry and the nature of the semiconductor
material, particularly in the I-layer. This paper presents a
simulation of four I-layer thickness (5m, 20m, 30m and
50m) effects on the silicon PIN diode I-V characteristics
carried out by using Sentaurus Technology Computer
Aided Design (TCAD). The major goals of the simulation
work are to study the I-layer thickness (d) effects on diode IV characteristics and to implement PIN diode fabrication
process flow into a commercially available process
environment. The important parameters of PIN diode were
analyzed to study the effect of PIN diode I-V characteristics.
KeywordsPIN diode; I- layer; thickness; Sentaurus TCAD
I.

doping profiles are analyzed using Sentaurus TCAD tools

discussed in the next topic
II.

PIN DIODE STRUCTURE

PIN diode is a silicon semiconductor consisting of a

layer of intrinsic (high resistivity) material of finite area
and thickness which is contained between a P-type and
N-type layer. When the diode is forward biased, charge
is injected into the intrinsic or I-layer [3]. This charge
consists of holes and electrons which have a finite
lifetime before recombination. The PIN diode structure is
shown in Fig.1.

INTRODUCTION

A PIN diode is a silicon (Si) semiconductor device

formed of a high resistivity intrinsic I-layer which
sandwiched between a P-type and N-type layer.
Generally, the PIN diode finds widely used in RF, UHF
and microwave circuits as it acts as a current controlled
resistor at these frequencies. PIN diodes are also used in
power electronics as their central layer can withstand
high voltages [1]. They are extensively implemented in
electronic switching applications as radio frequency
switches. The resistance value of the PIN diode is
determined only by the forward biased dc current. The
resistivity of the I-layer varies according to the quantity
of electrons and positive holes, and these changes the
high frequency series resistance [2].
Previous researches in [4-7] varies from the PIN diode
structure design, PIN geometrics due to I-layer, low
frequency model, large signal model and switching speed
model. A a result, in this paper the authors concentrate on
the geometry of PIN diode using different I-layer and its
effects toward the I-V characteristics PIN diode. The 2D
stucture of PIN diode is simulated with different
thickness (d) of I-layer and I-V characteristics and the
This work is supported by the Ministry of Higher Education, Malaysia
(MOHE) under the Fundamental Research Grant Scheme (FRGS);
vote number 0559.

978-1-4244-7647-3/10/$26.00 2010 IEEE

428

Figure 1. PINDiode Structure

By varying the I-layer width and diode area its

possible to construct PIN diode of different geometrics to
result in the same Shunt Resistance, RS and Total
Capacitance, CT characteric. These devices may have
similar small signal characteristics. However, the thicker
I-region diode would have a higher bulk or RF
breakdown voltage and better distortion properties. On
the other hand, the thinner device would have faster
switching speed. The theory of I-region thickness effects
has encouraged the study to be carried out.
III.

METHODOLOGY

A. Design and Simulation Tools

In this project, Sentaurus TCAD tool is used to design
the PIN diode structure and simulate the I-V
characterictics. Sentaurus TCAD is one of among TCAD
tools to design the semiconductor models. TCAD itself
refers by using computer simulations to develop and
optimize semiconductor processing technologies and
devices [8]. Fig.2 illustrates the design flow to create a
PIN diode by using Synopsis Sentaurus TCAD tools.

In the SSE tools, mesh is needed to generate meshes

that are suitable for semiconductor device simulation.
Meshing must be created for a device structure by
defining the reference window for the structure.
The length of each of PIN diode structure is set to be
90m while the thickness for the P-type and N-type layer
is 10m. These devices consists of a silicon
semiconductor substrate with boron doping of 1e+17cm3
on P-type layer and heavily doped of arsenic with
1e+19cm3 on N-type layer which a thin layer oxide of
thickness Tox=0.3m is grown. A contact for PIN diode
called the anode and cathode are formed on top and
bottom of the PIN diode structure.
IV.

Figure 2. Process Simulation Flow of PIN diode Design [8]

The setup of Sentaurus Workbench (SWB) project

supports PIN diode device creation and simulation of PIN
structure using different I-layer thickness. After the
structure is created, the I-V curve simulations are
performed. The family tree structure is created in the
SWB interface which involved in the project
development and simulations. The complete family tree
consists of SSE, Sentaurus Device (SDE) and Techplot.
The I-layer thickness, d is defined as the variable
parameter in the design structure.
B. Device Structure
Sentaurus Structure Editor (SSE) is a tool sequence for
this project which is used to build the 2D or 3D device
structures. SSE can emulate PIN Diode process step and
geometry editing operations. The device structure of PIN
diode created in SSE tools is shown in Fig. 3.
Anode

Doping
concentration
(1e17)

P-type layer
(Boron Doped)

I layer (Silicon)

N-type layer (Arsenic Doped)

Doping concentration (1e19)

10m

I layer
Thickness
(d)

10m

Cathode

Figure 3. PIN Diode Structure designed in SSE. The thickness of P-,

I- and N-layer and the doping profile are defined in the boundry
command file (bnd.cmd) created in SSE

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SIMULATION RESULTS

A. Doping Profiles and I-V Characteristics

Device simulations model is a semiconductor device
operation on a microscopic level and also done to extract
the electrical characteristics such as current-voltage
relations (I-V curve).
In the analysis, four (4) different I-layer thickness
have been chosen in the device structure which are 5m,
20m, 30m and 50m. The simulations for both doping
profiles and the I-V characteristics were carried out using
tdr.dat file and Sentaurus Inspect. Fig.4 illustrates the
simulation of a typical device structure with I-layer
thickness of 5 m. The simulation of device structure for
I-layer thickness of 20m, 30m and 50m are illustrated
in Fig.5, Fig.6 and Fig.7 respectively.

B. 5m I-layer Thickness.

d=5m

Figure 4. Simulation of Doping Concentration and I-V Characteristics of PIN Diode Device Structure with
d=5 m. The structure is doped with Arsenic (1e19) at N-layer and Boron (1e17) at the P-layer. For d=5 m,
the current collected for the device structure is 1 x 10-5 A.

C. 20 m I-layer Thickness.

d=20m

Figure 5. Simulation of Doping Concentration and I-V Characteristics of PIN Diode Device Structure with
d=20 m. The current collected using the device structure is 3 x 10-6 A.

D. 30 m I-layer Thickness.

d=30m

Figure 6. Simulation of Doping Concentration and I-V Characteristics of PIN Diode Device Structure with
d=30 m. Based on the doping concentration chart, the bottom part of the device (N-layer) is heavily doped
with Arsenic as can be seen from the colour concentration itself. The forward current simulated in the device
structure at d=30 m is 1.5 x 10-6 A.

430

E. 50 m I-layer Thickness.

d=50m

Figure 7. Simulation of Doping Concentration and I-V Characteristics of PIN Diode Device Structure with
d=50 m. The total thickness for the PIN diode structure is 70m. The forward current simulated using
Sentaurus Inspect found that the current is 1.5 x 10 -7A at forward voltage, V = 10V.

V.

ANALYSIS AND DISCUSSION

According to (2), the minority diffusion length, Ln and

Lp can be calculated to obtain the diode current and the
minority carrier lifetime, n = p = 10-17sec. The electron
diffusion constant, Dn is set to be 35cm2/s and hole
diffusion constant, Dp = 12cm2/s.

In order to check the reliability of the results, the

simulation analysis was repeated for four times. Fig.8
illustrates the I-V curve comparisons of each of the Ilayer thickness visualized using Techplot and Sentaurus
Inspect. The I-V curve is compiled together as it is easier
to view the trend of current versus the I-layer thicknesses.

Dn n and L p =

Ln =

D p p

(2)

The built in voltage, Vbi can be determined in (3) [2]:

Vbi =

kBT N a N d
ln
2
e
ni

(3)

Besides, eq. (4) is used to determine the depletion, W in

the doped regions. x i is the thickness of I-layer and

d=5m

Va = 5V , V i = 0.3V
d=20m

d=30m

W = x' n + x' p + x i

d=50m

2
=
e

Figure 8. Combinations of I-V Performance for

different I-layer Thicknesses.

(V bi + V a + V i ) + x i

(4)

Eq. (5) is applied to determine the generationrecombination current, IGR, while the prefactors current,
Io found according to (6) [9]. The area of PIN diode is
referred as A.

The calculation for PIN diode current is done

according to its minority charge density, the I-layer
thickness, the minority diffusion length and the
generation- recombination current. The minority charge
density for P and N layer can be determined according to
(1) [9]. The value for Na = 1017cm-3, Nd = 1019cm-3 and
ni= 1.5 x 1010cm-3 (constant for Si).

n
n2
n p = i and p n = i
Na
Na

Na + Nd

N .N
a d

I GR =

eAWn i
2

D p Pn D n n p
+
I O = eA
Lp
Ln

(1)

431

(5)

(6)

Therefore, the current, I for different I-layer thickness

can be determined using (7):

eV
I = I 0 exp
kBT

eV
+ I 0GR exp

2kBT

REFERENCES
[1] Bill
Doherty,
Micronotes:
PIN
Diode
Fundamentals. Microsemi Watertown, MicroNote,
Series 701, 1998.
[2] S.M.Sze, Physics of Semiconductor Devices, 3rd
ed., John Wiley & Sons, Inc. 2007.
[3] Skyworks Solutions, Inc., Design With PIN
Diodes, Application Note, 200312 Rev. A, July
21, 2005.
[4] Chung C. Chang, Ching H. Lee, Study and
Fabrication of PIN Photodiode by Using
ZnSe/PS/Si Structure,IEEE
Tran.Electron
Devices, Vol. 47, No. 1, pp 50-54, Jan 2000.
[5] K.Asano, T.Funaki, Y.Sugawara and T.Hikihara,
Simple circuit model of SiC pin diode composed
by using experimental electrical characteristics,
IEICE Electron. Express, Vol. 2, No. 13, pp.392398, 2005.
[6] D.Surls and M.Crawford, Individual and Parallel
Behavior
of High Current Density, High-Voltage
4th- Silicon Carbide P-I-N Diodes, IEEE Tran.
Magnetics, Vol. 41, No. 1, pp 330-333,
2005.
[7] K. W. Kobayashi, et. al., A Novel Baseband-1.5
GHz Monolithic HBT Variable Gain Amplifier
with Pin Diode Gain Control, IEEE 1995
Microwave and Millimeter-Wave Monolithic
Circuits Symposium Digest, pp. 181184.
[8] Sentaurus TCAD Basic Training, Synopsys Inc
manual, 2006.
[9] Jasprit Singh. Semiconductor Devices Basic
Principles. John Wiley & Sons, Inc. 2002.
[10] Y. Hussein, J. Spencer, S. El-Ghazaly, and S.
Goodnick, Efficient Modeling of PIN Diode
Switches
Employing
Time-Domain
Electromagnetic-Physics-Based
Simulators,
Presented at International Microwave Symposium,
June 2005.

(7)

The comparisons of different I-layer thickness

current are listed in Table 1. Using all the mathematical
relations above, it shows that the thickness of I-layer
region is inversely proportional to the forward current
performance.
TABLE 1 CURRENT FOR DIFFERENT I LAYER THICKNESS
COLLECTED AT FORWARD VOLTAGE, V = 10 V

I-layer
Thickness
(m)
5

Current (A)
from
simulation
1.0x10-5

Current (A)
from
calculation
5.0x10-5

20

3.0x10-6

6.87x10-6

30

1.5x10-6

4.0x10-6

50

1.5x10-7

2.6x10-7

ACKNOWLEDGMENT
The authors would also like to thank University Tun
Hussein Onn Malaysia for supporting the technical
facilities for this project and Mr W.S. Wong from
Trans-Dist Engineering Sdn. Bhd for useful
discussions.

CONCLUSION

In this paper, the I-layer thickness effects of the Si

PIN
diode on its I-V caharacteristics has been
successfully simulated and verified. The PIN diode
structure is designed using the boundary file and
doping profile before combined together in SSE. In
order to perform the electrical characteristics, the
device structure then compiled with SDE and Inspect
tools in the Sentaurus Workbench. The forward
currents collected for different I-layer thickness are
compared for both simulations and calculations. It is
proved that the thinner the thickness of I-layer, the
higher the forward current flows in the device. Hence,
the current performance is inversely proportional with
the I-layer thickness.

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