IMPLEMENTATION OF

THE ONBOARD ADC ON

SPARTAN 3E FPGA
PLATFORM

By :
Shobhit Chaurasia
Roll No:11010179
Department of
Computer Science
and Engineering,
IIT Guwahati
Duration:
May-June 2012

UNDER THE GUIDANCE OF: Dr. Praveen Kumar,

Assistant Professor, Department Of Electronics
and Electrical Engineering, IIT Guwahati

ACKNOWLEDGEMENT
I would like to avail this opportunity to express me indebtedness to my guide Dr.
Praveen Kumar, Assistant Professor, Department of Electronics and Electrical
Engineering, Indian Institute of Technology, Guwahati, for his valuable guidance,
constant encouragement and kind help at various stages for the successful completion
of this project.
I am also grateful to Dr. Gaurav Trivedi, Assistant Professor, Department of Electronics
and Electrical Engineering, for providing valuable assistance and insight during the
implementation and experimental process.
I would like to express my sincere gratitude to Reena Maam and Babita Maam,
Research Scholars, Department of Electronics and Electrical Engineering for their
constant and untiring efforts to make this project successful. I am also thankful to Mr.
Sidananda Sonowal, Junior Technical Superintendent, Department of Electronics and
Electrical Engineering for allowing access to valuable lab facilities in the department.
Last but not the least, I would like to thank my parents whose constant motivation and
moral support kept my hopes alive even during the hardest phases of the project.

Shobhit Chaurasia
Roll No.11010179
Department of Computer Science and Engineering
Indian Institute of Technology, Guwahati

Page 1 of 30

CONTENTS

ACKNOWLEDGEMENT ...................................
ABSTRACT
...................................................
OBJECTIVE
...................................................
MOTIVATION ...................................................
INTRODUCTION
...........................................
XILINX SPARTAN 3E STARTER KIT ...................
ONBOARD ADC
...........................................
PROGRAMMABLE PRE-AMPLIFIER ...................
WORKING
...................................................
ARITHEMATIC OPERATIONS ...........................
VHDL CODE ...................................................
CONCLUSIONS AND FUTURE WORK
...........
REFERENCES ...................................................

Page 2 of 30

1
3
4
5
6
8
9
12
13
20
22
29
30

ABSTRACT
The objective of this project is to first interface the onboard ADC available on the
Spartan 3E FPGA platform (Xilinx Spartan 3E Starter Kit), so that the real-world analog
signals can be processed by the FPGA board, which deals only in digital signals. Further,
certain arithmetic operations like binary addition/subtraction and binary division are
performed on the digital output of the onboard-ADC to convert it into a more desirable
and usable value by making the digital output of the onboard-ADC directly proportional
to the input analog values. The hardware description language used is VHDL.
Thus, first of all, the ADC was interfaced and the results were observed via ChipScopePro. Then, simple binary-arithmetic operations are performed where internal registers
of the FPGA were used to store and process upon the values of the digital data
obtained, which were observed both via LEDs on the FPGA kit as well as ChipScope-Pro.

Page 3 of 30

OBJECTIVE
o The underlying objective of the present work is to interface the on-board ADC
(Analog to Digital Convertor) on Xilinx Spartan 3E Starter Kit with the real world
signals.
o In doing so one can build a complete embedded dummy system that can take the
real world signal and then convert it into digital format (via the onboard-ADC).
o Then process the data thus obtained, performing certain binary-arithmetic
operations on it, converting the digital data into a more suitable form.

Page 4 of 30

MOTIVATION
Today the world is moving towards a digital platform. Everything right from Cable
television to our cell phone is getting digitized. But, at the same time, it is to be seen
that all physical world signals available to us are still very much analog in nature. But
their processing obviously happens in the digital domain. So for such a wide a variety of
applications, it is of utmost importance that we have properly designed Analog-ToDigital Convertors (ADCs).
A FPGA (Field Programmable Gate Array) board can be used to perform a lot of
operations on the real world signals, be it simple arithmetic operations or complex
transforms. The primary motivation behind taking up this project is the large utility of
the digital signals on which a lot of operations and transforms, viz Short time Fourier
transform, Stockwell Transform, Wavelet transform etc. could be done, which are very
tedious and time consuming processes if the signals are in the analog domain.
Simultaneously we must also remember that all digital signals cannot be used directly,
as all the real world signals are more or less analog in nature. Hence, it is of utmost
importance that we are able to use the ADC (and in certain cases, if required, DAC as
well) effectively and frequently. Hence, the analysis and the results which follow in the
project try to interface the onboard-ADC of Xilinx Spartan 3E Starter Kit with the real
world signals (analog DC voltages in this case) and try to give an insight into the
capabilities of FPGA boards by operating on the digital data thus obtained, converting it
into a more suitable form, using VHDL as the hardware description language.

Page 5 of 30

INTRODUCTION
The onboard-ADC on the Xilinx Spartan 3E Starter Kit is manufactured by LINEAR
TECHNOLOGY LTD. The ADC chip used is LTC1407A. The ADC chip has two separate
channels, namely VINA and VINB, which are sampled simultaneously. The digital
representation of the sampled analog values is shown as a 14-bit, 2s complement
binary value by the ADC. The ADC gets the analog inputs from the outside world through
the J7 Header via a pre-amplifier. The pre-amplifier is LTC6912-1, also a product of
LINEAR TECHNOLOGY LTD. The purpose of the pre-amplifier is to scale the incoming
voltage on VINA or VINB so that it maximizes the conversion range. While designing and
interfacing of the onboard-ADC, a simple state machine, with a number of states, was
used. This state machine was coded in VHDL and programmed on the FPGA. The state
machine drove the pre-amplifier and ADC from one state to another, controlling the
timings of various signals to be fed to the pre-amplifier and the ADC and capturing the
output of ADC based on the SPI clock on which the pre-amplifier and ADC read the input
analog signals and sample the output.

Hardware and Software Used

The FPGA used was Xilinx Spartan 3E Starter Kit with onboard ADC (LTC 1407A). An
external DC Power Supply was used for providing analog input values to the onboardADC. The software package used for coding and interfacing of FPGA kit with PC was
Xilinx ISE 11.1 Design Suite. Programming was done in VHDL.

Testing Technology Used

For testing purpose, ChipScope Pro Analyzer, an integrated package of the Xilinx ISE
Design Suite was used as it helps to visualize the internal signals of the FPGA board,
which is not feasible otherwise through the onboard-LCD screen or external
oscilloscopes as these signals (like the output signals of the ADC) are internal to the
board and do not have external interfacing. LEDs present on the FPGA kit were also used
to visualize the binary outputs. ChipScope Pro Analyzer tool inserts logic analyzer,
system analyzer, and virtual Input/Output (I/O) low-profile software cores directly into
the design, allowing one to view any internal signal or node on the PC itself. Signals are
captured in the system at the speed of operation and brought out through the
programming interface, freeing up pins for the design.

Page 6 of 30

ChipScope Pro Analyzer supports a variety of download cables for communication

between computer and the devices in the JTAG (Joint Test Action Group) boundary scan
chain. Of these some are listed below:
o Platform Cable USB
o Parallel Cable IV
Platform cable USB is the one used in this case of Spartan 3E Starter kit. The program is
dumped into the FPGA and then the analysis is done via ChipScope Pro. ChipScope Pro
uses the JTAG chain for displaying the output waveforms on the computer screen.

Page 7 of 30

XILINX SPARTAN 3E STARTER

KIT
The Spartan 3E Starter Kit provides us the basic features as provided by the Spartan 3E
FPGA. It also provides easy way to test various programs in the FPGA itself, by dumping
the bit file into the FPGA and then observing the output. The Spartan 3E FPGA board
comes built in with many peripherals that help in the proper working of the board and
also in interfacing the various signals to the board itself. Some of the peripherals are :o 2-line, 16-character LCD screen: This LCD screen can be interfaced with the various
on-board signals of the FPGA to display various texts as desired by the
programmer.
o PS/2 mouse/keyboard port: PS/2 keyboard or mouse can be connected to the
FPGA board and then depending on the key pressed the FPGA would do a variety
of things as programmed.
o VGA display port: This port can be used to display various encoded images on an
external screen. The image encoding would be done by the FPGA via the aid of a
program and then the encoded image would be displayed on the screen.
o Two 9-pin RS-232 ports: This ports help in the transmission of serial data to and
from the FPGA board.
o 50 MHz clock oscillator: This is the onboard system clock which helps in giving the
clock signal to the various events taking place within the FPGA and the various
programs that require clock for their working, A Digital clock manager can also be
used to reduce the frequency of the system clock so that is useful for various other
purposes which need smaller clock frequency.
o On-board USB-based FPGA download and debug interface: The programmable file
is dumped into the FPGA via the USB based download cable.
o Eight discrete LEDs: The LEDs can be interfaced to glow when a particular output
becomes high.
o Four slide switches and four push-button switches: These switches are used to give
the inputs to the FPGA board. They can also act as the reset switches for the
various programs.
o Four-output, SPI-based Digital-to-Analog Converter (DAC): It is the on-board DAC
which can be interfaced to give analog output of the digital data values.
o Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
preamplifier.

Page 8 of 30

ONBOARD ADC
ADCs (Analog to Digital Convertor) are of various types. The one used for our purpose is
the Successive Approximation Type ADC (SAR-ADC), where the main components
include a DAC (digital to analog convertor), a clock, a comparator and a SAR register for
storing the values of the digital data which comes after the comparator compares the
values of the DAC with the analog input and outputs a 1 or a 0 depending on the
condition. Some of the salient features of the onboard ADC are:
o 3Msps (3 Mega Hertz sampling rate) Sampling: The onboard-ADC has two
simultaneous differential inputs. The sampling rate is divided into two channels of
1.5 Msps each.
o 3V Single Supply Operation: It takes its inputs from a supply of 3V DC.
o 1.25V Differential Input Range: The interim range of the ADC is 2.5 V (1.25V). The
input voltage range can be set by changing the gain parameters.
o 3-Wire Serial Interface: It communicates with the external data or the external
world via serial media or serial bus (SPI in case of LTC 1407A). This makes
communication very easy and simple.

Page 9 of 30

Figure 2: Block diagram of SAR- ADC.

Figure 3: Circuit Diagram of the LTC1407A ADC chip.

Page 10 of 30

Figure 4: Detailed View for the Analog capture circuit

Page 11 of 30

Programmable Pre-Amplifier
The LTC6912-1 provides two independent inverting amplifiers with programmable gain.
The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the ADC, namely 1.65 1.25V.

Figure 5: A Dual, Matched Low Noise PGA

The LTC6912 is a family of dual channel, low noise, digitally programmable gain
amplifiers (PGA). The gains for both channels are independently programmable using a
3-wire SPI interface to select voltage gains of 0, -1, -2, -5, -10, -20, -50 and -100. A halfsupply reference, generated internally at the AGND pin, supports single power supply
applications.

Page 12 of 30

WORKING
Communication Between FPGA and Preamplifier
Various interface signals are used for the interfacing of the amplifier with the FPGA. The
amplifier uses the SPI bus for communicating with the FPGA, and this SPI bus is shared
among a variety of other peripheral devices like the ADC, DAC, Strata Flash and the
Platform Flash. Hence the other interface signals to those devices must be suitably
disabled so that proper interaction of the bus with the pre-amplifier takes place. Some
of the SPI signals controlling the working of pre-amplifier are mentioned below:o SPI_MOSI: This signal is found at the pin T4 of the Spartan 3E FPGA kit. This signal is
directed from the FPGA to the ADC. It presents serial data. MOSI stands for Master
Output, Slave Input. It is mainly responsible for presenting the 8-bit programmable
gain settings. Based on this pre-loaded gain settings the conversion of the analog
value to digital value takes place. Also the input range to the ADC depends on this
gain setting.
o AMP_CS: This signal is found at the pin N7 of the Spartan 3E FPGA kit. This signal is
directed from the FPGA to the AMP. It is an active low chip select signal. The
amplifier gain is set when the signal returns high.
o SPI_SCK: This signal is found at the pin U16 of the Spartan 3E FPGA kit. This signal is
directed from the FPGA to the AMP. It is basically the clock signal depending on
which the gain setting is done. The SPI_MOSI signal sends one bit at a time at the
rising edge of the SPI_SCK clock. Also AMP_DOUT signal, which is described below,
echoes the gain setting beck to the FPGA at the falling edge of the SPI_SCK clock.
o AMP_SHDN: This signal is found at the pin P7 of the Spartan 3E FPGA kit. This signal
is directed from the FPGA to the AMP. It is an Active high shutdown, reset signal.
o AMP_DOUT: This signal is found at the pin E18 of the Spartan 3E FPGA kit. This
signal is directed from the AMP to the FPGA. This signal simply echoes the previous
amplifier gain settings back to the FPGA. It can be ignored in most of the cases. It
again presents data in serial data format.

Setting the Gain Values

The gain setting is done by programming the programmable pre-amplifier via SPI_MOSI.
The gain for each channel of the amplifier is sent as an 8-bit command word, consisting
of two 4-bit fields. The SPI bus transaction starts when the FPGA asserts AMP_CS Low.
The amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock
signal. This data is sent with MSB first, i.e. B3 bit is sent first and then the rest in order
to program the gain of the amplifier. A pre-defined table sets the gain value according
to the bits given to the gain register. The permissible gains and the corresponding
Page 13 of 30

settings are given in the Table 1. Serial interface timing diagram for the signals of
amplifier is shown in Figure 8 along with the corresponding Table 2.

Gain
0
-1
-2
-5
-10
-20
-100

A3
B3
0
0
0
0
0
0
0

A2
B2
0
0
0
0
1
1
1

A1
B1
0
0
1
1
0
1
1

A0
B0
0
1
0
1
0
0
1

Input Voltage Range

Minimum Maximum
0.4
1.025
1.4
1.5875
1.625
1.6375

2.9
2.275
1.9
1.7125
1.675
1.6625

Table 1: The Gain settings along with the input voltage range and register values

A0

A1

A2

A3

B0

A Gain

B1

B2

B Gain

Figure 7: Diagram for gain register settings via the A gain and the B gain.

Page 14 of 30

B3

Figure 8: Serial interface timing diagram for applying gain settings to pre-amplifier.

SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9

PARAMETER
DIN Valid to CLK Setup
DIN Valid to CLK Hold
CLK Low
CLK High
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
DOUT Output Delay
CLK Low to CS/LD Low

MIN
60
0
100
100
60
60
30

MAX

125
0

Table 2: The timing ranges corresponding to Figure 8.

Page 15 of 30

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns

Working of ADC
ADC presents a 14-bit, 2s complement digital output of the analog input. The input
voltage given to the ADC depends on the programmable gain settings of the preamplifier. The maximum input range is for the gain = -1 for which the input voltage
range from 0.4V to 2.9V. The Analog to Digital Conversion formula is given below:

Here D [13:0] represents the 14 bit twos complement value of the analog input. It is
output to the FPGA from the ADC via the SPI_MISO signal, as will be discussed later in
the interfacing signals of the FPGA and the ADC. GAIN is the gain setting given via the
programming of the gain register bit by bit. VIN is the input voltage to the ADC. 1.65V is
the reference voltage of the ADC. This is achieved by the voltage divider circuit provided
in the ADC circuit (dividing the Vcc which is 3.3V). The range of the ADC used is 1.25V.
Hence the output is scaled by 1.25V. Also the output obtained is in 14 bit 2s
complement form and hence the output is scaled by 8192. Both the input channels
[VIN(A) and VIN(B)] are sampled simultaneously.

Communication Between FPGA and ADC

o AD_CONV: This signal is active high shutdown and reset signal. This signal marks the
beginning of the conversion of the analog signal. It is an internal signal of the FPGA
board, which cant be viewed with the help of an external oscilloscope. Pin P11 is
responsible for this signal. This signal is directed from FPGA to ADC.
o SPI_MISO: This signal is the serial data output from the ADC chip to the FPGA board.
It is the one that gives the digital representation of the sampled analog value as 14bit 2s complement binary value. It is again an internal signal and pin N10 is
responsible for this signal. This signal is directed from FPGA to ADC.
o SPI_SCK: As described earlier, this is the clock signal which plays an important role
in the analog to digital conversion process and also sending the data from the ADC
unit to the FPGA.

Controlling the ADC Through VHDL Coding

The serial interface sends out the two conversion results in 32 clock-cycles for
compatibility with standard serial interfaces. Two 14 bit results are obtained from the
ADC. The AD_CONV signal is not a traditional SPI slave select enable. Provisions should
be made to provide enough SPI_SCK clock cycles so that the ADC leaves the SPI_MISO
signal in the high impedance state. Otherwise, the ADC blocks communication to the
other SPI peripherals. The ADC tri-states its data output for two clock cycles before and
after each 14-bit data transfer (hence a total of 34 clock sequence is used).
Page 16 of 30

The SPI bus signals are shared by other devices on the board. It is vital that other
peripheral devices are disabled when the FPGA communicates with the AMP or ADC to
avoid bus contention. Whenever the AD_CONV signal goes high, the Analog to Digital
Converter (ADC) simultaneously samples both analog channels. The results of this
conversion are not presented until the next time AD_CONV is asserted on the SPI bus,
thus creating a latency of one sample. The maximum sample rate is approximately
1.5MHz. Serial interface timing diagram for the signals of amplifier is shown in Figure 9
along with the corresponding Table 3 on next page.

Page 17 of 30

Figure 9: Serial interface timing diagram for ADC conversion and sampling.
Page 18 of 30

SYMBOL

MIN

tSCK

PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisition
Period)
Clock Period

tCONV

Conversion Time

32

t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t12

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time
SCK Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
32nd SCK(up) to CONV(up) Interval
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
VREF Settling Time After Sleep-to-Wake Transition

2
3
0
4
4
1.2
45
8
6
2
2

fSAMPLE(MAX)
tTHROUGHPUT

667
19.6

UNITS
MHz

1.5

Table 3: The timing ranges corresponding to Figure 9.

Page 19 of 30

MAX

ns

ns
SCLK
cycles
ns
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000

ARITHEMATIC OPERATIONS
Through state-machine built in VHDL language meeting all the timing constraints of the
different SPI interface signals, a 14-bit 2s complement binary form of the analog input
voltages can be obtained through the SPI_MISO signal of ADC bit-by-bit. This binary
output is governed by the following relation:

Due to the in-built 1.65V reference of the pre-amplifier, the digital output is not directly
proportional to the analog input; it has an offset. Removing this offset-error makes the
digital data more convenient to use. The following error manipulation can be employed
to remove this offset.

Error Manipulation

Now, if GAIN = (-1), we get:

In 14-bit 2s complement binary format:

where,
D so obtained is directly proportional to the input analog voltage; with the offset
removed.

Calculating Va/Vb
As discussed earlier, an FPGA can be used to perform even complex computations. We
can have an insight into the internal computational power of FPGA by performing a
simple 14-bit 2complement binary division operation using the internal registers of the
FPGA. DA[13:0] and DB[13:0] are already known to us. We will perform binary division
on the two to compute VA/VB. Note that since DA[13:0] and DB[13:0] are directly
Page 20 of 30

proportional to VA and VB respectively, DA/DB will be equal to VA/VB. This ratio of input
voltages can be used for many further computations and as an input to many control
systems like Fuzzy-Logic Controller or for Digital Pulse-Width Modulation etc.
Restoring Division Algorithm is used for computing the quotient and remainder of the
binary division under consideration.
Consider the binary division x/y, where x and y are binary numbers.
Put x in register A, y in register B, initialize register P with all bits as 0 and perform n
division steps (n is the quotient bit-count). Each step consists of:
o Shift the register pair (P, A) one bit left.
o Subtract the contents of B from P and put the result back in P.
o If the result is -ve, set the low-order bit of A to 0 and restore the old value of P by
adding the contents of B back in P.
o If the result is +ve, set the lowest-order bit of A to 1.
o Repeat the above steps until all the bits of A have been replaced.
o A is the quotient and P is the remainder.
It is called restoring division algorithm because if subtraction by B yields a negative
result, the register P is restored by adding B back.
For example:
P
A
Operation
00000
1110
Divide 14 = 1110 by 3 = 11. B register always contains 0011
00001
110
step 1(i): shift
-00011
step 1(ii): subtract
----------00010
1100
step 1(iii): quotient is negative, set quotient bit to 0
00001
1100
step 1(iv): restore
00011
100
step 2(i): shift
-00011
step 2(ii): subtract
---------00000
1001
step 2(iii): quotient is positive, set quotient bit to 1
00001
001
step 3(i): shift
-00011
step 3(ii): subtract
----------00010
0010
step 3(iii): quotient is positive, set quotient bit to 0
00001
0010
step 3(iv): restore
00010
010
step 4(i): shift
-00011
step 4(ii): subtract
----------00001
0100
step 4(iii): quotient is positive, set quotient bit to 0
00010
0100
step 4(iv): restore
The quotient is 0100 and the remainder is 00010
Page 21 of 30

VHDL CODE
---------------------------------------------------------------------------------- University: IIT Guwahati
-- Engineer: Shobhit Chaurasia
--- Create Date:
18:38:35 06/20/2012
-- Design Name:
-- Module Name:
adc - Behavioral
-- Project Name:
Implementation of ADC on Xilinx FPGA
-- Target Devices: Xilinx Spartan 3E Starter Kit
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- The restoring division module is added separately
--------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adc is
port (enable
led_enable
clk_50
SPI_MISO
AD_CONV
AMP_CS
SPI_MOSI
SPI_SCK
LED
AMP_SHDN
SPI_SS_B
SF_CE0
FPGA_INIT_B
DAC_CS
);
end adc;

:
:
:
:
:
:
:
:
:
:
:
:
:
:

in std_logic;
--Switch to start preamp and adc
in std_logic;
in std_logic;
in std_logic;
out std_logic; --SPI-bus for ADC
out std_logic; --SPI-bus for preamp
out std_logic;
out std_logic;
out signed(7 downto 0);
out std_logic; --preamp
out std_logic; --SPI-bus for other device
out std_logic; --SPI-bus for other device
out std_logic; --SPI-bus for other device
out std_logic
--SPI-bus for DAC

architecture Behavioral of adc is

type state_type
is (amp_state, adc_state);
type amp_state_type is (IDLE, START, HI, DUMMY_LO, LO, NOTHING);

Page 22 of 30

type adc_state_type is (IDLE_AD,

START_AD,LO_AD,HI_AD,FINE_AD,ERROR_MANIPULATE);
signal state: state_type:= amp_state;
signal amp_state_reg
: amp_state_type := IDLE;
signal adc_state_reg
: adc_state_type := IDLE_AD;
signal sck_reg
: std_logic:='0';
signal clk_div
: std_logic :='0';
signal risingedge : std_logic := '1';
signal clk_counter: integer range 0 to 25:=0;
signal ADC1
: signed(13 downto 0); --VINA
signal ADC2
: signed(13 downto 0); --VINB
signal error
: signed(14 downto 0) :="101010111000011"; --error
constant in decimal form is -10813
signal ADC1_correct: signed(14 downto 0); --directly proportional to
VINA
signal ADC2_correct: signed(14 downto 0); --directly proportional to
VINB
begin
--process for clock divider
--2 MHz clock
process (clk_50)
begin
if(clk_50'event and clk_50 ='1') then
if(clk_counter = 25) then
risingedge <= risingedge xor '1';
clk_div <= clk_div xor '1';
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
end if;
end if;
end process;
--deactivte other device SPI-bus
SPI_SS_B <= '0'; --value given in Xilinx datasheet is wrong
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
DAC_CS <= '1';
--START PROCESS PREAMP - ADC
process(clk_50)
variable enable2
:integer range 0 to 2:=0;
variable first
: integer range 0 to 1:=0;
variable dummy_counter :integer :=0;
variable count
: integer range 0 to 17; -- 14 bits for 1 ADC
channel + 2 for zero
variable counter
: integer range 0 to 34; -- 34 SPI_SCK clock
changes for an entire ADC-loop
variable gaincount
: integer range 0 to 7; -- 8 bits preamp signal
constant gain_temp
: std_logic_vector (7 downto 0):= "00010001"; - largest range of preamp
begin
if (clk_50'event and clk_50 ='1') then
if(clk_counter=25 and risingedge='1') then

Page 23 of 30

case state is
--START AMP CYCLE
when amp_state =>
case amp_state_reg is
when IDLE =>
gaincount:=7;
if (enable='1') then
sck_reg<='0';
AMP_SHDN <= '0';
amp_state_reg <= START;
else
AMP_SHDN <= '1';
AMP_CS <= '1';
amp_state_reg <= IDLE;
end if;
when START =>
AMP_SHDN <= '0';
sck_reg <= '0';
SPI_MOSI <= '0';
counter := 0;
AMP_CS <= '0';
if(dummy_counter=1) then --for the
min 30ns between amp_cs=1 and sck high
amp_state_reg <= HI;
dummy_counter :=0;
else
dummy_counter := dummy_counter+1;
amp_state_reg <=START;
end if;
when HI =>
if(dummy_counter=1)then
sck_reg <= '1';
counter := counter+1;
amp_state_reg <= DUMMY_LO;
dummy_counter:=0;
else
SPI_MOSI <= gain_temp(gaincount);
-- for spi_mosi to be ready min 30ns before rising sck
dummy_counter:=dummy_counter+1;
amp_state_reg <=HI;
end if;
when DUMMY_LO =>
if (counter=8) then
amp_state_reg<=LO;
else
sck_reg<='1';
amp_state_reg <= LO;
end if;
when LO =>
if counter = 8 then
AMP_SHDN <= '0'; --if we
assert amp_shdn high, we need to reprogram gain everytime

Page 24 of 30

amp_state_reg <= NOTHING;

SPI_MOSI <= '0';
AMP_CS <= '1';
gaincount := 7;
sck_reg <= '0';
state <= adc_state;
else
sck_reg <= '0';
gaincount := gaincount-1;
amp_state_reg <= HI;
AMP_CS<='0';
--although not
required as already done
end if;
when NOTHING =>
AMP_CS <= '1';
when others =>
amp_state_reg <= IDLE;
end case;
--START ADC CYCLE
when adc_state =>
AMP_CS<='1';
case adc_state_reg is
when IDLE_AD =>
counter := 0;
sck_reg <= '0';
-If (enable = '0') then
AD_CONV <= '0';
AMP_SHDN <='1';
state <= amp_state;
amp_state_reg <= IDLE;
else
adc_state_reg <= START_AD;
AD_CONV <= '1';
end if;
when START_AD =>
sck_reg <= '0';
AD_CONV <= '0';
count := 17;
adc_state_reg <=LO_AD;
when LO_AD =>
sck_reg<='0';
if count > 0 then
count := count-1;
end if;
counter := counter+1;
adc_state_reg <=HI_AD;
when HI_AD =>

Page 25 of 30

sck_reg <= '1';

if counter <= 2 then
adc_state_reg <= LO_AD; --for
2 clock cycles before
elsif counter > 2 and counter <= 16 then
ADC1(count) <= SPI_MISO;
adc_state_reg <= LO_AD;
elsif counter > 16 and counter <= 18 then
count:=15;
adc_state_reg <= LO_AD;
elsif counter > 18 and counter <=32 then
ADC2(count) <= SPI_MISO;
adc_state_reg <= LO_AD;
elsif counter = 33 then
adc_state_reg <= LO_AD; --for 2
cycles after
else
if(enable2=1) then
first:=1;
end if;
adc_state_reg <= FINE_AD;
end if;
when FINE_AD =>
counter := 0;
count := 17;
sck_reg <= '0';
adc_state_reg <= ERROR_MANIPULATE;
if(first=0) then
enable2:=1;
elsif(first=1) then
enable2:=2;
end if;
when ERROR_MANIPULATE =>
ADC1_correct<=error+(ADC1(13) & ADC1);
ADC2_correct<=error+(ADC2(13) & ADC2);
adc_state_reg <= IDLE_AD;
when others =>
adc_state_reg <= IDLE_AD;
end case;
end case;
end if;
end if;
if (first=1 and led_enable='0') then
LED <= ADC1_correct(14 downto 7);
elsif(first=1 and led_enable='1') then
LED(7) <= ADC1_correct(6);
LED(6) <= ADC1_correct(5);
LED(5) <= ADC1_correct(4);
LED(4) <= ADC1_correct(3);
LED(3) <= ADC1_correct(2);
LED(2) <= ADC1_correct(1);
LED(1) <= ADC1_correct(0);
LED(0) <= '0';

Page 26 of 30

end if;
end process;
SPI_SCK <= sck_reg;
end Behavioral;

Vhdl Module For Restoring Division Algorithm

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
function
variable
variable
variable
variable

-- for UNSIGNED

divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is

a1 : unsigned(a'length-1 downto 0):=a;
b1 : unsigned(b'length-1 downto 0):=b;
p1 : unsigned(b'length downto 0):= (others => '0');
i : integer:=0;

begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;

UCF Constraints
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

"enable" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

"led_enable" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
"led_enable" CLOCK_DEDICATED_ROUTE = FALSE;
"clk_50" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
"SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
"AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
"SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
"AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
"SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
"SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
"SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
"FPGA_INIT_B" LOC ="T3" | IOSTANDARD = LVCMOS33 | SLEW=SLOW | DRIVE = 4 ;
"DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
"LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
"LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

Page 27 of 30

NET
NET
NET
NET
NET

"LED<3>"
"LED<4>"
"LED<5>"
"LED<6>"
"LED<7>"

LOC
LOC
LOC
LOC
LOC

=
=
=
=
=

"F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

"C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
"D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
"E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
"F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

The above three modules were integrated in a Xilinx ISE project and the project was
successfully executed, simulated, dumped on the FPGA board and tested using
ChipScope Pro Analyzer (to analyze clock-pulse and waveforms of other signals) and
with the help of onboard LEDs to visualize the output.

Page 28 of 30

CONCLUSIONS AND FUTURE

WORK
Conclusion
o The onboard ADC of the Spartan 3E Starter Kit FPGA Board was properly interfaced
with real world signals.
o ChipScope-Pro Analyzer was used to analyze the internal signals.
o The ADC was analyzed for a constant voltage supply.
o It was observed that the ADC output signal as seen through ChipScope-Pro
Analyzer and the value theoretically calculated were almost same.

Future Work
o The standalone implementation of ADC could be integrated in different projects
and used.
o A similar implementation of the onboard DAC could be achieved and used in
conjunction with ADC for numerous applications like Fast Fourier Transforms,
implementation of Fuzzy Logic control using FPGA etc.

Page 29 of 30

REFERNCES
o Xilinx,

Spartan-3E

FPGA

starter

kit

Board

User

Guide,

Internet:

http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf

o Linear

Technology

Limited,

Datasheet

of

LTC

1407-1,

Internet:

6912,

Internet:

http://cds.linear.com/docs/Datasheet/14071fb.pdf

o Linear

Technology

Limited,

Datasheet

http://cds.linear.com/docs/Datasheet/6912fa.pdf

Page 30 of 30

of

LTC